icp_qat_fw_loader_handle.h

 1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
 2/* Copyright(c) 2014 - 2020 Intel Corporation */
 3#ifndef __ICP_QAT_FW_LOADER_HANDLE_H__
 4#define __ICP_QAT_FW_LOADER_HANDLE_H__
 5#include "icp_qat_uclo.h"
 6
 7struct icp_qat_fw_loader_ae_data {
 8	unsigned int state;
 9	unsigned int ustore_size;
10	unsigned int free_addr;
11	unsigned int free_size;
12	unsigned int live_ctx_mask;
13};
14
15struct icp_qat_fw_loader_hal_handle {
16	struct icp_qat_fw_loader_ae_data aes[ICP_QAT_UCLO_MAX_AE];
17	unsigned int ae_mask;
18	unsigned int admin_ae_mask;
19	unsigned int slice_mask;
20	unsigned int revision_id;
21	unsigned int ae_max_num;
22	unsigned int upc_mask;
23	unsigned int max_ustore;
24};
25
26struct icp_qat_fw_loader_chip_info {
27	int mmp_sram_size;
28	bool nn;
29	bool lm2lm3;
30	u32 lm_size;
31	u32 icp_rst_csr;
32	u32 icp_rst_mask;
33	u32 glb_clk_enable_csr;
34	u32 misc_ctl_csr;
35	u32 wakeup_event_val;
36	bool fw_auth;
37	bool css_3k;
38	bool dual_sign;
39	bool tgroup_share_ustore;
40	u32 fcu_ctl_csr;
41	u32 fcu_sts_csr;
42	u32 fcu_dram_addr_hi;
43	u32 fcu_dram_addr_lo;
44	u32 fcu_loaded_ae_csr;
45	u8 fcu_loaded_ae_pos;
46};
47
48struct icp_qat_fw_loader_handle {
49	struct icp_qat_fw_loader_hal_handle *hal_handle;
50	struct icp_qat_fw_loader_chip_info *chip_info;
51	struct pci_dev *pci_dev;
52	void *obj_handle;
53	void *sobj_handle;
54	void *mobj_handle;
55	unsigned int cfg_ae_mask;
56	void __iomem *hal_sram_addr_v;
57	void __iomem *hal_cap_g_ctl_csr_addr_v;
58	void __iomem *hal_cap_ae_xfer_csr_addr_v;
59	void __iomem *hal_cap_ae_local_csr_addr_v;
60	void __iomem *hal_ep_csr_addr_v;
61};
62
63struct icp_firml_dram_desc {
64	void __iomem *dram_base_addr;
65	void *dram_base_addr_v;
66	dma_addr_t dram_bus_addr;
67	u64 dram_size;
68};
69#endif