icp_qat_fw_la.h

  1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
  2/* Copyright(c) 2014 - 2020 Intel Corporation */
  3#ifndef _ICP_QAT_FW_LA_H_
  4#define _ICP_QAT_FW_LA_H_
  5#include "icp_qat_fw.h"
  6
  7enum icp_qat_fw_la_cmd_id {
  8	ICP_QAT_FW_LA_CMD_CIPHER = 0,
  9	ICP_QAT_FW_LA_CMD_AUTH = 1,
 10	ICP_QAT_FW_LA_CMD_CIPHER_HASH = 2,
 11	ICP_QAT_FW_LA_CMD_HASH_CIPHER = 3,
 12	ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4,
 13	ICP_QAT_FW_LA_CMD_TRNG_TEST = 5,
 14	ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6,
 15	ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7,
 16	ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8,
 17	ICP_QAT_FW_LA_CMD_MGF1 = 9,
 18	ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10,
 19	ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11,
 20	ICP_QAT_FW_LA_CMD_DELIMITER = 12
 21};
 22
 23#define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
 24#define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
 25#define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
 26#define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
 27
 28struct icp_qat_fw_la_bulk_req {
 29	struct icp_qat_fw_comn_req_hdr comn_hdr;
 30	struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
 31	struct icp_qat_fw_comn_req_mid comn_mid;
 32	struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
 33	struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
 34};
 35
 36#define ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE 1
 37#define QAT_LA_SLICE_TYPE_BITPOS 14
 38#define QAT_LA_SLICE_TYPE_MASK 0x3
 39#define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1
 40#define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0
 41#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12
 42#define ICP_QAT_FW_LA_ZUC_3G_PROTO 1
 43#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1
 44#define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11
 45#define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1
 46#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1
 47#define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0
 48#define QAT_LA_DIGEST_IN_BUFFER_BITPOS	10
 49#define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1
 50#define ICP_QAT_FW_LA_SNOW_3G_PROTO 4
 51#define ICP_QAT_FW_LA_GCM_PROTO	2
 52#define ICP_QAT_FW_LA_CCM_PROTO	1
 53#define ICP_QAT_FW_LA_NO_PROTO 0
 54#define QAT_LA_PROTO_BITPOS 7
 55#define QAT_LA_PROTO_MASK 0x7
 56#define ICP_QAT_FW_LA_CMP_AUTH_RES 1
 57#define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0
 58#define QAT_LA_CMP_AUTH_RES_BITPOS 6
 59#define QAT_LA_CMP_AUTH_RES_MASK 0x1
 60#define ICP_QAT_FW_LA_RET_AUTH_RES 1
 61#define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0
 62#define QAT_LA_RET_AUTH_RES_BITPOS 5
 63#define QAT_LA_RET_AUTH_RES_MASK 0x1
 64#define ICP_QAT_FW_LA_UPDATE_STATE 1
 65#define ICP_QAT_FW_LA_NO_UPDATE_STATE 0
 66#define QAT_LA_UPDATE_STATE_BITPOS 4
 67#define QAT_LA_UPDATE_STATE_MASK 0x1
 68#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0
 69#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1
 70#define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3
 71#define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1
 72#define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0
 73#define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1
 74#define QAT_LA_CIPH_IV_FLD_BITPOS 2
 75#define QAT_LA_CIPH_IV_FLD_MASK   0x1
 76#define ICP_QAT_FW_LA_PARTIAL_NONE 0
 77#define ICP_QAT_FW_LA_PARTIAL_START 1
 78#define ICP_QAT_FW_LA_PARTIAL_MID 3
 79#define ICP_QAT_FW_LA_PARTIAL_END 2
 80#define QAT_LA_PARTIAL_BITPOS 0
 81#define QAT_LA_PARTIAL_MASK 0x3
 82#define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \
 83	cmp_auth, ret_auth, update_state, \
 84	ciph_iv, ciphcfg, partial) \
 85	(((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \
 86	QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \
 87	((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \
 88	QAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \
 89	((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \
 90	QAT_LA_DIGEST_IN_BUFFER_BITPOS) | \
 91	((proto & QAT_LA_PROTO_MASK) << \
 92	QAT_LA_PROTO_BITPOS)	| \
 93	((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \
 94	QAT_LA_CMP_AUTH_RES_BITPOS) | \
 95	((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \
 96	QAT_LA_RET_AUTH_RES_BITPOS) | \
 97	((update_state & QAT_LA_UPDATE_STATE_MASK) << \
 98	QAT_LA_UPDATE_STATE_BITPOS) | \
 99	((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \
100	QAT_LA_CIPH_IV_FLD_BITPOS) | \
101	((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \
102	QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \
103	((partial & QAT_LA_PARTIAL_MASK) << \
104	QAT_LA_PARTIAL_BITPOS))
105
106#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \
107	QAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \
108	QAT_LA_CIPH_IV_FLD_MASK)
109
110#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \
111	QAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
112	QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
113
114#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \
115	QAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
116	QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
117
118#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \
119	QAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
120	QAT_LA_GCM_IV_LEN_FLAG_MASK)
121
122#define ICP_QAT_FW_LA_PROTO_GET(flags) \
123	QAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK)
124
125#define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \
126	QAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \
127	QAT_LA_CMP_AUTH_RES_MASK)
128
129#define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \
130	QAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \
131	QAT_LA_RET_AUTH_RES_MASK)
132
133#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \
134	QAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
135	QAT_LA_DIGEST_IN_BUFFER_MASK)
136
137#define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \
138	QAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \
139	QAT_LA_UPDATE_STATE_MASK)
140
141#define ICP_QAT_FW_LA_PARTIAL_GET(flags) \
142	QAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \
143	QAT_LA_PARTIAL_MASK)
144
145#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \
146	QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \
147	QAT_LA_CIPH_IV_FLD_MASK)
148
149#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \
150	QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
151	QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
152
153#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \
154	QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
155	QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
156
157#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \
158	QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
159	QAT_LA_GCM_IV_LEN_FLAG_MASK)
160
161#define ICP_QAT_FW_LA_PROTO_SET(flags, val) \
162	QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \
163	QAT_LA_PROTO_MASK)
164
165#define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \
166	QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \
167	QAT_LA_CMP_AUTH_RES_MASK)
168
169#define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \
170	QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \
171	QAT_LA_RET_AUTH_RES_MASK)
172
173#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \
174	QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
175	QAT_LA_DIGEST_IN_BUFFER_MASK)
176
177#define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \
178	QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \
179	QAT_LA_UPDATE_STATE_MASK)
180
181#define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \
182	QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
183	QAT_LA_PARTIAL_MASK)
184
185#define ICP_QAT_FW_LA_SLICE_TYPE_SET(flags, val) \
186	QAT_FIELD_SET(flags, val, QAT_LA_SLICE_TYPE_BITPOS, \
187	QAT_LA_SLICE_TYPE_MASK)
188
189struct icp_qat_fw_cipher_req_hdr_cd_pars {
190	union {
191		struct {
192			__u64 content_desc_addr;
193			__u16 content_desc_resrvd1;
194			__u8 content_desc_params_sz;
195			__u8 content_desc_hdr_resrvd2;
196			__u32 content_desc_resrvd3;
197		} s;
198		struct {
199			__u32 cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
200		} s1;
201	} u;
202};
203
204struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {
205	union {
206		struct {
207			__u64 content_desc_addr;
208			__u16 content_desc_resrvd1;
209			__u8 content_desc_params_sz;
210			__u8 content_desc_hdr_resrvd2;
211			__u32 content_desc_resrvd3;
212		} s;
213		struct {
214			__u32 cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
215		} sl;
216	} u;
217};
218
219struct icp_qat_fw_cipher_cd_ctrl_hdr {
220	__u8 cipher_state_sz;
221	__u8 cipher_key_sz;
222	__u8 cipher_cfg_offset;
223	__u8 next_curr_id;
224	__u8 cipher_padding_sz;
225	__u8 resrvd1;
226	__u16 resrvd2;
227	__u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];
228};
229
230struct icp_qat_fw_auth_cd_ctrl_hdr {
231	__u32 resrvd1;
232	__u8 resrvd2;
233	__u8 hash_flags;
234	__u8 hash_cfg_offset;
235	__u8 next_curr_id;
236	__u8 resrvd3;
237	__u8 outer_prefix_sz;
238	__u8 final_sz;
239	__u8 inner_res_sz;
240	__u8 resrvd4;
241	__u8 inner_state1_sz;
242	__u8 inner_state2_offset;
243	__u8 inner_state2_sz;
244	__u8 outer_config_offset;
245	__u8 outer_state1_sz;
246	__u8 outer_res_sz;
247	__u8 outer_prefix_offset;
248};
249
250struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
251	__u8 cipher_state_sz;
252	__u8 cipher_key_sz;
253	__u8 cipher_cfg_offset;
254	__u8 next_curr_id_cipher;
255	__u8 cipher_padding_sz;
256	__u8 hash_flags;
257	__u8 hash_cfg_offset;
258	__u8 next_curr_id_auth;
259	__u8 resrvd1;
260	__u8 outer_prefix_sz;
261	__u8 final_sz;
262	__u8 inner_res_sz;
263	__u8 resrvd2;
264	__u8 inner_state1_sz;
265	__u8 inner_state2_offset;
266	__u8 inner_state2_sz;
267	__u8 outer_config_offset;
268	__u8 outer_state1_sz;
269	__u8 outer_res_sz;
270	__u8 outer_prefix_offset;
271};
272
273#define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
274#define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0
275#define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX	240
276#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \
277	(sizeof(struct icp_qat_fw_la_cipher_req_params_t))
278#define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
279
280struct icp_qat_fw_la_cipher_req_params {
281	__u32 cipher_offset;
282	__u32 cipher_length;
283	union {
284		__u32 cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
285		struct {
286			__u64 cipher_IV_ptr;
287			__u64 resrvd1;
288		} s;
289	} u;
290};
291
292struct icp_qat_fw_la_auth_req_params {
293	__u32 auth_off;
294	__u32 auth_len;
295	union {
296		__u64 auth_partial_st_prefix;
297		__u64 aad_adr;
298	} u1;
299	__u64 auth_res_addr;
300	union {
301		__u8 inner_prefix_sz;
302		__u8 aad_sz;
303	} u2;
304	__u8 resrvd1;
305	__u8 hash_state_sz;
306	__u8 auth_res_sz;
307} __packed;
308
309struct icp_qat_fw_la_auth_req_params_resrvd_flds {
310	__u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];
311	union {
312		__u8 inner_prefix_sz;
313		__u8 aad_sz;
314	} u2;
315	__u8 resrvd1;
316	__u16 resrvd2;
317};
318
319struct icp_qat_fw_la_resp {
320	struct icp_qat_fw_comn_resp_hdr comn_resp;
321	__u64 opaque_data;
322	__u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
323};
324
325#define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \
326	((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \
327	  ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
328
329#define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
330{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \
331	((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
332	& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
333	((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
334	& ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
335
336#define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \
337	(((cd_ctrl_hdr_t)->next_curr_id_cipher) \
338	& ICP_QAT_FW_COMN_CURR_ID_MASK)
339
340#define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \
341{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \
342	((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
343	& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
344	((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
345
346#define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \
347	((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
348	>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
349
350#define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
351{ (cd_ctrl_hdr_t)->next_curr_id_auth = \
352	((((cd_ctrl_hdr_t)->next_curr_id_auth) \
353	& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
354	((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
355	& ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
356
357#define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \
358	(((cd_ctrl_hdr_t)->next_curr_id_auth) \
359	& ICP_QAT_FW_COMN_CURR_ID_MASK)
360
361#define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \
362{ (cd_ctrl_hdr_t)->next_curr_id_auth = \
363	((((cd_ctrl_hdr_t)->next_curr_id_auth) \
364	& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
365	((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
366
367#endif