adf_gen6_ras.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright(c) 2025 Intel Corporation */
  3#ifndef ADF_GEN6_RAS_H_
  4#define ADF_GEN6_RAS_H_
  5
  6#include <linux/bits.h>
  7
  8struct adf_ras_ops;
  9
 10/* Error source registers */
 11#define ADF_GEN6_ERRSOU0	0x41A200
 12#define ADF_GEN6_ERRSOU1	0x41A204
 13#define ADF_GEN6_ERRSOU2	0x41A208
 14#define ADF_GEN6_ERRSOU3	0x41A20C
 15
 16/* Error source mask registers */
 17#define ADF_GEN6_ERRMSK0	0x41A210
 18#define ADF_GEN6_ERRMSK1	0x41A214
 19#define ADF_GEN6_ERRMSK2	0x41A218
 20#define ADF_GEN6_ERRMSK3	0x41A21C
 21
 22/* ERRSOU0 Correctable error mask */
 23#define ADF_GEN6_ERRSOU0_MASK				BIT(0)
 24
 25#define ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT			BIT(0)
 26#define ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT		BIT(1)
 27#define ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT		BIT(2)
 28#define ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT		BIT(3)
 29#define ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT	        BIT(4)
 30
 31#define ADF_GEN6_ERRSOU1_MASK ( \
 32	(ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT)	| \
 33	(ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT)	| \
 34	(ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT)	| \
 35	(ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT)	| \
 36	(ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT))
 37
 38#define ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT			BIT(0)
 39#define ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT		BIT(1)
 40#define ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT		BIT(2)
 41#define ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT		BIT(3)
 42#define ADF_GEN6_ERRMSK1_IOSFCMD_PARERR_BIT	        BIT(4)
 43
 44#define ADF_GEN6_ERRMSK1_MASK ( \
 45	(ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT)	| \
 46	(ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT)	| \
 47	(ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT)	| \
 48	(ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT)	| \
 49	(ADF_GEN6_ERRMSK1_IOSFCMD_PARERR_BIT))
 50
 51/* HI AE Uncorrectable error log */
 52#define ADF_GEN6_HIAEUNCERRLOG_CPP0			0x41A300
 53
 54/* HI AE Uncorrectable error log enable */
 55#define ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0		0x41A320
 56
 57/* HI AE Correctable error log */
 58#define ADF_GEN6_HIAECORERRLOG_CPP0			0x41A308
 59
 60/* HI AE Correctable error log enable */
 61#define ADF_GEN6_HIAECORERRLOGENABLE_CPP0		0x41A318
 62
 63/* HI CPP Agent Command parity error log */
 64#define ADF_GEN6_HICPPAGENTCMDPARERRLOG			0x41A310
 65
 66/* HI CPP Agent command parity error logging enable */
 67#define ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE		0x41A314
 68
 69#define ADF_6XXX_HICPPAGENTCMDPARERRLOG_MASK		0x1B
 70
 71/* RI Memory parity error status register */
 72#define ADF_GEN6_RIMEM_PARERR_STS			0x41B128
 73
 74/* RI Memory parity error reporting enable */
 75#define ADF_GEN6_RI_MEM_PAR_ERR_EN0			0x41B12C
 76
 77/*
 78 * RI Memory parity error mask
 79 * BIT(4) - ri_tlq_phdr parity error
 80 * BIT(5) - ri_tlq_pdata parity error
 81 * BIT(6) - ri_tlq_nphdr parity error
 82 * BIT(7) - ri_tlq_npdata parity error
 83 * BIT(8) - ri_tlq_cplhdr parity error
 84 * BIT(10) - BIT(13) - ri_tlq_cpldata[0:3] parity error
 85 * BIT(19) - ri_cds_cmd_fifo parity error
 86 * BIT(20) - ri_obc_ricpl_fifo parity error
 87 * BIT(21) - ri_obc_tiricpl_fifo parity error
 88 * BIT(22) - ri_obc_cppcpl_fifo parity error
 89 * BIT(23) - ri_obc_pendcpl_fifo parity error
 90 * BIT(24) - ri_cpp_cmd_fifo parity error
 91 * BIT(25) - ri_cds_ticmd_fifo parity error
 92 * BIT(26) - riti_cmd_fifo parity error
 93 * BIT(27) - ri_int_msixtbl parity error
 94 * BIT(28) - ri_int_imstbl parity error
 95 * BIT(30) - ri_kpt_fuses parity error
 96 */
 97#define ADF_GEN6_RIMEM_PARERR_FATAL_MASK \
 98	(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | \
 99	 BIT(7) | BIT(8) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \
100	 BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27) | \
101	 BIT(28) | BIT(30))
102
103#define ADF_GEN6_RIMEM_PARERR_CERR_MASK \
104	(BIT(10) | BIT(11) | BIT(12) | BIT(13))
105
106/* TI CI parity status */
107#define ADF_GEN6_TI_CI_PAR_STS				0x50060C
108
109/* TI CI parity reporting mask */
110#define ADF_GEN6_TI_CI_PAR_ERR_MASK			0x500608
111
112/*
113 * TI CI parity status mask
114 * BIT(0) - CdCmdQ_sts patiry error status
115 * BIT(1) - CdDataQ_sts parity error status
116 * BIT(3) - CPP_SkidQ_sts parity error status
117 */
118#define ADF_GEN6_TI_CI_PAR_STS_MASK \
119	(BIT(0) | BIT(1) | BIT(3))
120
121/* TI PULLFUB parity status */
122#define ADF_GEN6_TI_PULL0FUB_PAR_STS			0x500618
123
124/* TI PULLFUB parity error reporting mask */
125#define ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK		0x500614
126
127/*
128 * TI PULLFUB parity status mask
129 * BIT(0) - TrnPullReqQ_sts parity status
130 * BIT(1) - TrnSharedDataQ_sts parity status
131 * BIT(2) - TrnPullReqDataQ_sts parity status
132 * BIT(4) - CPP_CiPullReqQ_sts parity status
133 * BIT(5) - CPP_TrnPullReqQ_sts parity status
134 * BIT(6) - CPP_PullidQ_sts parity status
135 * BIT(7) - CPP_WaitDataQ_sts parity status
136 * BIT(8) - CPP_CdDataQ_sts parity status
137 * BIT(9) - CPP_TrnDataQP0_sts parity status
138 * BIT(10) - BIT(11) - CPP_TrnDataQRF[00:01]_sts parity status
139 * BIT(12) - CPP_TrnDataQP1_sts parity status
140 * BIT(13) - BIT(14) - CPP_TrnDataQRF[10:11]_sts parity status
141 */
142#define ADF_GEN6_TI_PULL0FUB_PAR_STS_MASK \
143	(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | \
144	 BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14))
145
146/* TI PUSHUB parity status */
147#define ADF_GEN6_TI_PUSHFUB_PAR_STS			0x500630
148
149/* TI PUSHFUB parity error reporting mask */
150#define ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK		0x50062C
151
152/*
153 * TI PUSHUB parity status mask
154 * BIT(0) - SbPushReqQ_sts parity status
155 * BIT(1) - BIT(2) - SbPushDataQ[0:1]_sts parity status
156 * BIT(4) - CPP_CdPushReqQ_sts parity status
157 * BIT(5) - BIT(6) - CPP_CdPushDataQ[0:1]_sts parity status
158 * BIT(7) - CPP_SbPushReqQ_sts parity status
159 * BIT(8) - CPP_SbPushDataQP_sts parity status
160 * BIT(9) - BIT(10) - CPP_SbPushDataQRF[0:1]_sts parity status
161 */
162#define ADF_GEN6_TI_PUSHFUB_PAR_STS_MASK \
163	(BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | \
164	 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10))
165
166/* TI CD parity status */
167#define ADF_GEN6_TI_CD_PAR_STS				0x50063C
168
169/* TI CD parity error mask */
170#define ADF_GEN6_TI_CD_PAR_ERR_MASK			0x500638
171
172/*
173 * TI CD parity status mask
174 * BIT(0) - BIT(15) - CtxMdRam[0:15]_sts parity status
175 * BIT(16) - Leaf2ClusterRam_sts parity status
176 * BIT(17) - BIT(18) - Ring2LeafRam[0:1]_sts parity status
177 * BIT(19) - VirtualQ_sts parity status
178 * BIT(20) - DtRdQ_sts parity status
179 * BIT(21) - DtWrQ_sts parity status
180 * BIT(22) - RiCmdQ_sts parity status
181 * BIT(23) - BypassQ_sts parity status
182 * BIT(24) - DtRdQ_sc_sts parity status
183 * BIT(25) - DtWrQ_sc_sts parity status
184 */
185#define ADF_GEN6_TI_CD_PAR_STS_MASK \
186	(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
187	 BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | \
188	 BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
189	 BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25))
190
191/* TI TRNSB parity status */
192#define ADF_GEN6_TI_TRNSB_PAR_STS			0x500648
193
194/* TI TRNSB parity error reporting mask */
195#define ADF_GEN6_TI_TRNSB_PAR_ERR_MASK			0x500644
196
197/*
198 * TI TRNSB parity status mask
199 * BIT(0) - TrnPHdrQP_sts parity status
200 * BIT(1) - TrnPHdrQRF_sts parity status
201 * BIT(2) - TrnPDataQP_sts parity status
202 * BIT(3) - BIT(6) - TrnPDataQRF[0:3]_sts parity status
203 * BIT(7) - TrnNpHdrQP_sts parity status
204 * BIT(8) - BIT(9) - TrnNpHdrQRF[0:1]_sts parity status
205 * BIT(10) - TrnCplHdrQ_sts parity status
206 * BIT(11) - TrnPutObsReqQ_sts parity status
207 * BIT(12) - TrnPushReqQ_sts parity status
208 * BIT(13) - SbSplitIdRam_sts parity status
209 * BIT(14) - SbReqCountQ_sts parity status
210 * BIT(15) - SbCplTrkRam_sts parity status
211 * BIT(16) - SbGetObsReqQ_sts parity status
212 * BIT(17) - SbEpochIdQ_sts parity status
213 * BIT(18) - SbAtCplHdrQ_sts parity status
214 * BIT(19) - SbAtCplDataQ_sts parity status
215 * BIT(20) - SbReqCountRam_sts parity status
216 * BIT(21) - SbAtCplHdrQ_sc_sts parity status
217 */
218#define ADF_GEN6_TI_TRNSB_PAR_STS_MASK \
219	(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | \
220	 BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | \
221	 BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | \
222	 BIT(19) | BIT(20) | BIT(21))
223
224/* Status register to log misc error on RI */
225#define ADF_GEN6_RIMISCSTS				0x41B1B8
226
227/* Status control register to log misc RI error */
228#define ADF_GEN6_RIMISCCTL				0x41B1BC
229
230/*
231 * ERRSOU2 bit mask
232 * BIT(0) - SSM Interrupt Mask
233 * BIT(1) - CFC on CPP. ORed of CFC Push error and Pull error
234 * BIT(2) - BIT(4) - CPP attention interrupts
235 * BIT(18) - PM interrupt
236 */
237#define ADF_GEN6_ERRSOU2_SSM_ERR_BIT			BIT(0)
238#define ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT	BIT(1)
239#define ADF_GEN6_ERRSOU2_CPP_CFC_ATT_INT_MASK \
240	(BIT(2) | BIT(3) | BIT(4))
241
242#define ADF_GEN6_ERRSOU2_PM_INT_BIT			BIT(18)
243
244#define ADF_GEN6_ERRSOU2_MASK \
245	(ADF_GEN6_ERRSOU2_SSM_ERR_BIT | \
246	 ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT)
247
248#define ADF_GEN6_ERRSOU2_DIS_MASK \
249	(ADF_GEN6_ERRSOU2_SSM_ERR_BIT | \
250	 ADF_GEN6_ERRSOU2_CPP_CFC_ERR_STATUS_BIT | \
251	 ADF_GEN6_ERRSOU2_CPP_CFC_ATT_INT_MASK)
252
253#define ADF_GEN6_IAINTSTATSSM				0x28
254
255/* IAINTSTATSSM error bit mask definitions */
256#define ADF_GEN6_IAINTSTATSSM_SH_ERR_BIT		BIT(0)
257#define ADF_GEN6_IAINTSTATSSM_PPERR_BIT			BIT(2)
258#define ADF_GEN6_IAINTSTATSSM_SCMPAR_ERR_BIT		BIT(4)
259#define ADF_GEN6_IAINTSTATSSM_CPPPAR_ERR_BIT		BIT(5)
260#define ADF_GEN6_IAINTSTATSSM_RFPAR_ERR_BIT		BIT(6)
261#define ADF_GEN6_IAINTSTATSSM_UNEXP_CPL_ERR_BIT		BIT(7)
262
263#define ADF_GEN6_IAINTSTATSSM_MASK \
264	(ADF_GEN6_IAINTSTATSSM_SH_ERR_BIT | \
265	 ADF_GEN6_IAINTSTATSSM_PPERR_BIT | \
266	 ADF_GEN6_IAINTSTATSSM_SCMPAR_ERR_BIT | \
267	 ADF_GEN6_IAINTSTATSSM_CPPPAR_ERR_BIT | \
268	 ADF_GEN6_IAINTSTATSSM_RFPAR_ERR_BIT | \
269	 ADF_GEN6_IAINTSTATSSM_UNEXP_CPL_ERR_BIT)
270
271#define ADF_GEN6_UERRSSMSH				0x18
272
273/*
274 * UERRSSMSH error bit mask definitions
275 *
276 * BIT(0) - Indicates one uncorrectable error
277 * BIT(15) - Indicates multiple uncorrectable errors
278 *	     in device shared memory
279 */
280#define ADF_GEN6_UERRSSMSH_MASK			(BIT(0) | BIT(15))
281
282/*
283 * CERRSSMSH error bit
284 * BIT(0) - Indicates one correctable error
285 */
286#define ADF_GEN6_CERRSSMSH_ERROR_BIT			(BIT(0) | BIT(15) | BIT(24))
287#define ADF_GEN6_CERRSSMSH				0x10
288
289#define ADF_GEN6_INTMASKSSM				0x0
290
291/*
292 * Error reporting mask in INTMASKSSM
293 * BIT(0) - Shared memory uncorrectable interrupt mask
294 * BIT(2) - PPERR interrupt mask
295 * BIT(4) - SCM parity error interrupt mask
296 * BIT(5) - CPP parity error interrupt mask
297 * BIT(6) - SHRAM RF parity error interrupt mask
298 * BIT(7) - AXI unexpected completion error mask
299 */
300#define ADF_GEN6_INTMASKSSM_MASK	\
301	(BIT(0) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(7))
302
303/* CPP push or pull error */
304#define ADF_GEN6_PPERR					0x8
305
306#define ADF_GEN6_PPERR_MASK				(BIT(0) | BIT(1))
307
308/*
309 * SSM_FERR_STATUS error bit mask definitions
310 */
311#define ADF_GEN6_SCM_PAR_ERR_MASK			BIT(5)
312#define ADF_GEN6_CPP_PAR_ERR_MASK			(BIT(0) | BIT(1) | BIT(2))
313#define ADF_GEN6_UNEXP_CPL_ERR_MASK			(BIT(3) | BIT(4) | BIT(10) | BIT(11))
314#define ADF_GEN6_RF_PAR_ERR_MASK			BIT(16)
315
316#define ADF_GEN6_SSM_FERR_STATUS			0x9C
317
318#define ADF_GEN6_CPP_CFC_ERR_STATUS			0x640C04
319
320/*
321 * BIT(0) - Indicates one or more CPP CFC errors
322 * BIT(1) - Indicates multiple CPP CFC errors
323 * BIT(7) - Indicates CPP CFC command parity error type
324 * BIT(8) - Indicates CPP CFC data parity error type
325 */
326#define ADF_GEN6_CPP_CFC_ERR_STATUS_ERR_BIT		BIT(0)
327#define ADF_GEN6_CPP_CFC_ERR_STATUS_MERR_BIT		BIT(1)
328#define ADF_GEN6_CPP_CFC_ERR_STATUS_CMDPAR_BIT		BIT(7)
329#define ADF_GEN6_CPP_CFC_ERR_STATUS_DATAPAR_BIT		BIT(8)
330#define ADF_GEN6_CPP_CFC_FATAL_ERR_BIT		\
331	(ADF_GEN6_CPP_CFC_ERR_STATUS_ERR_BIT |	\
332	 ADF_GEN6_CPP_CFC_ERR_STATUS_MERR_BIT)
333
334/*
335 * BIT(0) - Enables CFC to detect and log a push/pull data error
336 * BIT(1) - Enables CFC to generate interrupt to PCIEP for a CPP error
337 * BIT(4) - When 1 parity detection is disabled
338 * BIT(5) - When 1 parity detection is disabled on CPP command bus
339 * BIT(6) - When 1 parity detection is disabled on CPP push/pull bus
340 * BIT(9) - When 1 RF parity error detection is disabled
341 */
342#define ADF_GEN6_CPP_CFC_ERR_CTRL_MASK		(BIT(0) | BIT(1))
343
344#define ADF_GEN6_CPP_CFC_ERR_CTRL_DIS_MASK \
345	(BIT(4) | BIT(5) | BIT(6) | BIT(9) | BIT(10))
346
347#define ADF_GEN6_CPP_CFC_ERR_CTRL			0x640C00
348
349/*
350 * BIT(0) - Clears bit(0) of ADF_GEN6_CPP_CFC_ERR_STATUS
351 *	    when an error is reported on CPP
352 * BIT(1) - Clears bit(1) of ADF_GEN6_CPP_CFC_ERR_STATUS
353 *	    when multiple errors are reported on CPP
354 * BIT(2) - Clears bit(2) of ADF_GEN6_CPP_CFC_ERR_STATUS
355 *	    when attention interrupt is reported
356 */
357#define ADF_GEN6_CPP_CFC_ERR_STATUS_CLR_MASK		(BIT(0) | BIT(1) | BIT(2))
358#define ADF_GEN6_CPP_CFC_ERR_STATUS_CLR			0x640C08
359
360/*
361 * ERRSOU3 bit masks
362 * BIT(0) - indicates error response order overflow and/or BME error
363 * BIT(1) - indicates RI push/pull error
364 * BIT(2) - indicates TI push/pull error
365 * BIT(5) - indicates TI pull parity error
366 * BIT(6) - indicates RI push parity error
367 * BIT(7) - indicates VFLR interrupt
368 * BIT(8) - indicates ring pair interrupts for ATU detected fault
369 * BIT(9) - indicates rate limiting error
370 */
371#define ADF_GEN6_ERRSOU3_TIMISCSTS_BIT			BIT(0)
372#define ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK		(BIT(1) | BIT(6))
373#define ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK		(BIT(2) | BIT(5))
374#define ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT			BIT(7)
375#define ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT		BIT(8)
376#define ADF_GEN6_ERRSOU3_RLTERROR_BIT			BIT(9)
377#define ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT		BIT(16)
378#define ADF_GEN6_ERRSOU3_PCIE_DEVHALT_BIT		BIT(17)
379#define ADF_GEN6_ERRSOU3_PG_REQ_DEVHALT_BIT		BIT(18)
380#define ADF_GEN6_ERRSOU3_XLT_CPL_DEVHALT_BIT		BIT(19)
381#define ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT		BIT(20)
382
383#define ADF_GEN6_ERRSOU3_MASK ( \
384	(ADF_GEN6_ERRSOU3_TIMISCSTS_BIT) | \
385	(ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK) | \
386	(ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK) | \
387	(ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT) | \
388	(ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT) | \
389	(ADF_GEN6_ERRSOU3_RLTERROR_BIT) | \
390	(ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT) | \
391	(ADF_GEN6_ERRSOU3_PCIE_DEVHALT_BIT) | \
392	(ADF_GEN6_ERRSOU3_PG_REQ_DEVHALT_BIT) | \
393	(ADF_GEN6_ERRSOU3_XLT_CPL_DEVHALT_BIT) | \
394	(ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT))
395
396#define ADF_GEN6_ERRSOU3_DIS_MASK ( \
397	(ADF_GEN6_ERRSOU3_TIMISCSTS_BIT) | \
398	(ADF_GEN6_ERRSOU3_RICPPINTSTS_MASK) | \
399	(ADF_GEN6_ERRSOU3_TICPPINTSTS_MASK) | \
400	(ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT) | \
401	(ADF_GEN6_ERRSOU3_ATUFAULTSTATUS_BIT) | \
402	(ADF_GEN6_ERRSOU3_RLTERROR_BIT) | \
403	(ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT))
404
405/* Rate limiting error log register */
406#define ADF_GEN6_RLT_ERRLOG				0x508814
407
408#define ADF_GEN6_RLT_ERRLOG_MASK	(BIT(0) | BIT(1) | BIT(2) | BIT(3))
409
410/* TI misc status register */
411#define ADF_GEN6_TIMISCSTS				0x50054C
412
413/* TI misc error reporting mask */
414#define ADF_GEN6_TIMISCCTL				0x500548
415
416/*
417 * TI Misc error reporting control mask
418 * BIT(0) - Enables error detection and logging in TIMISCSTS register
419 * BIT(1) - It has effect only when SRIOV enabled, this bit is 0 by default
420 * BIT(2) - Enables the D-F-x counter within the dispatch arbiter
421 *	    to start based on the command triggered from
422 * BIT(30) - Disables VFLR functionality
423 * bits 1, 2 and 30 value should be preserved and not meant to be changed
424 * within RAS.
425 */
426#define ADF_GEN6_TIMISCCTL_BIT				BIT(0)
427#define ADF_GEN6_TIMSCCTL_RELAY_MASK			(BIT(1) | BIT(2) | BIT(30))
428
429/* RI CPP interface status register */
430#define ADF_GEN6_RICPPINTSTS				0x41A330
431
432/*
433 * Uncorrectable error mask in RICPPINTSTS register
434 * BIT(0) - RI asserted the CPP error signal during a push
435 * BIT(1) - RI detected the CPP error signal asserted during a pull
436 * BIT(2) - RI detected a push data parity error
437 * BIT(3) - RI detected a push valid parity error
438 */
439#define ADF_GEN6_RICPPINTSTS_MASK			(BIT(0) | BIT(1) | BIT(2) | BIT(3))
440
441/* RI CPP interface register control */
442#define ADF_GEN6_RICPPINTCTL				0x41A32C
443
444/*
445 * Control bit mask for RICPPINTCTL register
446 * BIT(0) - value of 1 enables error detection and reporting
447 *	    on the RI CPP Push interface
448 * BIT(1) - value of 1 enables error detection and reporting
449 *	    on the RI CPP Pull interface
450 * BIT(2) - value of 1 enables error detection and reporting
451 *	    on the RI Parity
452 * BIT(3) - value of 1 enable checking parity on CPP
453 */
454#define ADF_GEN6_RICPPINTCTL_MASK \
455	(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
456
457/* TI CPP interface status register */
458#define ADF_GEN6_TICPPINTSTS				0x50053C
459
460/*
461 * Uncorrectable error mask in TICPPINTSTS register
462 * BIT(0) - value of 1 indicates that the TI asserted
463 *	    the CPP error signal during a push
464 * BIT(1) - value of 1 indicates that the TI detected
465 *	    the CPP error signal asserted during a pull
466 * BIT(2) - value of 1 indicates that the TI detected
467 *	    a pull data parity error
468 */
469#define ADF_GEN6_TICPPINTSTS_MASK			(BIT(0) | BIT(1) | BIT(2))
470
471/* TI CPP interface status register control */
472#define ADF_GEN6_TICPPINTCTL				0x500538
473
474/*
475 * Control bit mask for TICPPINTCTL register
476 * BIT(0) - value of 1 enables error detection and reporting on
477 *	    the TI CPP Push interface
478 * BIT(1) - value of 1 enables error detection and reporting on
479 *	    the TI CPP Push interface
480 * BIT(2) - value of 1 enables parity error detection and logging on
481 *	    the TI CPP Pull interface
482 * BIT(3) - value of 1 enables CPP CMD and Pull Data parity checking
483 */
484#define ADF_GEN6_TICPPINTCTL_MASK	\
485	(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
486
487/* ATU fault status register */
488#define ADF_GEN6_ATUFAULTSTATUS(i)			(0x506000 + ((i) * 0x4))
489
490#define ADF_GEN6_ATUFAULTSTATUS_BIT			BIT(0)
491
492/* Command parity error detected on IOSFP command to QAT */
493#define ADF_GEN6_RIMISCSTS_BIT				BIT(0)
494
495#define ADF_GEN6_GENSTS					0x41A220
496#define ADF_GEN6_GENSTS_DEVICE_STATE_MASK		GENMASK(1, 0)
497#define ADF_GEN6_GENSTS_RESET_TYPE_MASK			GENMASK(3, 2)
498#define ADF_GEN6_GENSTS_PFLR				0x1
499#define ADF_GEN6_GENSTS_COLD_RESET			0x3
500#define ADF_GEN6_GENSTS_DEVHALT				0x1
501
502void adf_gen6_init_ras_ops(struct adf_ras_ops *ras_ops);
503
504#endif /* ADF_GEN6_RAS_H_ */