adf_gen4_hw_data.h

  1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
  2/* Copyright(c) 2020 Intel Corporation */
  3#ifndef ADF_GEN4_HW_DATA_H_
  4#define ADF_GEN4_HW_DATA_H_
  5
  6#include <linux/units.h>
  7
  8#include "adf_accel_devices.h"
  9#include "adf_cfg_common.h"
 10#include "adf_dc.h"
 11
 12/* PCIe configuration space */
 13#define ADF_GEN4_BAR_MASK	(BIT(0) | BIT(2) | BIT(4))
 14#define ADF_GEN4_SRAM_BAR	0
 15#define ADF_GEN4_PMISC_BAR	1
 16#define ADF_GEN4_ETR_BAR	2
 17
 18/* Clocks frequency */
 19#define ADF_GEN4_KPT_COUNTER_FREQ	(100 * HZ_PER_MHZ)
 20
 21/* Physical function fuses */
 22#define ADF_GEN4_FUSECTL0_OFFSET	0x2C8
 23#define ADF_GEN4_FUSECTL1_OFFSET	0x2CC
 24#define ADF_GEN4_FUSECTL2_OFFSET	0x2D0
 25#define ADF_GEN4_FUSECTL3_OFFSET	0x2D4
 26#define ADF_GEN4_FUSECTL4_OFFSET	0x2D8
 27#define ADF_GEN4_FUSECTL5_OFFSET	0x2DC
 28
 29/* Accelerators */
 30#define ADF_GEN4_ACCELERATORS_MASK	0x1
 31#define ADF_GEN4_MAX_ACCELERATORS	1
 32#define ADF_GEN4_ADMIN_ACCELENGINES	1
 33
 34/* MSIX interrupt */
 35#define ADF_GEN4_SMIAPF_RP_X0_MASK_OFFSET	0x41A040
 36#define ADF_GEN4_SMIAPF_RP_X1_MASK_OFFSET	0x41A044
 37#define ADF_GEN4_SMIAPF_MASK_OFFSET		0x41A084
 38#define ADF_GEN4_MSIX_RTTABLE_OFFSET(i)		(0x409000 + ((i) * 0x04))
 39
 40/* Bank and ring configuration */
 41#define ADF_GEN4_MAX_RPS		64
 42#define ADF_GEN4_NUM_RINGS_PER_BANK	2
 43#define ADF_GEN4_NUM_BANKS_PER_VF	4
 44#define ADF_GEN4_ETR_MAX_BANKS		64
 45#define ADF_GEN4_RX_RINGS_OFFSET	1
 46#define ADF_GEN4_TX_RINGS_MASK		0x1
 47
 48/* Arbiter configuration */
 49#define ADF_GEN4_ARB_CONFIG			(BIT(31) | BIT(6) | BIT(0))
 50#define ADF_GEN4_ARB_OFFSET			0x0
 51#define ADF_GEN4_ARB_WRK_2_SER_MAP_OFFSET	0x400
 52
 53/* Admin Interface Reg Offset */
 54#define ADF_GEN4_ADMINMSGUR_OFFSET	0x500574
 55#define ADF_GEN4_ADMINMSGLR_OFFSET	0x500578
 56#define ADF_GEN4_MAILBOX_BASE_OFFSET	0x600970
 57
 58/* Default ring mapping */
 59#define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP \
 60	(ASYM << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
 61	  SYM << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
 62	 ASYM << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
 63	  SYM << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
 64
 65/* WDT timers
 66 *
 67 * Timeout is in cycles. Clock speed may vary across products but this
 68 * value should be a few milli-seconds.
 69 */
 70#define ADF_SSM_WDT_DEFAULT_VALUE	0x7000000ULL
 71#define ADF_SSM_WDT_PKE_DEFAULT_VALUE	0x8000000
 72#define ADF_SSMWDTL_OFFSET		0x54
 73#define ADF_SSMWDTH_OFFSET		0x5C
 74#define ADF_SSMWDTPKEL_OFFSET		0x58
 75#define ADF_SSMWDTPKEH_OFFSET		0x60
 76
 77/* Ring reset */
 78#define ADF_RPRESET_POLL_TIMEOUT_US	(5 * USEC_PER_SEC)
 79#define ADF_RPRESET_POLL_DELAY_US	20
 80#define ADF_WQM_CSR_RPRESETCTL_RESET	BIT(0)
 81#define ADF_WQM_CSR_RPRESETCTL_DRAIN	BIT(2)
 82#define ADF_WQM_CSR_RPRESETCTL(bank)	(0x6000 + ((bank) << 3))
 83#define ADF_WQM_CSR_RPRESETSTS_STATUS	BIT(0)
 84#define ADF_WQM_CSR_RPRESETSTS(bank)	(ADF_WQM_CSR_RPRESETCTL(bank) + 4)
 85
 86/* Ring interrupt */
 87#define ADF_COALESCED_POLL_TIMEOUT_US	(1 * USEC_PER_SEC)
 88#define ADF_COALESCED_POLL_DELAY_US	1000
 89#define ADF_WQM_CSR_RPINTSOU(bank)	(0x200000 + ((bank) << 12))
 90#define ADF_WQM_CSR_RP_IDX_RX		1
 91
 92/* Error source registers */
 93#define ADF_GEN4_ERRSOU0	(0x41A200)
 94#define ADF_GEN4_ERRSOU1	(0x41A204)
 95#define ADF_GEN4_ERRSOU2	(0x41A208)
 96#define ADF_GEN4_ERRSOU3	(0x41A20C)
 97
 98/* Error source mask registers */
 99#define ADF_GEN4_ERRMSK0	(0x41A210)
100#define ADF_GEN4_ERRMSK1	(0x41A214)
101#define ADF_GEN4_ERRMSK2	(0x41A218)
102#define ADF_GEN4_ERRMSK3	(0x41A21C)
103
104#define ADF_GEN4_VFLNOTIFY	BIT(7)
105
106/* Number of heartbeat counter pairs */
107#define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE
108
109/* Rate Limiting */
110#define ADF_GEN4_RL_R2L_OFFSET			0x508000
111#define ADF_GEN4_RL_L2C_OFFSET			0x509000
112#define ADF_GEN4_RL_C2S_OFFSET			0x508818
113#define ADF_GEN4_RL_TOKEN_PCIEIN_BUCKET_OFFSET	0x508800
114#define ADF_GEN4_RL_TOKEN_PCIEOUT_BUCKET_OFFSET	0x508804
115
116/* Arbiter threads mask with error value */
117#define ADF_GEN4_ENA_THD_MASK_ERROR	GENMASK(ADF_NUM_THREADS_PER_AE, 0)
118
119/* PF2VM communication channel */
120#define ADF_GEN4_PF2VM_OFFSET(i)	(0x40B010 + (i) * 0x20)
121#define ADF_GEN4_VM2PF_OFFSET(i)	(0x40B014 + (i) * 0x20)
122#define ADF_GEN4_VINTMSKPF2VM_OFFSET(i)	(0x40B00C + (i) * 0x20)
123#define ADF_GEN4_VINTSOUPF2VM_OFFSET(i)	(0x40B008 + (i) * 0x20)
124#define ADF_GEN4_VINTMSK_OFFSET(i)	(0x40B004 + (i) * 0x20)
125#define ADF_GEN4_VINTSOU_OFFSET(i)	(0x40B000 + (i) * 0x20)
126
127struct adf_gen4_vfmig {
128	struct adf_mstate_mgr *mstate_mgr;
129	bool bank_stopped[ADF_GEN4_NUM_BANKS_PER_VF];
130};
131
132void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
133
134enum icp_qat_gen4_slice_mask {
135	ICP_ACCEL_GEN4_MASK_CIPHER_SLICE = BIT(0),
136	ICP_ACCEL_GEN4_MASK_AUTH_SLICE = BIT(1),
137	ICP_ACCEL_GEN4_MASK_PKE_SLICE = BIT(2),
138	ICP_ACCEL_GEN4_MASK_COMPRESS_SLICE = BIT(3),
139	ICP_ACCEL_GEN4_MASK_UCS_SLICE = BIT(4),
140	ICP_ACCEL_GEN4_MASK_EIA3_SLICE = BIT(5),
141	ICP_ACCEL_GEN4_MASK_SMX_SLICE = BIT(7),
142	ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE = BIT(8),
143	ICP_ACCEL_GEN4_MASK_ZUC_256_SLICE = BIT(9),
144};
145
146enum adf_gen4_rp_groups {
147	RP_GROUP_0,
148	RP_GROUP_1,
149	RP_GROUP_COUNT
150};
151
152void adf_gen4_enable_error_correction(struct adf_accel_dev *accel_dev);
153void adf_gen4_enable_ints(struct adf_accel_dev *accel_dev);
154u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self);
155void adf_gen4_get_admin_info(struct admin_info *admin_csrs_info);
156void adf_gen4_get_arb_info(struct arb_info *arb_info);
157u32 adf_gen4_get_etr_bar_id(struct adf_hw_device_data *self);
158u32 adf_gen4_get_heartbeat_clock(struct adf_hw_device_data *self);
159u32 adf_gen4_get_misc_bar_id(struct adf_hw_device_data *self);
160u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self);
161u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self);
162enum dev_sku_info adf_gen4_get_sku(struct adf_hw_device_data *self);
163u32 adf_gen4_get_sram_bar_id(struct adf_hw_device_data *self);
164int adf_gen4_init_device(struct adf_accel_dev *accel_dev);
165int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number);
166void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev);
167void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
168int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev);
169u16 adf_gen4_get_ring_to_svc_map(struct adf_accel_dev *accel_dev);
170int adf_gen4_bank_quiesce_coal_timer(struct adf_accel_dev *accel_dev,
171				     u32 bank_idx, int timeout_ms);
172int adf_gen4_bank_drain_start(struct adf_accel_dev *accel_dev,
173			      u32 bank_number, int timeout_us);
174void adf_gen4_bank_drain_finish(struct adf_accel_dev *accel_dev,
175				u32 bank_number);
176bool adf_gen4_services_supported(unsigned long service_mask);
177void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);
178void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data);
179u32 adf_gen4_get_svc_slice_cnt(struct adf_accel_dev *accel_dev,
180			       enum adf_base_services svc);
181
182#endif