adf_gen4_hw_csr_data.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* Copyright(c) 2024 Intel Corporation */
  3#include <linux/types.h>
  4#include "adf_gen4_hw_csr_data.h"
  5
  6static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
  7{
  8	return BUILD_RING_BASE_ADDR(addr, size);
  9}
 10
 11static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
 12{
 13	return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
 14}
 15
 16static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
 17				u32 value)
 18{
 19	WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
 20}
 21
 22static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
 23{
 24	return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
 25}
 26
 27static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
 28				u32 value)
 29{
 30	WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
 31}
 32
 33static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank)
 34{
 35	return READ_CSR_STAT(csr_base_addr, bank);
 36}
 37
 38static u32 read_csr_uo_stat(void __iomem *csr_base_addr, u32 bank)
 39{
 40	return READ_CSR_UO_STAT(csr_base_addr, bank);
 41}
 42
 43static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
 44{
 45	return READ_CSR_E_STAT(csr_base_addr, bank);
 46}
 47
 48static u32 read_csr_ne_stat(void __iomem *csr_base_addr, u32 bank)
 49{
 50	return READ_CSR_NE_STAT(csr_base_addr, bank);
 51}
 52
 53static u32 read_csr_nf_stat(void __iomem *csr_base_addr, u32 bank)
 54{
 55	return READ_CSR_NF_STAT(csr_base_addr, bank);
 56}
 57
 58static u32 read_csr_f_stat(void __iomem *csr_base_addr, u32 bank)
 59{
 60	return READ_CSR_F_STAT(csr_base_addr, bank);
 61}
 62
 63static u32 read_csr_c_stat(void __iomem *csr_base_addr, u32 bank)
 64{
 65	return READ_CSR_C_STAT(csr_base_addr, bank);
 66}
 67
 68static u32 read_csr_exp_stat(void __iomem *csr_base_addr, u32 bank)
 69{
 70	return READ_CSR_EXP_STAT(csr_base_addr, bank);
 71}
 72
 73static u32 read_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank)
 74{
 75	return READ_CSR_EXP_INT_EN(csr_base_addr, bank);
 76}
 77
 78static void write_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank,
 79				 u32 value)
 80{
 81	WRITE_CSR_EXP_INT_EN(csr_base_addr, bank, value);
 82}
 83
 84static u32 read_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
 85				u32 ring)
 86{
 87	return READ_CSR_RING_CONFIG(csr_base_addr, bank, ring);
 88}
 89
 90static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,
 91				  u32 value)
 92{
 93	WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
 94}
 95
 96static dma_addr_t read_csr_ring_base(void __iomem *csr_base_addr, u32 bank,
 97				     u32 ring)
 98{
 99	return READ_CSR_RING_BASE(csr_base_addr, bank, ring);
100}
101
102static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
103				dma_addr_t addr)
104{
105	WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
106}
107
108static u32 read_csr_int_en(void __iomem *csr_base_addr, u32 bank)
109{
110	return READ_CSR_INT_EN(csr_base_addr, bank);
111}
112
113static void write_csr_int_en(void __iomem *csr_base_addr, u32 bank, u32 value)
114{
115	WRITE_CSR_INT_EN(csr_base_addr, bank, value);
116}
117
118static u32 read_csr_int_flag(void __iomem *csr_base_addr, u32 bank)
119{
120	return READ_CSR_INT_FLAG(csr_base_addr, bank);
121}
122
123static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank,
124			       u32 value)
125{
126	WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
127}
128
129static u32 read_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
130{
131	return READ_CSR_INT_SRCSEL(csr_base_addr, bank);
132}
133
134static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
135{
136	WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
137}
138
139static void write_csr_int_srcsel_w_val(void __iomem *csr_base_addr, u32 bank,
140				       u32 value)
141{
142	WRITE_CSR_INT_SRCSEL_W_VAL(csr_base_addr, bank, value);
143}
144
145static u32 read_csr_int_col_en(void __iomem *csr_base_addr, u32 bank)
146{
147	return READ_CSR_INT_COL_EN(csr_base_addr, bank);
148}
149
150static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value)
151{
152	WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
153}
154
155static u32 read_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank)
156{
157	return READ_CSR_INT_COL_CTL(csr_base_addr, bank);
158}
159
160static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
161				  u32 value)
162{
163	WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
164}
165
166static u32 read_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank)
167{
168	return READ_CSR_INT_FLAG_AND_COL(csr_base_addr, bank);
169}
170
171static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
172				       u32 value)
173{
174	WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
175}
176
177static u32 read_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank)
178{
179	return READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank);
180}
181
182static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
183				      u32 value)
184{
185	WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
186}
187
188static u32 get_int_col_ctl_enable_mask(void)
189{
190	return ADF_RING_CSR_INT_COL_CTL_ENABLE;
191}
192
193void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
194{
195	csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
196	csr_ops->read_csr_ring_head = read_csr_ring_head;
197	csr_ops->write_csr_ring_head = write_csr_ring_head;
198	csr_ops->read_csr_ring_tail = read_csr_ring_tail;
199	csr_ops->write_csr_ring_tail = write_csr_ring_tail;
200	csr_ops->read_csr_stat = read_csr_stat;
201	csr_ops->read_csr_uo_stat = read_csr_uo_stat;
202	csr_ops->read_csr_e_stat = read_csr_e_stat;
203	csr_ops->read_csr_ne_stat = read_csr_ne_stat;
204	csr_ops->read_csr_nf_stat = read_csr_nf_stat;
205	csr_ops->read_csr_f_stat = read_csr_f_stat;
206	csr_ops->read_csr_c_stat = read_csr_c_stat;
207	csr_ops->read_csr_exp_stat = read_csr_exp_stat;
208	csr_ops->read_csr_exp_int_en = read_csr_exp_int_en;
209	csr_ops->write_csr_exp_int_en = write_csr_exp_int_en;
210	csr_ops->read_csr_ring_config = read_csr_ring_config;
211	csr_ops->write_csr_ring_config = write_csr_ring_config;
212	csr_ops->read_csr_ring_base = read_csr_ring_base;
213	csr_ops->write_csr_ring_base = write_csr_ring_base;
214	csr_ops->read_csr_int_en = read_csr_int_en;
215	csr_ops->write_csr_int_en = write_csr_int_en;
216	csr_ops->read_csr_int_flag = read_csr_int_flag;
217	csr_ops->write_csr_int_flag = write_csr_int_flag;
218	csr_ops->read_csr_int_srcsel = read_csr_int_srcsel;
219	csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
220	csr_ops->write_csr_int_srcsel_w_val = write_csr_int_srcsel_w_val;
221	csr_ops->read_csr_int_col_en = read_csr_int_col_en;
222	csr_ops->write_csr_int_col_en = write_csr_int_col_en;
223	csr_ops->read_csr_int_col_ctl = read_csr_int_col_ctl;
224	csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
225	csr_ops->read_csr_int_flag_and_col = read_csr_int_flag_and_col;
226	csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
227	csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en;
228	csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
229	csr_ops->get_int_col_ctl_enable_mask = get_int_col_ctl_enable_mask;
230}
231EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops);