adf_420xx_hw_data.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* Copyright(c) 2023 Intel Corporation */
  3#include <linux/iopoll.h>
  4#include <adf_accel_devices.h>
  5#include <adf_admin.h>
  6#include <adf_cfg.h>
  7#include <adf_cfg_services.h>
  8#include <adf_clock.h>
  9#include <adf_common_drv.h>
 10#include <adf_fw_config.h>
 11#include <adf_gen4_config.h>
 12#include <adf_gen4_hw_csr_data.h>
 13#include <adf_gen4_hw_data.h>
 14#include <adf_gen4_pfvf.h>
 15#include <adf_gen4_pm.h>
 16#include <adf_gen4_ras.h>
 17#include <adf_gen4_tl.h>
 18#include <adf_gen4_vf_mig.h>
 19#include <adf_timer.h>
 20#include "adf_420xx_hw_data.h"
 21#include "icp_qat_hw.h"
 22
 23#define ADF_AE_GROUP_0		GENMASK(3, 0)
 24#define ADF_AE_GROUP_1		GENMASK(7, 4)
 25#define ADF_AE_GROUP_2		GENMASK(11, 8)
 26#define ADF_AE_GROUP_3		GENMASK(15, 12)
 27#define ADF_AE_GROUP_4		BIT(16)
 28
 29#define ENA_THD_MASK_ASYM	GENMASK(1, 0)
 30#define ENA_THD_MASK_SYM	GENMASK(3, 0)
 31#define ENA_THD_MASK_DC		GENMASK(1, 0)
 32
 33static const char * const adf_420xx_fw_objs[] = {
 34	[ADF_FW_SYM_OBJ] =  ADF_420XX_SYM_OBJ,
 35	[ADF_FW_ASYM_OBJ] =  ADF_420XX_ASYM_OBJ,
 36	[ADF_FW_DC_OBJ] =  ADF_420XX_DC_OBJ,
 37	[ADF_FW_ADMIN_OBJ] = ADF_420XX_ADMIN_OBJ,
 38};
 39
 40static const struct adf_fw_config adf_fw_cy_config[] = {
 41	{ADF_AE_GROUP_3, ADF_FW_SYM_OBJ},
 42	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},
 43	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},
 44	{ADF_AE_GROUP_0, ADF_FW_ASYM_OBJ},
 45	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},
 46};
 47
 48static const struct adf_fw_config adf_fw_dc_config[] = {
 49	{ADF_AE_GROUP_1, ADF_FW_DC_OBJ},
 50	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},
 51	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},
 52};
 53
 54static const struct adf_fw_config adf_fw_sym_config[] = {
 55	{ADF_AE_GROUP_3, ADF_FW_SYM_OBJ},
 56	{ADF_AE_GROUP_2, ADF_FW_SYM_OBJ},
 57	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},
 58	{ADF_AE_GROUP_0, ADF_FW_SYM_OBJ},
 59	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},
 60};
 61
 62static const struct adf_fw_config adf_fw_asym_config[] = {
 63	{ADF_AE_GROUP_3, ADF_FW_ASYM_OBJ},
 64	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},
 65	{ADF_AE_GROUP_1, ADF_FW_ASYM_OBJ},
 66	{ADF_AE_GROUP_0, ADF_FW_ASYM_OBJ},
 67	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},
 68};
 69
 70static const struct adf_fw_config adf_fw_asym_dc_config[] = {
 71	{ADF_AE_GROUP_3, ADF_FW_ASYM_OBJ},
 72	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},
 73	{ADF_AE_GROUP_1, ADF_FW_ASYM_OBJ},
 74	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},
 75	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},
 76};
 77
 78static const struct adf_fw_config adf_fw_sym_dc_config[] = {
 79	{ADF_AE_GROUP_2, ADF_FW_SYM_OBJ},
 80	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},
 81	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},
 82	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},
 83};
 84
 85static const struct adf_fw_config adf_fw_dcc_config[] = {
 86	{ADF_AE_GROUP_1, ADF_FW_DC_OBJ},
 87	{ADF_AE_GROUP_0, ADF_FW_SYM_OBJ},
 88	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},
 89};
 90
 91
 92static struct adf_hw_device_class adf_420xx_class = {
 93	.name = ADF_420XX_DEVICE_NAME,
 94	.type = DEV_420XX,
 95};
 96
 97static u32 get_ae_mask(struct adf_hw_device_data *self)
 98{
 99	u32 me_disable = self->fuses[ADF_FUSECTL4];
100
101	return ~me_disable & ADF_420XX_ACCELENGINES_MASK;
102}
103
104static u32 uof_get_num_objs(struct adf_accel_dev *accel_dev)
105{
106	switch (adf_get_service_enabled(accel_dev)) {
107	case SVC_SYM_ASYM:
108		return ARRAY_SIZE(adf_fw_cy_config);
109	case SVC_DC:
110		return ARRAY_SIZE(adf_fw_dc_config);
111	case SVC_DCC:
112		return ARRAY_SIZE(adf_fw_dcc_config);
113	case SVC_SYM:
114		return ARRAY_SIZE(adf_fw_sym_config);
115	case SVC_ASYM:
116		return ARRAY_SIZE(adf_fw_asym_config);
117	case SVC_ASYM_DC:
118		return ARRAY_SIZE(adf_fw_asym_dc_config);
119	case SVC_SYM_DC:
120		return ARRAY_SIZE(adf_fw_sym_dc_config);
121	default:
122		return 0;
123	}
124}
125
126static const struct adf_fw_config *get_fw_config(struct adf_accel_dev *accel_dev)
127{
128	switch (adf_get_service_enabled(accel_dev)) {
129	case SVC_SYM_ASYM:
130		return adf_fw_cy_config;
131	case SVC_DC:
132		return adf_fw_dc_config;
133	case SVC_DCC:
134		return adf_fw_dcc_config;
135	case SVC_SYM:
136		return adf_fw_sym_config;
137	case SVC_ASYM:
138		return adf_fw_asym_config;
139	case SVC_ASYM_DC:
140		return adf_fw_asym_dc_config;
141	case SVC_SYM_DC:
142		return adf_fw_sym_dc_config;
143	default:
144		return NULL;
145	}
146}
147
148static void update_ae_mask(struct adf_accel_dev *accel_dev)
149{
150	struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
151	const struct adf_fw_config *fw_config;
152	u32 config_ae_mask = 0;
153	u32 ae_mask, num_objs;
154	int i;
155
156	ae_mask = get_ae_mask(hw_data);
157
158	/* Modify the AE mask based on the firmware configuration loaded */
159	fw_config = get_fw_config(accel_dev);
160	num_objs = uof_get_num_objs(accel_dev);
161
162	config_ae_mask |= ADF_420XX_ADMIN_AE_MASK;
163	for (i = 0; i < num_objs; i++)
164		config_ae_mask |= fw_config[i].ae_mask;
165
166	hw_data->ae_mask = ae_mask & config_ae_mask;
167}
168
169static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
170{
171	u32 capabilities_sym, capabilities_asym, capabilities_dc;
172	struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
173	u32 capabilities_dcc;
174	u32 fusectl1;
175
176	/* As a side effect, update ae_mask based on configuration */
177	update_ae_mask(accel_dev);
178
179	/* Read accelerator capabilities mask */
180	pci_read_config_dword(pdev, ADF_GEN4_FUSECTL1_OFFSET, &fusectl1);
181
182	capabilities_sym = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
183			  ICP_ACCEL_CAPABILITIES_CIPHER |
184			  ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
185			  ICP_ACCEL_CAPABILITIES_SHA3 |
186			  ICP_ACCEL_CAPABILITIES_SHA3_EXT |
187			  ICP_ACCEL_CAPABILITIES_HKDF |
188			  ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
189			  ICP_ACCEL_CAPABILITIES_AESGCM_SPC |
190			  ICP_ACCEL_CAPABILITIES_SM3 |
191			  ICP_ACCEL_CAPABILITIES_SM4 |
192			  ICP_ACCEL_CAPABILITIES_AES_V2 |
193			  ICP_ACCEL_CAPABILITIES_ZUC |
194			  ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT |
195			  ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN;
196
197	/* A set bit in fusectl1 means the feature is OFF in this SKU */
198	if (fusectl1 & ICP_ACCEL_GEN4_MASK_CIPHER_SLICE) {
199		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
200		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_HKDF;
201		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
202	}
203
204	if (fusectl1 & ICP_ACCEL_GEN4_MASK_UCS_SLICE) {
205		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
206		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
207		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
208		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
209	}
210
211	if (fusectl1 & ICP_ACCEL_GEN4_MASK_AUTH_SLICE) {
212		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
213		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SHA3;
214		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
215		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
216	}
217
218	if (fusectl1 & ICP_ACCEL_GEN4_MASK_SMX_SLICE) {
219		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM3;
220		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM4;
221	}
222
223	if (fusectl1 & ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE) {
224		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC;
225		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT;
226	}
227
228	if (fusectl1 & ICP_ACCEL_GEN4_MASK_EIA3_SLICE)
229		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_ZUC;
230
231	capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
232			  ICP_ACCEL_CAPABILITIES_SM2 |
233			  ICP_ACCEL_CAPABILITIES_ECEDMONT;
234
235	if (fusectl1 & ICP_ACCEL_GEN4_MASK_PKE_SLICE) {
236		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
237		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;
238		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
239	}
240
241	capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |
242			  ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
243			  ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
244			  ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
245
246	if (fusectl1 & ICP_ACCEL_GEN4_MASK_COMPRESS_SLICE) {
247		capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
248		capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
249		capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
250		capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
251	}
252
253	switch (adf_get_service_enabled(accel_dev)) {
254	case SVC_SYM_ASYM:
255		return capabilities_sym | capabilities_asym;
256	case SVC_DC:
257		return capabilities_dc;
258	case SVC_DCC:
259		/*
260		 * Sym capabilities are available for chaining operations,
261		 * but sym crypto instances cannot be supported
262		 */
263		capabilities_dcc = capabilities_dc | capabilities_sym;
264		capabilities_dcc &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
265		return capabilities_dcc;
266	case SVC_SYM:
267		return capabilities_sym;
268	case SVC_ASYM:
269		return capabilities_asym;
270	case SVC_ASYM_DC:
271		return capabilities_asym | capabilities_dc;
272	case SVC_SYM_DC:
273		return capabilities_sym | capabilities_dc;
274	default:
275		return 0;
276	}
277}
278
279static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
280{
281	if (adf_gen4_init_thd2arb_map(accel_dev))
282		dev_warn(&GET_DEV(accel_dev),
283			 "Failed to generate thread to arbiter mapping");
284
285	return GET_HW_DATA(accel_dev)->thd_to_arb_map;
286}
287
288static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)
289{
290	rl_data->pciout_tb_offset = ADF_GEN4_RL_TOKEN_PCIEOUT_BUCKET_OFFSET;
291	rl_data->pciin_tb_offset = ADF_GEN4_RL_TOKEN_PCIEIN_BUCKET_OFFSET;
292	rl_data->r2l_offset = ADF_GEN4_RL_R2L_OFFSET;
293	rl_data->l2c_offset = ADF_GEN4_RL_L2C_OFFSET;
294	rl_data->c2s_offset = ADF_GEN4_RL_C2S_OFFSET;
295
296	rl_data->pcie_scale_div = ADF_420XX_RL_PCIE_SCALE_FACTOR_DIV;
297	rl_data->pcie_scale_mul = ADF_420XX_RL_PCIE_SCALE_FACTOR_MUL;
298	rl_data->dcpr_correction = ADF_420XX_RL_DCPR_CORRECTION;
299	rl_data->max_tp[SVC_ASYM] = ADF_420XX_RL_MAX_TP_ASYM;
300	rl_data->max_tp[SVC_SYM] = ADF_420XX_RL_MAX_TP_SYM;
301	rl_data->max_tp[SVC_DC] = ADF_420XX_RL_MAX_TP_DC;
302	rl_data->scan_interval = ADF_420XX_RL_SCANS_PER_SEC;
303	rl_data->scale_ref = ADF_420XX_RL_SLICE_REF;
304
305	adf_gen4_init_num_svc_aes(rl_data);
306}
307
308static int get_rp_group(struct adf_accel_dev *accel_dev, u32 ae_mask)
309{
310	switch (ae_mask) {
311	case ADF_AE_GROUP_0:
312		return RP_GROUP_0;
313	case ADF_AE_GROUP_1:
314	case ADF_AE_GROUP_3:
315		return RP_GROUP_1;
316	case ADF_AE_GROUP_2:
317		if (get_fw_config(accel_dev) == adf_fw_cy_config)
318			return RP_GROUP_0;
319		else
320			return RP_GROUP_1;
321	default:
322		dev_dbg(&GET_DEV(accel_dev), "ae_mask not recognized");
323		return -EINVAL;
324	}
325}
326
327static u32 get_ena_thd_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
328{
329	const struct adf_fw_config *fw_config;
330
331	if (obj_num >= uof_get_num_objs(accel_dev))
332		return ADF_GEN4_ENA_THD_MASK_ERROR;
333
334	fw_config = get_fw_config(accel_dev);
335	if (!fw_config)
336		return ADF_GEN4_ENA_THD_MASK_ERROR;
337
338	switch (fw_config[obj_num].obj) {
339	case ADF_FW_ASYM_OBJ:
340		return ENA_THD_MASK_ASYM;
341	case ADF_FW_SYM_OBJ:
342		return ENA_THD_MASK_SYM;
343	case ADF_FW_DC_OBJ:
344		return ENA_THD_MASK_DC;
345	default:
346		return ADF_GEN4_ENA_THD_MASK_ERROR;
347	}
348}
349
350static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num,
351				const char * const fw_objs[], int num_objs)
352{
353	const struct adf_fw_config *fw_config;
354	int id;
355
356	fw_config = get_fw_config(accel_dev);
357	if (fw_config)
358		id = fw_config[obj_num].obj;
359	else
360		id = -EINVAL;
361
362	if (id < 0 || id >= num_objs)
363		return NULL;
364
365	return fw_objs[id];
366}
367
368static const char *uof_get_name_420xx(struct adf_accel_dev *accel_dev, u32 obj_num)
369{
370	int num_fw_objs = ARRAY_SIZE(adf_420xx_fw_objs);
371
372	return uof_get_name(accel_dev, obj_num, adf_420xx_fw_objs, num_fw_objs);
373}
374
375static int uof_get_obj_type(struct adf_accel_dev *accel_dev, u32 obj_num)
376{
377	const struct adf_fw_config *fw_config;
378
379	if (obj_num >= uof_get_num_objs(accel_dev))
380		return -EINVAL;
381
382	fw_config = get_fw_config(accel_dev);
383	if (!fw_config)
384		return -EINVAL;
385
386	return fw_config[obj_num].obj;
387}
388
389static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
390{
391	const struct adf_fw_config *fw_config;
392
393	fw_config = get_fw_config(accel_dev);
394	if (!fw_config)
395		return 0;
396
397	return fw_config[obj_num].ae_mask;
398}
399
400static void adf_gen4_set_err_mask(struct adf_dev_err_mask *dev_err_mask)
401{
402	dev_err_mask->cppagentcmdpar_mask = ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK;
403	dev_err_mask->parerr_ath_cph_mask = ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK;
404	dev_err_mask->parerr_cpr_xlt_mask = ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK;
405	dev_err_mask->parerr_dcpr_ucs_mask = ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK;
406	dev_err_mask->parerr_pke_mask = ADF_420XX_PARITYERRORMASK_PKE_MASK;
407	dev_err_mask->parerr_wat_wcp_mask = ADF_420XX_PARITYERRORMASK_WAT_WCP_MASK;
408	dev_err_mask->ssmfeatren_mask = ADF_420XX_SSMFEATREN_MASK;
409}
410
411void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)
412{
413	hw_data->dev_class = &adf_420xx_class;
414	hw_data->instance_id = adf_420xx_class.instances++;
415	hw_data->num_banks = ADF_GEN4_ETR_MAX_BANKS;
416	hw_data->num_banks_per_vf = ADF_GEN4_NUM_BANKS_PER_VF;
417	hw_data->num_rings_per_bank = ADF_GEN4_NUM_RINGS_PER_BANK;
418	hw_data->num_accel = ADF_GEN4_MAX_ACCELERATORS;
419	hw_data->num_engines = ADF_420XX_MAX_ACCELENGINES;
420	hw_data->num_logical_accel = 1;
421	hw_data->tx_rx_gap = ADF_GEN4_RX_RINGS_OFFSET;
422	hw_data->tx_rings_mask = ADF_GEN4_TX_RINGS_MASK;
423	hw_data->ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;
424	hw_data->alloc_irq = adf_isr_resource_alloc;
425	hw_data->free_irq = adf_isr_resource_free;
426	hw_data->enable_error_correction = adf_gen4_enable_error_correction;
427	hw_data->get_accel_mask = adf_gen4_get_accel_mask;
428	hw_data->get_ae_mask = get_ae_mask;
429	hw_data->get_num_accels = adf_gen4_get_num_accels;
430	hw_data->get_num_aes = adf_gen4_get_num_aes;
431	hw_data->get_sram_bar_id = adf_gen4_get_sram_bar_id;
432	hw_data->get_etr_bar_id = adf_gen4_get_etr_bar_id;
433	hw_data->get_misc_bar_id = adf_gen4_get_misc_bar_id;
434	hw_data->get_arb_info = adf_gen4_get_arb_info;
435	hw_data->get_admin_info = adf_gen4_get_admin_info;
436	hw_data->get_accel_cap = get_accel_cap;
437	hw_data->get_sku = adf_gen4_get_sku;
438	hw_data->init_admin_comms = adf_init_admin_comms;
439	hw_data->exit_admin_comms = adf_exit_admin_comms;
440	hw_data->send_admin_init = adf_send_admin_init;
441	hw_data->init_arb = adf_init_arb;
442	hw_data->exit_arb = adf_exit_arb;
443	hw_data->get_arb_mapping = adf_get_arbiter_mapping;
444	hw_data->enable_ints = adf_gen4_enable_ints;
445	hw_data->init_device = adf_gen4_init_device;
446	hw_data->reset_device = adf_reset_flr;
447	hw_data->admin_ae_mask = ADF_420XX_ADMIN_AE_MASK;
448	hw_data->num_rps = ADF_GEN4_MAX_RPS;
449	hw_data->fw_name = ADF_420XX_FW;
450	hw_data->fw_mmp_name = ADF_420XX_MMP;
451	hw_data->uof_get_name = uof_get_name_420xx;
452	hw_data->uof_get_num_objs = uof_get_num_objs;
453	hw_data->uof_get_obj_type = uof_get_obj_type;
454	hw_data->uof_get_ae_mask = uof_get_ae_mask;
455	hw_data->get_rp_group = get_rp_group;
456	hw_data->get_ena_thd_mask = get_ena_thd_mask;
457	hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;
458	hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
459	hw_data->get_ring_to_svc_map = adf_gen4_get_ring_to_svc_map;
460	hw_data->disable_iov = adf_disable_sriov;
461	hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
462	hw_data->enable_pm = adf_gen4_enable_pm;
463	hw_data->handle_pm_interrupt = adf_gen4_handle_pm_interrupt;
464	hw_data->dev_config = adf_gen4_dev_config;
465	hw_data->start_timer = adf_timer_start;
466	hw_data->stop_timer = adf_timer_stop;
467	hw_data->get_hb_clock = adf_gen4_get_heartbeat_clock;
468	hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;
469	hw_data->clock_frequency = ADF_420XX_AE_FREQ;
470	hw_data->services_supported = adf_gen4_services_supported;
471	hw_data->get_svc_slice_cnt = adf_gen4_get_svc_slice_cnt;
472
473	adf_gen4_set_err_mask(&hw_data->dev_err_mask);
474	adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);
475	adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);
476	adf_gen4_init_dc_ops(&hw_data->dc_ops);
477	adf_gen4_init_ras_ops(&hw_data->ras_ops);
478	adf_gen4_init_tl_data(&hw_data->tl_data);
479	adf_gen4_init_vf_mig_ops(&hw_data->vfmig_ops);
480	adf_init_rl_data(&hw_data->rl_data);
481}
482
483void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data)
484{
485	hw_data->dev_class->instances--;
486}