cptpf_main.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2016 Cavium, Inc.
  4 */
  5
  6#include <linux/device.h>
  7#include <linux/firmware.h>
  8#include <linux/interrupt.h>
  9#include <linux/module.h>
 10#include <linux/moduleparam.h>
 11#include <linux/pci.h>
 12#include <linux/printk.h>
 13
 14#include "cptpf.h"
 15
 16#define DRV_NAME	"thunder-cpt"
 17#define DRV_VERSION	"1.0"
 18
 19static u32 num_vfs = 4; /* Default 4 VF enabled */
 20module_param(num_vfs, uint, 0444);
 21MODULE_PARM_DESC(num_vfs, "Number of VFs to enable(1-16)");
 22
 23/*
 24 * Disable cores specified by coremask
 25 */
 26static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask,
 27			      u8 type, u8 grp)
 28{
 29	u64 pf_exe_ctl;
 30	u32 timeout = 100;
 31	u64 grpmask = 0;
 32	struct device *dev = &cpt->pdev->dev;
 33
 34	if (type == AE_TYPES)
 35		coremask = (coremask << cpt->max_se_cores);
 36
 37	/* Disengage the cores from groups */
 38	grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));
 39	cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),
 40			(grpmask & ~coremask));
 41	udelay(CSR_DELAY);
 42	grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));
 43	while (grp & coremask) {
 44		dev_err(dev, "Cores still busy %llx", coremask);
 45		grp = cpt_read_csr64(cpt->reg_base,
 46				     CPTX_PF_EXEC_BUSY(0));
 47		if (!timeout--)
 48			break;
 49
 50		udelay(CSR_DELAY);
 51	}
 52
 53	/* Disable the cores */
 54	pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));
 55	cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),
 56			(pf_exe_ctl & ~coremask));
 57	udelay(CSR_DELAY);
 58}
 59
 60/*
 61 * Enable cores specified by coremask
 62 */
 63static void cpt_enable_cores(struct cpt_device *cpt, u64 coremask,
 64			     u8 type)
 65{
 66	u64 pf_exe_ctl;
 67
 68	if (type == AE_TYPES)
 69		coremask = (coremask << cpt->max_se_cores);
 70
 71	pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));
 72	cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),
 73			(pf_exe_ctl | coremask));
 74	udelay(CSR_DELAY);
 75}
 76
 77static void cpt_configure_group(struct cpt_device *cpt, u8 grp,
 78				u64 coremask, u8 type)
 79{
 80	u64 pf_gx_en = 0;
 81
 82	if (type == AE_TYPES)
 83		coremask = (coremask << cpt->max_se_cores);
 84
 85	pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));
 86	cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),
 87			(pf_gx_en | coremask));
 88	udelay(CSR_DELAY);
 89}
 90
 91static void cpt_disable_mbox_interrupts(struct cpt_device *cpt)
 92{
 93	/* Clear mbox(0) interupts for all vfs */
 94	cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull);
 95}
 96
 97static void cpt_disable_ecc_interrupts(struct cpt_device *cpt)
 98{
 99	/* Clear ecc(0) interupts for all vfs */
100	cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull);
101}
102
103static void cpt_disable_exec_interrupts(struct cpt_device *cpt)
104{
105	/* Clear exec interupts for all vfs */
106	cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull);
107}
108
109static void cpt_disable_all_interrupts(struct cpt_device *cpt)
110{
111	cpt_disable_mbox_interrupts(cpt);
112	cpt_disable_ecc_interrupts(cpt);
113	cpt_disable_exec_interrupts(cpt);
114}
115
116static void cpt_enable_mbox_interrupts(struct cpt_device *cpt)
117{
118	/* Set mbox(0) interupts for all vfs */
119	cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull);
120}
121
122static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
123{
124	int ret = 0, core = 0, shift = 0;
125	u32 total_cores = 0;
126	struct device *dev = &cpt->pdev->dev;
127
128	if (!mcode || !mcode->code) {
129		dev_err(dev, "Either the mcode is null or data is NULL\n");
130		return -EINVAL;
131	}
132
133	if (mcode->code_size == 0) {
134		dev_err(dev, "microcode size is 0\n");
135		return -EINVAL;
136	}
137
138	/* Assumes 0-9 are SE cores for UCODE_BASE registers and
139	 * AE core bases follow
140	 */
141	if (mcode->is_ae) {
142		core = CPT_MAX_SE_CORES; /* start couting from 10 */
143		total_cores = CPT_MAX_TOTAL_CORES; /* upto 15 */
144	} else {
145		core = 0; /* start couting from 0 */
146		total_cores = CPT_MAX_SE_CORES; /* upto 9 */
147	}
148
149	/* Point to microcode for each core of the group */
150	for (; core < total_cores ; core++, shift++) {
151		if (mcode->core_mask & (1 << shift)) {
152			cpt_write_csr64(cpt->reg_base,
153					CPTX_PF_ENGX_UCODE_BASE(0, core),
154					(u64)mcode->phys_base);
155		}
156	}
157	return ret;
158}
159
160static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode)
161{
162	int ret = 0;
163	struct device *dev = &cpt->pdev->dev;
164
165	/* Make device not ready */
166	cpt->flags &= ~CPT_FLAG_DEVICE_READY;
167	/* Disable All PF interrupts */
168	cpt_disable_all_interrupts(cpt);
169	/* Calculate mcode group and coremasks */
170	if (mcode->is_ae) {
171		if (mcode->num_cores > cpt->max_ae_cores) {
172			dev_err(dev, "Requested for more cores than available AE cores\n");
173			ret = -EINVAL;
174			goto cpt_init_fail;
175		}
176
177		if (cpt->next_group >= CPT_MAX_CORE_GROUPS) {
178			dev_err(dev, "Can't load, all eight microcode groups in use");
179			return -ENFILE;
180		}
181
182		mcode->group = cpt->next_group;
183		/* Convert requested cores to mask */
184		mcode->core_mask = GENMASK(mcode->num_cores, 0);
185		cpt_disable_cores(cpt, mcode->core_mask, AE_TYPES,
186				  mcode->group);
187		/* Load microcode for AE engines */
188		ret = cpt_load_microcode(cpt, mcode);
189		if (ret) {
190			dev_err(dev, "Microcode load Failed for %s\n",
191				mcode->version);
192			goto cpt_init_fail;
193		}
194		cpt->next_group++;
195		/* Configure group mask for the mcode */
196		cpt_configure_group(cpt, mcode->group, mcode->core_mask,
197				    AE_TYPES);
198		/* Enable AE cores for the group mask */
199		cpt_enable_cores(cpt, mcode->core_mask, AE_TYPES);
200	} else {
201		if (mcode->num_cores > cpt->max_se_cores) {
202			dev_err(dev, "Requested for more cores than available SE cores\n");
203			ret = -EINVAL;
204			goto cpt_init_fail;
205		}
206		if (cpt->next_group >= CPT_MAX_CORE_GROUPS) {
207			dev_err(dev, "Can't load, all eight microcode groups in use");
208			return -ENFILE;
209		}
210
211		mcode->group = cpt->next_group;
212		/* Covert requested cores to mask */
213		mcode->core_mask = GENMASK(mcode->num_cores, 0);
214		cpt_disable_cores(cpt, mcode->core_mask, SE_TYPES,
215				  mcode->group);
216		/* Load microcode for SE engines */
217		ret = cpt_load_microcode(cpt, mcode);
218		if (ret) {
219			dev_err(dev, "Microcode load Failed for %s\n",
220				mcode->version);
221			goto cpt_init_fail;
222		}
223		cpt->next_group++;
224		/* Configure group mask for the mcode */
225		cpt_configure_group(cpt, mcode->group, mcode->core_mask,
226				    SE_TYPES);
227		/* Enable SE cores for the group mask */
228		cpt_enable_cores(cpt, mcode->core_mask, SE_TYPES);
229	}
230
231	/* Enabled PF mailbox interrupts */
232	cpt_enable_mbox_interrupts(cpt);
233	cpt->flags |= CPT_FLAG_DEVICE_READY;
234
235	return ret;
236
237cpt_init_fail:
238	/* Enabled PF mailbox interrupts */
239	cpt_enable_mbox_interrupts(cpt);
240
241	return ret;
242}
243
244struct ucode_header {
245	u8 version[CPT_UCODE_VERSION_SZ];
246	__be32 code_length;
247	u32 data_length;
248	u64 sram_address;
249};
250
251static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae)
252{
253	const struct firmware *fw_entry;
254	struct device *dev = &cpt->pdev->dev;
255	struct ucode_header *ucode;
256	unsigned int code_length;
257	struct microcode *mcode;
258	int j, ret = 0;
259
260	ret = request_firmware(&fw_entry, fw, dev);
261	if (ret)
262		return ret;
263
264	ucode = (struct ucode_header *)fw_entry->data;
265	mcode = &cpt->mcode[cpt->next_mc_idx];
266	memcpy(mcode->version, (u8 *)fw_entry->data, CPT_UCODE_VERSION_SZ);
267	code_length = ntohl(ucode->code_length);
268	if (code_length == 0 || code_length >= INT_MAX / 2) {
269		ret = -EINVAL;
270		goto fw_release;
271	}
272	mcode->code_size = code_length * 2;
273
274	mcode->is_ae = is_ae;
275	mcode->core_mask = 0ULL;
276	mcode->num_cores = is_ae ? 6 : 10;
277
278	/*  Allocate DMAable space */
279	mcode->code = dma_alloc_coherent(&cpt->pdev->dev, mcode->code_size,
280					 &mcode->phys_base, GFP_KERNEL);
281	if (!mcode->code) {
282		dev_err(dev, "Unable to allocate space for microcode");
283		ret = -ENOMEM;
284		goto fw_release;
285	}
286
287	memcpy((void *)mcode->code, (void *)(fw_entry->data + sizeof(*ucode)),
288	       mcode->code_size);
289
290	/* Byte swap 64-bit */
291	for (j = 0; j < (mcode->code_size / 8); j++)
292		((__be64 *)mcode->code)[j] = cpu_to_be64(((u64 *)mcode->code)[j]);
293	/*  MC needs 16-bit swap */
294	for (j = 0; j < (mcode->code_size / 2); j++)
295		((__be16 *)mcode->code)[j] = cpu_to_be16(((u16 *)mcode->code)[j]);
296
297	dev_dbg(dev, "mcode->code_size = %u\n", mcode->code_size);
298	dev_dbg(dev, "mcode->is_ae = %u\n", mcode->is_ae);
299	dev_dbg(dev, "mcode->num_cores = %u\n", mcode->num_cores);
300	dev_dbg(dev, "mcode->code = %llx\n", (u64)mcode->code);
301	dev_dbg(dev, "mcode->phys_base = %llx\n", mcode->phys_base);
302
303	ret = do_cpt_init(cpt, mcode);
304	if (ret) {
305		dma_free_coherent(&cpt->pdev->dev, mcode->code_size,
306				  mcode->code, mcode->phys_base);
307		dev_err(dev, "do_cpt_init failed with ret: %d\n", ret);
308		goto fw_release;
309	}
310
311	dev_info(dev, "Microcode Loaded %s\n", mcode->version);
312	mcode->is_mc_valid = 1;
313	cpt->next_mc_idx++;
314
315fw_release:
316	release_firmware(fw_entry);
317
318	return ret;
319}
320
321static int cpt_ucode_load(struct cpt_device *cpt)
322{
323	int ret = 0;
324	struct device *dev = &cpt->pdev->dev;
325
326	ret = cpt_ucode_load_fw(cpt, "cpt8x-mc-ae.out", true);
327	if (ret) {
328		dev_err(dev, "ae:cpt_ucode_load failed with ret: %d\n", ret);
329		return ret;
330	}
331	ret = cpt_ucode_load_fw(cpt, "cpt8x-mc-se.out", false);
332	if (ret) {
333		dev_err(dev, "se:cpt_ucode_load failed with ret: %d\n", ret);
334		return ret;
335	}
336
337	return ret;
338}
339
340static irqreturn_t cpt_mbx0_intr_handler(int irq, void *cpt_irq)
341{
342	struct cpt_device *cpt = (struct cpt_device *)cpt_irq;
343
344	cpt_mbox_intr_handler(cpt, 0);
345
346	return IRQ_HANDLED;
347}
348
349static void cpt_reset(struct cpt_device *cpt)
350{
351	cpt_write_csr64(cpt->reg_base, CPTX_PF_RESET(0), 1);
352}
353
354static void cpt_find_max_enabled_cores(struct cpt_device *cpt)
355{
356	union cptx_pf_constants pf_cnsts = {0};
357
358	pf_cnsts.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_CONSTANTS(0));
359	cpt->max_se_cores = pf_cnsts.s.se;
360	cpt->max_ae_cores = pf_cnsts.s.ae;
361}
362
363static u32 cpt_check_bist_status(struct cpt_device *cpt)
364{
365	union cptx_pf_bist_status bist_sts = {0};
366
367	bist_sts.u = cpt_read_csr64(cpt->reg_base,
368				    CPTX_PF_BIST_STATUS(0));
369
370	return bist_sts.u;
371}
372
373static u64 cpt_check_exe_bist_status(struct cpt_device *cpt)
374{
375	union cptx_pf_exe_bist_status bist_sts = {0};
376
377	bist_sts.u = cpt_read_csr64(cpt->reg_base,
378				    CPTX_PF_EXE_BIST_STATUS(0));
379
380	return bist_sts.u;
381}
382
383static void cpt_disable_all_cores(struct cpt_device *cpt)
384{
385	u32 grp, timeout = 100;
386	struct device *dev = &cpt->pdev->dev;
387
388	/* Disengage the cores from groups */
389	for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) {
390		cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0);
391		udelay(CSR_DELAY);
392	}
393
394	grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));
395	while (grp) {
396		dev_err(dev, "Cores still busy");
397		grp = cpt_read_csr64(cpt->reg_base,
398				     CPTX_PF_EXEC_BUSY(0));
399		if (!timeout--)
400			break;
401
402		udelay(CSR_DELAY);
403	}
404	/* Disable the cores */
405	cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0);
406}
407
408/*
409 * Ensure all cores are disengaged from all groups by
410 * calling cpt_disable_all_cores() before calling this
411 * function.
412 */
413static void cpt_unload_microcode(struct cpt_device *cpt)
414{
415	u32 grp = 0, core;
416
417	/* Free microcode bases and reset group masks */
418	for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) {
419		struct microcode *mcode = &cpt->mcode[grp];
420
421		if (cpt->mcode[grp].code)
422			dma_free_coherent(&cpt->pdev->dev, mcode->code_size,
423					  mcode->code, mcode->phys_base);
424		mcode->code = NULL;
425	}
426	/* Clear UCODE_BASE registers for all engines */
427	for (core = 0; core < CPT_MAX_TOTAL_CORES; core++)
428		cpt_write_csr64(cpt->reg_base,
429				CPTX_PF_ENGX_UCODE_BASE(0, core), 0ull);
430}
431
432static int cpt_device_init(struct cpt_device *cpt)
433{
434	u64 bist;
435	struct device *dev = &cpt->pdev->dev;
436
437	/* Reset the PF when probed first */
438	cpt_reset(cpt);
439	msleep(100);
440
441	/*Check BIST status*/
442	bist = (u64)cpt_check_bist_status(cpt);
443	if (bist) {
444		dev_err(dev, "RAM BIST failed with code 0x%llx", bist);
445		return -ENODEV;
446	}
447
448	bist = cpt_check_exe_bist_status(cpt);
449	if (bist) {
450		dev_err(dev, "Engine BIST failed with code 0x%llx", bist);
451		return -ENODEV;
452	}
453
454	/*Get CLK frequency*/
455	/*Get max enabled cores */
456	cpt_find_max_enabled_cores(cpt);
457	/*Disable all cores*/
458	cpt_disable_all_cores(cpt);
459	/*Reset device parameters*/
460	cpt->next_mc_idx   = 0;
461	cpt->next_group = 0;
462	/* PF is ready */
463	cpt->flags |= CPT_FLAG_DEVICE_READY;
464
465	return 0;
466}
467
468static int cpt_register_interrupts(struct cpt_device *cpt)
469{
470	int ret;
471	struct device *dev = &cpt->pdev->dev;
472
473	/* Enable MSI-X */
474	ret = pci_alloc_irq_vectors(cpt->pdev, CPT_PF_MSIX_VECTORS,
475			CPT_PF_MSIX_VECTORS, PCI_IRQ_MSIX);
476	if (ret < 0) {
477		dev_err(&cpt->pdev->dev, "Request for #%d msix vectors failed\n",
478			CPT_PF_MSIX_VECTORS);
479		return ret;
480	}
481
482	/* Register mailbox interrupt handlers */
483	ret = request_irq(pci_irq_vector(cpt->pdev, CPT_PF_INT_VEC_E_MBOXX(0)),
484			  cpt_mbx0_intr_handler, 0, "CPT Mbox0", cpt);
485	if (ret)
486		goto fail;
487
488	/* Enable mailbox interrupt */
489	cpt_enable_mbox_interrupts(cpt);
490	return 0;
491
492fail:
493	dev_err(dev, "Request irq failed\n");
494	pci_disable_msix(cpt->pdev);
495	return ret;
496}
497
498static void cpt_unregister_interrupts(struct cpt_device *cpt)
499{
500	free_irq(pci_irq_vector(cpt->pdev, CPT_PF_INT_VEC_E_MBOXX(0)), cpt);
501	pci_disable_msix(cpt->pdev);
502}
503
504static int cpt_sriov_init(struct cpt_device *cpt, int num_vfs)
505{
506	int pos = 0;
507	int err;
508	u16 total_vf_cnt;
509	struct pci_dev *pdev = cpt->pdev;
510
511	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
512	if (!pos) {
513		dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
514		return -ENODEV;
515	}
516
517	cpt->num_vf_en = num_vfs; /* User requested VFs */
518	pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
519	if (total_vf_cnt < cpt->num_vf_en)
520		cpt->num_vf_en = total_vf_cnt;
521
522	if (!total_vf_cnt)
523		return 0;
524
525	/*Enabled the available VFs */
526	err = pci_enable_sriov(pdev, cpt->num_vf_en);
527	if (err) {
528		dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
529			cpt->num_vf_en);
530		cpt->num_vf_en = 0;
531		return err;
532	}
533
534	/* TODO: Optionally enable static VQ priorities feature */
535
536	dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
537		 cpt->num_vf_en);
538
539	cpt->flags |= CPT_FLAG_SRIOV_ENABLED;
540
541	return 0;
542}
543
544static int cpt_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
545{
546	struct device *dev = &pdev->dev;
547	struct cpt_device *cpt;
548	int err;
549
550	if (num_vfs > 16 || num_vfs < 4) {
551		dev_warn(dev, "Invalid vf count %d, Resetting it to 4(default)\n",
552			 num_vfs);
553		num_vfs = 4;
554	}
555
556	cpt = devm_kzalloc(dev, sizeof(*cpt), GFP_KERNEL);
557	if (!cpt)
558		return -ENOMEM;
559
560	pci_set_drvdata(pdev, cpt);
561	cpt->pdev = pdev;
562	err = pci_enable_device(pdev);
563	if (err) {
564		dev_err(dev, "Failed to enable PCI device\n");
565		pci_set_drvdata(pdev, NULL);
566		return err;
567	}
568
569	err = pci_request_regions(pdev, DRV_NAME);
570	if (err) {
571		dev_err(dev, "PCI request regions failed 0x%x\n", err);
572		goto cpt_err_disable_device;
573	}
574
575	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
576	if (err) {
577		dev_err(dev, "Unable to get usable 48-bit DMA configuration\n");
578		goto cpt_err_release_regions;
579	}
580
581	/* MAP PF's configuration registers */
582	cpt->reg_base = pcim_iomap(pdev, 0, 0);
583	if (!cpt->reg_base) {
584		dev_err(dev, "Cannot map config register space, aborting\n");
585		err = -ENOMEM;
586		goto cpt_err_release_regions;
587	}
588
589	/* CPT device HW initialization */
590	cpt_device_init(cpt);
591
592	/* Register interrupts */
593	err = cpt_register_interrupts(cpt);
594	if (err)
595		goto cpt_err_release_regions;
596
597	err = cpt_ucode_load(cpt);
598	if (err)
599		goto cpt_err_unregister_interrupts;
600
601	/* Configure SRIOV */
602	err = cpt_sriov_init(cpt, num_vfs);
603	if (err)
604		goto cpt_err_unregister_interrupts;
605
606	return 0;
607
608cpt_err_unregister_interrupts:
609	cpt_unregister_interrupts(cpt);
610cpt_err_release_regions:
611	pci_release_regions(pdev);
612cpt_err_disable_device:
613	pci_disable_device(pdev);
614	pci_set_drvdata(pdev, NULL);
615	return err;
616}
617
618static void cpt_remove(struct pci_dev *pdev)
619{
620	struct cpt_device *cpt = pci_get_drvdata(pdev);
621
622	/* Disengage SE and AE cores from all groups*/
623	cpt_disable_all_cores(cpt);
624	/* Unload microcodes */
625	cpt_unload_microcode(cpt);
626	cpt_unregister_interrupts(cpt);
627	pci_disable_sriov(pdev);
628	pci_release_regions(pdev);
629	pci_disable_device(pdev);
630	pci_set_drvdata(pdev, NULL);
631}
632
633static void cpt_shutdown(struct pci_dev *pdev)
634{
635	struct cpt_device *cpt = pci_get_drvdata(pdev);
636
637	if (!cpt)
638		return;
639
640	dev_info(&pdev->dev, "Shutdown device %x:%x.\n",
641		 (u32)pdev->vendor, (u32)pdev->device);
642
643	cpt_unregister_interrupts(cpt);
644	pci_release_regions(pdev);
645	pci_disable_device(pdev);
646	pci_set_drvdata(pdev, NULL);
647}
648
649/* Supported devices */
650static const struct pci_device_id cpt_id_table[] = {
651	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_PF_DEVICE_ID) },
652	{ 0, }  /* end of table */
653};
654
655static struct pci_driver cpt_pci_driver = {
656	.name = DRV_NAME,
657	.id_table = cpt_id_table,
658	.probe = cpt_probe,
659	.remove = cpt_remove,
660	.shutdown = cpt_shutdown,
661};
662
663module_pci_driver(cpt_pci_driver);
664
665MODULE_AUTHOR("George Cherian <george.cherian@cavium.com>");
666MODULE_DESCRIPTION("Cavium Thunder CPT Physical Function Driver");
667MODULE_LICENSE("GPL v2");
668MODULE_VERSION(DRV_VERSION);
669MODULE_DEVICE_TABLE(pci, cpt_id_table);