qcom-cpufreq-nvmem.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4 */
  5
  6/*
  7 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
  8 * the CPU frequency subset and voltage value of each OPP varies
  9 * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
 10 * defines the voltage and frequency value based on the msm-id in SMEM
 11 * and speedbin blown in the efuse combination.
 12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
 13 * to provide the OPP framework with required information.
 14 * This is used to determine the voltage and frequency value for each OPP of
 15 * operating-points-v2 table when it is parsed by the OPP framework.
 16 */
 17
 18#include <linux/cpu.h>
 19#include <linux/err.h>
 20#include <linux/init.h>
 21#include <linux/kernel.h>
 22#include <linux/module.h>
 23#include <linux/nvmem-consumer.h>
 24#include <linux/of.h>
 25#include <linux/platform_device.h>
 26#include <linux/pm.h>
 27#include <linux/pm_domain.h>
 28#include <linux/pm_opp.h>
 29#include <linux/pm_runtime.h>
 30#include <linux/slab.h>
 31#include <linux/soc/qcom/smem.h>
 32
 33#include <dt-bindings/arm/qcom,ids.h>
 34
 35enum ipq806x_versions {
 36	IPQ8062_VERSION = 0,
 37	IPQ8064_VERSION,
 38	IPQ8065_VERSION,
 39};
 40
 41#define IPQ6000_VERSION	BIT(2)
 42
 43enum ipq8074_versions {
 44	IPQ8074_HAWKEYE_VERSION = 0,
 45	IPQ8074_ACORN_VERSION,
 46};
 47
 48struct qcom_cpufreq_drv;
 49
 50struct qcom_cpufreq_match_data {
 51	int (*get_version)(struct device *cpu_dev,
 52			   struct nvmem_cell *speedbin_nvmem,
 53			   char **pvs_name,
 54			   struct qcom_cpufreq_drv *drv);
 55	const char **pd_names;
 56	unsigned int num_pd_names;
 57};
 58
 59struct qcom_cpufreq_drv_cpu {
 60	int opp_token;
 61	struct dev_pm_domain_list *pd_list;
 62};
 63
 64struct qcom_cpufreq_drv {
 65	u32 versions;
 66	const struct qcom_cpufreq_match_data *data;
 67	struct qcom_cpufreq_drv_cpu cpus[];
 68};
 69
 70static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
 71
 72static int qcom_cpufreq_simple_get_version(struct device *cpu_dev,
 73					   struct nvmem_cell *speedbin_nvmem,
 74					   char **pvs_name,
 75					   struct qcom_cpufreq_drv *drv)
 76{
 77	u8 *speedbin;
 78
 79	*pvs_name = NULL;
 80	speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
 81	if (IS_ERR(speedbin))
 82		return PTR_ERR(speedbin);
 83
 84	dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin);
 85	drv->versions = 1 << *speedbin;
 86	kfree(speedbin);
 87	return 0;
 88}
 89
 90static void get_krait_bin_format_a(struct device *cpu_dev,
 91					  int *speed, int *pvs,
 92					  u8 *buf)
 93{
 94	u32 pte_efuse;
 95
 96	pte_efuse = *((u32 *)buf);
 97
 98	*speed = pte_efuse & 0xf;
 99	if (*speed == 0xf)
100		*speed = (pte_efuse >> 4) & 0xf;
101
102	if (*speed == 0xf) {
103		*speed = 0;
104		dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
105	} else {
106		dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
107	}
108
109	*pvs = (pte_efuse >> 10) & 0x7;
110	if (*pvs == 0x7)
111		*pvs = (pte_efuse >> 13) & 0x7;
112
113	if (*pvs == 0x7) {
114		*pvs = 0;
115		dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
116	} else {
117		dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
118	}
119}
120
121static void get_krait_bin_format_b(struct device *cpu_dev,
122					  int *speed, int *pvs, int *pvs_ver,
123					  u8 *buf)
124{
125	u32 pte_efuse, redundant_sel;
126
127	pte_efuse = *((u32 *)buf);
128	redundant_sel = (pte_efuse >> 24) & 0x7;
129
130	*pvs_ver = (pte_efuse >> 4) & 0x3;
131
132	switch (redundant_sel) {
133	case 1:
134		*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
135		*speed = (pte_efuse >> 27) & 0xf;
136		break;
137	case 2:
138		*pvs = (pte_efuse >> 27) & 0xf;
139		*speed = pte_efuse & 0x7;
140		break;
141	default:
142		/* 4 bits of PVS are in efuse register bits 31, 8-6. */
143		*pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
144		*speed = pte_efuse & 0x7;
145	}
146
147	/* Check SPEED_BIN_BLOW_STATUS */
148	if (pte_efuse & BIT(3)) {
149		dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
150	} else {
151		dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
152		*speed = 0;
153	}
154
155	/* Check PVS_BLOW_STATUS */
156	pte_efuse = *(((u32 *)buf) + 1);
157	pte_efuse &= BIT(21);
158	if (pte_efuse) {
159		dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
160	} else {
161		dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
162		*pvs = 0;
163	}
164
165	dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
166}
167
168static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
169					  struct nvmem_cell *speedbin_nvmem,
170					  char **pvs_name,
171					  struct qcom_cpufreq_drv *drv)
172{
173	size_t len;
174	u32 msm_id;
175	u8 *speedbin;
176	int ret;
177	*pvs_name = NULL;
178
179	ret = qcom_smem_get_soc_id(&msm_id);
180	if (ret)
181		return ret;
182
183	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
184	if (IS_ERR(speedbin))
185		return PTR_ERR(speedbin);
186
187	switch (msm_id) {
188	case QCOM_ID_MSM8996:
189	case QCOM_ID_APQ8096:
190	case QCOM_ID_IPQ5332:
191	case QCOM_ID_IPQ5322:
192	case QCOM_ID_IPQ5312:
193	case QCOM_ID_IPQ5302:
194	case QCOM_ID_IPQ5300:
195	case QCOM_ID_IPQ5321:
196	case QCOM_ID_IPQ9514:
197	case QCOM_ID_IPQ9550:
198	case QCOM_ID_IPQ9554:
199	case QCOM_ID_IPQ9570:
200	case QCOM_ID_IPQ9574:
201		drv->versions = 1 << (unsigned int)(*speedbin);
202		break;
203	case QCOM_ID_IPQ5424:
204	case QCOM_ID_IPQ5404:
205		drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0);
206		break;
207	case QCOM_ID_MSM8996SG:
208	case QCOM_ID_APQ8096SG:
209		drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
210		break;
211	default:
212		BUG();
213		break;
214	}
215
216	kfree(speedbin);
217	return 0;
218}
219
220static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
221					   struct nvmem_cell *speedbin_nvmem,
222					   char **pvs_name,
223					   struct qcom_cpufreq_drv *drv)
224{
225	int speed = 0, pvs = 0, pvs_ver = 0;
226	u8 *speedbin;
227	size_t len;
228	int ret = 0;
229
230	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
231
232	if (IS_ERR(speedbin))
233		return PTR_ERR(speedbin);
234
235	switch (len) {
236	case 4:
237		get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
238		break;
239	case 8:
240		get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
241				       speedbin);
242		break;
243	default:
244		dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
245		ret = -ENODEV;
246		goto len_error;
247	}
248
249	snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
250		 speed, pvs, pvs_ver);
251
252	drv->versions = (1 << speed);
253
254len_error:
255	kfree(speedbin);
256	return ret;
257}
258
259static const struct of_device_id qcom_cpufreq_ipq806x_match_list[] __maybe_unused = {
260	{ .compatible = "qcom,ipq8062", .data = (const void *)QCOM_ID_IPQ8062 },
261	{ .compatible = "qcom,ipq8064", .data = (const void *)QCOM_ID_IPQ8064 },
262	{ .compatible = "qcom,ipq8065", .data = (const void *)QCOM_ID_IPQ8065 },
263	{ .compatible = "qcom,ipq8066", .data = (const void *)QCOM_ID_IPQ8066 },
264	{ .compatible = "qcom,ipq8068", .data = (const void *)QCOM_ID_IPQ8068 },
265	{ .compatible = "qcom,ipq8069", .data = (const void *)QCOM_ID_IPQ8069 },
266	{ /* sentinel */ }
267};
268
269static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
270					     struct nvmem_cell *speedbin_nvmem,
271					     char **pvs_name,
272					     struct qcom_cpufreq_drv *drv)
273{
274	int msm_id = -1, ret = 0;
275	int speed = 0, pvs = 0;
276	u8 *speedbin;
277	size_t len;
278
279	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
280	if (IS_ERR(speedbin))
281		return PTR_ERR(speedbin);
282
283	if (len != 4) {
284		dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
285		ret = -ENODEV;
286		goto exit;
287	}
288
289	get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
290
291	ret = qcom_smem_get_soc_id(&msm_id);
292	if (ret == -ENODEV) {
293		const struct of_device_id *match;
294		struct device_node *root;
295
296		root = of_find_node_by_path("/");
297		if (!root) {
298			ret = -ENODEV;
299			goto exit;
300		}
301
302		/* Fallback to compatible match with no SMEM initialized */
303		match = of_match_node(qcom_cpufreq_ipq806x_match_list, root);
304		of_node_put(root);
305		if (!match) {
306			ret = -ENODEV;
307			goto exit;
308		}
309
310		/* We found a matching device, get the msm_id from the data entry */
311		msm_id = (int)(uintptr_t)match->data;
312		ret = 0;
313	} else if (ret) {
314		goto exit;
315	}
316
317	switch (msm_id) {
318	case QCOM_ID_IPQ8062:
319		drv->versions = BIT(IPQ8062_VERSION);
320		break;
321	case QCOM_ID_IPQ8064:
322	case QCOM_ID_IPQ8066:
323	case QCOM_ID_IPQ8068:
324		drv->versions = BIT(IPQ8064_VERSION);
325		break;
326	case QCOM_ID_IPQ8065:
327	case QCOM_ID_IPQ8069:
328		drv->versions = BIT(IPQ8065_VERSION);
329		break;
330	default:
331		dev_err(cpu_dev,
332			"SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
333			msm_id);
334		drv->versions = BIT(IPQ8062_VERSION);
335		break;
336	}
337
338	/* IPQ8064 speed is never fused. Only pvs values are fused. */
339	snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs);
340
341exit:
342	kfree(speedbin);
343	return ret;
344}
345
346static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
347					     struct nvmem_cell *speedbin_nvmem,
348					     char **pvs_name,
349					     struct qcom_cpufreq_drv *drv)
350{
351	u32 msm_id;
352	int ret;
353	u8 *speedbin;
354	*pvs_name = NULL;
355
356	ret = qcom_smem_get_soc_id(&msm_id);
357	if (ret)
358		return ret;
359
360	speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
361	if (IS_ERR(speedbin))
362		return PTR_ERR(speedbin);
363
364	switch (msm_id) {
365	case QCOM_ID_IPQ6005:
366	case QCOM_ID_IPQ6010:
367	case QCOM_ID_IPQ6018:
368	case QCOM_ID_IPQ6028:
369		/* Fuse Value    Freq    BIT to set
370		 * ---------------------------------
371		 *   2’b0     No Limit     BIT(0)
372		 *   2’b1     1.5 GHz      BIT(1)
373		 */
374		drv->versions = 1 << (unsigned int)(*speedbin);
375		break;
376	case QCOM_ID_IPQ6000:
377		/*
378		 * IPQ6018 family only has one bit to advertise the CPU
379		 * speed-bin, but that is not enough for IPQ6000 which
380		 * is only rated up to 1.2GHz.
381		 * So for IPQ6000 manually set BIT(2) based on SMEM ID.
382		 */
383		drv->versions = IPQ6000_VERSION;
384		break;
385	default:
386		dev_err(cpu_dev,
387			"SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
388			msm_id);
389		drv->versions = IPQ6000_VERSION;
390		break;
391	}
392
393	kfree(speedbin);
394	return 0;
395}
396
397static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
398					     struct nvmem_cell *speedbin_nvmem,
399					     char **pvs_name,
400					     struct qcom_cpufreq_drv *drv)
401{
402	u32 msm_id;
403	int ret;
404	*pvs_name = NULL;
405
406	ret = qcom_smem_get_soc_id(&msm_id);
407	if (ret)
408		return ret;
409
410	switch (msm_id) {
411	case QCOM_ID_IPQ8070A:
412	case QCOM_ID_IPQ8071A:
413	case QCOM_ID_IPQ8172:
414	case QCOM_ID_IPQ8173:
415	case QCOM_ID_IPQ8174:
416		drv->versions = BIT(IPQ8074_ACORN_VERSION);
417		break;
418	case QCOM_ID_IPQ8072A:
419	case QCOM_ID_IPQ8074A:
420	case QCOM_ID_IPQ8076A:
421	case QCOM_ID_IPQ8078A:
422		drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
423		break;
424	default:
425		dev_err(cpu_dev,
426			"SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
427			msm_id);
428		drv->versions = BIT(IPQ8074_ACORN_VERSION);
429		break;
430	}
431
432	return 0;
433}
434
435static const struct qcom_cpufreq_match_data match_data_kryo = {
436	.get_version = qcom_cpufreq_kryo_name_version,
437};
438
439static const struct qcom_cpufreq_match_data match_data_krait = {
440	.get_version = qcom_cpufreq_krait_name_version,
441};
442
443static const struct qcom_cpufreq_match_data match_data_msm8909 = {
444	.get_version = qcom_cpufreq_simple_get_version,
445	.pd_names = (const char *[]) { "perf" },
446	.num_pd_names = 1,
447};
448
449static const struct qcom_cpufreq_match_data match_data_qcs404 = {
450	.pd_names = (const char *[]) { "cpr" },
451	.num_pd_names = 1,
452};
453
454static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
455	.get_version = qcom_cpufreq_ipq6018_name_version,
456};
457
458static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
459	.get_version = qcom_cpufreq_ipq8064_name_version,
460};
461
462static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
463	.get_version = qcom_cpufreq_ipq8074_name_version,
464};
465
466static void qcom_cpufreq_suspend_pd_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu)
467{
468	struct dev_pm_domain_list *pd_list = drv->cpus[cpu].pd_list;
469	int i;
470
471	if (!pd_list)
472		return;
473
474	for (i = 0; i < pd_list->num_pds; i++)
475		device_set_awake_path(pd_list->pd_devs[i]);
476}
477
478static int qcom_cpufreq_probe(struct platform_device *pdev)
479{
480	struct qcom_cpufreq_drv *drv;
481	struct nvmem_cell *speedbin_nvmem;
482	struct device *cpu_dev;
483	char pvs_name_buffer[] = "speedXX-pvsXX-vXX";
484	char *pvs_name = pvs_name_buffer;
485	unsigned cpu;
486	const struct of_device_id *match;
487	int ret;
488
489	cpu_dev = get_cpu_device(0);
490	if (!cpu_dev)
491		return -ENODEV;
492
493	struct device_node *np __free(device_node) =
494		dev_pm_opp_of_get_opp_desc_node(cpu_dev);
495	if (!np)
496		return -ENOENT;
497
498	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
499	      of_device_is_compatible(np, "operating-points-v2-krait-cpu");
500	if (!ret)
501		return -ENOENT;
502
503	drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()),
504		           GFP_KERNEL);
505	if (!drv)
506		return -ENOMEM;
507
508	match = pdev->dev.platform_data;
509	drv->data = match->data;
510	if (!drv->data)
511		return -ENODEV;
512
513	if (drv->data->get_version) {
514		speedbin_nvmem = of_nvmem_cell_get(np, NULL);
515		if (IS_ERR(speedbin_nvmem))
516			return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
517					     "Could not get nvmem cell\n");
518
519		ret = drv->data->get_version(cpu_dev,
520							speedbin_nvmem, &pvs_name, drv);
521		if (ret) {
522			nvmem_cell_put(speedbin_nvmem);
523			return ret;
524		}
525		nvmem_cell_put(speedbin_nvmem);
526	}
527
528	for_each_present_cpu(cpu) {
529		struct dev_pm_opp_config config = {
530			.supported_hw = NULL,
531		};
532
533		cpu_dev = get_cpu_device(cpu);
534		if (NULL == cpu_dev) {
535			ret = -ENODEV;
536			goto free_opp;
537		}
538
539		if (drv->data->get_version) {
540			config.supported_hw = &drv->versions;
541			config.supported_hw_count = 1;
542
543			if (pvs_name)
544				config.prop_name = pvs_name;
545		}
546
547		if (config.supported_hw) {
548			drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config);
549			if (drv->cpus[cpu].opp_token < 0) {
550				ret = drv->cpus[cpu].opp_token;
551				dev_err(cpu_dev, "Failed to set OPP config\n");
552				goto free_opp;
553			}
554		}
555
556		if (drv->data->pd_names) {
557			struct dev_pm_domain_attach_data attach_data = {
558				.pd_names = drv->data->pd_names,
559				.num_pd_names = drv->data->num_pd_names,
560				.pd_flags = PD_FLAG_DEV_LINK_ON |
561					    PD_FLAG_REQUIRED_OPP,
562			};
563
564			ret = dev_pm_domain_attach_list(cpu_dev, &attach_data,
565							&drv->cpus[cpu].pd_list);
566			if (ret < 0)
567				goto free_opp;
568		}
569	}
570
571	cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
572							  NULL, 0);
573	if (!IS_ERR(cpufreq_dt_pdev)) {
574		platform_set_drvdata(pdev, drv);
575		return 0;
576	}
577
578	ret = PTR_ERR(cpufreq_dt_pdev);
579	dev_err(cpu_dev, "Failed to register platform device\n");
580
581free_opp:
582	for_each_present_cpu(cpu) {
583		dev_pm_domain_detach_list(drv->cpus[cpu].pd_list);
584		dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
585	}
586	return ret;
587}
588
589static void qcom_cpufreq_remove(struct platform_device *pdev)
590{
591	struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
592	unsigned int cpu;
593
594	platform_device_unregister(cpufreq_dt_pdev);
595
596	for_each_present_cpu(cpu) {
597		dev_pm_domain_detach_list(drv->cpus[cpu].pd_list);
598		dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
599	}
600}
601
602static int qcom_cpufreq_suspend(struct device *dev)
603{
604	struct qcom_cpufreq_drv *drv = dev_get_drvdata(dev);
605	unsigned int cpu;
606
607	for_each_present_cpu(cpu)
608		qcom_cpufreq_suspend_pd_devs(drv, cpu);
609
610	return 0;
611}
612
613static DEFINE_SIMPLE_DEV_PM_OPS(qcom_cpufreq_pm_ops, qcom_cpufreq_suspend, NULL);
614
615static struct platform_driver qcom_cpufreq_driver = {
616	.probe = qcom_cpufreq_probe,
617	.remove = qcom_cpufreq_remove,
618	.driver = {
619		.name = "qcom-cpufreq-nvmem",
620		.pm = pm_sleep_ptr(&qcom_cpufreq_pm_ops),
621	},
622};
623
624static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_unused = {
625	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
626	{ .compatible = "qcom,msm8909", .data = &match_data_msm8909 },
627	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
628	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
629	{ .compatible = "qcom,ipq5332", .data = &match_data_kryo },
630	{ .compatible = "qcom,ipq5424", .data = &match_data_kryo },
631	{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
632	{ .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
633	{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
634	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
635	{ .compatible = "qcom,ipq9574", .data = &match_data_kryo },
636	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
637	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
638	{},
639};
640MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
641
642/*
643 * Since the driver depends on smem and nvmem drivers, which may
644 * return EPROBE_DEFER, all the real activity is done in the probe,
645 * which may be defered as well. The init here is only registering
646 * the driver and the platform device.
647 */
648static int __init qcom_cpufreq_init(void)
649{
650	struct device_node *np __free(device_node) = of_find_node_by_path("/");
651	const struct of_device_id *match;
652	int ret;
653
654	if (!np)
655		return -ENODEV;
656
657	match = of_match_node(qcom_cpufreq_match_list, np);
658	if (!match)
659		return -ENODEV;
660
661	ret = platform_driver_register(&qcom_cpufreq_driver);
662	if (unlikely(ret < 0))
663		return ret;
664
665	cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
666						     -1, match, sizeof(*match));
667	ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
668	if (0 == ret)
669		return 0;
670
671	platform_driver_unregister(&qcom_cpufreq_driver);
672	return ret;
673}
674module_init(qcom_cpufreq_init);
675
676static void __exit qcom_cpufreq_exit(void)
677{
678	platform_device_unregister(cpufreq_pdev);
679	platform_driver_unregister(&qcom_cpufreq_driver);
680}
681module_exit(qcom_cpufreq_exit);
682
683MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
684MODULE_LICENSE("GPL v2");