pmac64-cpufreq.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  4 *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
  5 *
  6 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
  7 * that is iMac G5 and latest single CPU desktop.
  8 */
  9
 10#undef DEBUG
 11
 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 13
 14#include <linux/module.h>
 15#include <linux/types.h>
 16#include <linux/errno.h>
 17#include <linux/kernel.h>
 18#include <linux/delay.h>
 19#include <linux/sched.h>
 20#include <linux/cpufreq.h>
 21#include <linux/init.h>
 22#include <linux/completion.h>
 23#include <linux/mutex.h>
 24#include <linux/of.h>
 25
 26#include <asm/machdep.h>
 27#include <asm/irq.h>
 28#include <asm/sections.h>
 29#include <asm/cputable.h>
 30#include <asm/time.h>
 31#include <asm/smu.h>
 32#include <asm/pmac_pfunc.h>
 33
 34#define DBG(fmt...) pr_debug(fmt)
 35
 36/* see 970FX user manual */
 37
 38#define SCOM_PCR 0x0aa001			/* PCR scom addr */
 39
 40#define PCR_HILO_SELECT		0x80000000U	/* 1 = PCR, 0 = PCRH */
 41#define PCR_SPEED_FULL		0x00000000U	/* 1:1 speed value */
 42#define PCR_SPEED_HALF		0x00020000U	/* 1:2 speed value */
 43#define PCR_SPEED_QUARTER	0x00040000U	/* 1:4 speed value */
 44#define PCR_SPEED_MASK		0x000e0000U	/* speed mask */
 45#define PCR_SPEED_SHIFT		17
 46#define PCR_FREQ_REQ_VALID	0x00010000U	/* freq request valid */
 47#define PCR_VOLT_REQ_VALID	0x00008000U	/* volt request valid */
 48#define PCR_TARGET_TIME_MASK	0x00006000U	/* target time */
 49#define PCR_STATLAT_MASK	0x00001f00U	/* STATLAT value */
 50#define PCR_SNOOPLAT_MASK	0x000000f0U	/* SNOOPLAT value */
 51#define PCR_SNOOPACC_MASK	0x0000000fU	/* SNOOPACC value */
 52
 53#define SCOM_PSR 0x408001			/* PSR scom addr */
 54/* warning: PSR is a 64 bits register */
 55#define PSR_CMD_RECEIVED	0x2000000000000000U   /* command received */
 56#define PSR_CMD_COMPLETED	0x1000000000000000U   /* command completed */
 57#define PSR_CUR_SPEED_MASK	0x0300000000000000U   /* current speed */
 58#define PSR_CUR_SPEED_SHIFT	(56)
 59
 60/*
 61 * The G5 only supports two frequencies (Quarter speed is not supported)
 62 */
 63#define CPUFREQ_HIGH                  0
 64#define CPUFREQ_LOW                   1
 65
 66static struct cpufreq_frequency_table g5_cpu_freqs[] = {
 67	{0, CPUFREQ_HIGH,	0},
 68	{0, CPUFREQ_LOW,	0},
 69	{0, 0,			CPUFREQ_TABLE_END},
 70};
 71
 72/* Power mode data is an array of the 32 bits PCR values to use for
 73 * the various frequencies, retrieved from the device-tree
 74 */
 75static int g5_pmode_cur;
 76
 77static void (*g5_switch_volt)(int speed_mode);
 78static int (*g5_switch_freq)(int speed_mode);
 79static int (*g5_query_freq)(void);
 80
 81static unsigned long transition_latency;
 82
 83#ifdef CONFIG_PMAC_SMU
 84
 85static const u32 *g5_pmode_data;
 86static int g5_pmode_max;
 87
 88static struct smu_sdbp_fvt *g5_fvt_table;	/* table of op. points */
 89static int g5_fvt_count;			/* number of op. points */
 90static int g5_fvt_cur;				/* current op. point */
 91
 92/*
 93 * SMU based voltage switching for Neo2 platforms
 94 */
 95
 96static void g5_smu_switch_volt(int speed_mode)
 97{
 98	struct smu_simple_cmd	cmd;
 99
100	DECLARE_COMPLETION_ONSTACK(comp);
101	smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
102			 &comp, 'V', 'S', 'L', 'E', 'W',
103			 0xff, g5_fvt_cur+1, speed_mode);
104	wait_for_completion(&comp);
105}
106
107/*
108 * Platform function based voltage/vdnap switching for Neo2
109 */
110
111static struct pmf_function *pfunc_set_vdnap0;
112static struct pmf_function *pfunc_vdnap0_complete;
113
114static void g5_vdnap_switch_volt(int speed_mode)
115{
116	struct pmf_args args;
117	u32 slew, done = 0;
118	unsigned long timeout;
119
120	slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
121	args.count = 1;
122	args.u[0].p = &slew;
123
124	pmf_call_one(pfunc_set_vdnap0, &args);
125
126	/* It's an irq GPIO so we should be able to just block here,
127	 * I'll do that later after I've properly tested the IRQ code for
128	 * platform functions
129	 */
130	timeout = jiffies + HZ/10;
131	while(!time_after(jiffies, timeout)) {
132		args.count = 1;
133		args.u[0].p = &done;
134		pmf_call_one(pfunc_vdnap0_complete, &args);
135		if (done)
136			break;
137		usleep_range(1000, 1000);
138	}
139	if (done == 0)
140		pr_warn("Timeout in clock slewing !\n");
141}
142
143
144/*
145 * SCOM based frequency switching for 970FX rev3
146 */
147static int g5_scom_switch_freq(int speed_mode)
148{
149	unsigned long flags;
150	int to;
151
152	/* If frequency is going up, first ramp up the voltage */
153	if (speed_mode < g5_pmode_cur)
154		g5_switch_volt(speed_mode);
155
156	local_irq_save(flags);
157
158	/* Clear PCR high */
159	scom970_write(SCOM_PCR, 0);
160	/* Clear PCR low */
161       	scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
162	/* Set PCR low */
163	scom970_write(SCOM_PCR, PCR_HILO_SELECT |
164		      g5_pmode_data[speed_mode]);
165
166	/* Wait for completion */
167	for (to = 0; to < 10; to++) {
168		unsigned long psr = scom970_read(SCOM_PSR);
169
170		if ((psr & PSR_CMD_RECEIVED) == 0 &&
171		    (((psr >> PSR_CUR_SPEED_SHIFT) ^
172		      (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
173		    == 0)
174			break;
175		if (psr & PSR_CMD_COMPLETED)
176			break;
177		udelay(100);
178	}
179
180	local_irq_restore(flags);
181
182	/* If frequency is going down, last ramp the voltage */
183	if (speed_mode > g5_pmode_cur)
184		g5_switch_volt(speed_mode);
185
186	g5_pmode_cur = speed_mode;
187	ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
188
189	return 0;
190}
191
192static int g5_scom_query_freq(void)
193{
194	unsigned long psr = scom970_read(SCOM_PSR);
195	int i;
196
197	for (i = 0; i <= g5_pmode_max; i++)
198		if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
199		      (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
200			break;
201	return i;
202}
203
204/*
205 * Fake voltage switching for platforms with missing support
206 */
207
208static void g5_dummy_switch_volt(int speed_mode)
209{
210}
211
212#endif /* CONFIG_PMAC_SMU */
213
214/*
215 * Platform function based voltage switching for PowerMac7,2 & 7,3
216 */
217
218static struct pmf_function *pfunc_cpu0_volt_high;
219static struct pmf_function *pfunc_cpu0_volt_low;
220static struct pmf_function *pfunc_cpu1_volt_high;
221static struct pmf_function *pfunc_cpu1_volt_low;
222
223static void g5_pfunc_switch_volt(int speed_mode)
224{
225	if (speed_mode == CPUFREQ_HIGH) {
226		if (pfunc_cpu0_volt_high)
227			pmf_call_one(pfunc_cpu0_volt_high, NULL);
228		if (pfunc_cpu1_volt_high)
229			pmf_call_one(pfunc_cpu1_volt_high, NULL);
230	} else {
231		if (pfunc_cpu0_volt_low)
232			pmf_call_one(pfunc_cpu0_volt_low, NULL);
233		if (pfunc_cpu1_volt_low)
234			pmf_call_one(pfunc_cpu1_volt_low, NULL);
235	}
236	usleep_range(10000, 10000); /* should be faster , to fix */
237}
238
239/*
240 * Platform function based frequency switching for PowerMac7,2 & 7,3
241 */
242
243static struct pmf_function *pfunc_cpu_setfreq_high;
244static struct pmf_function *pfunc_cpu_setfreq_low;
245static struct pmf_function *pfunc_cpu_getfreq;
246static struct pmf_function *pfunc_slewing_done;
247
248static int g5_pfunc_switch_freq(int speed_mode)
249{
250	struct pmf_args args;
251	u32 done = 0;
252	unsigned long timeout;
253	int rc;
254
255	DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
256
257	/* If frequency is going up, first ramp up the voltage */
258	if (speed_mode < g5_pmode_cur)
259		g5_switch_volt(speed_mode);
260
261	/* Do it */
262	if (speed_mode == CPUFREQ_HIGH)
263		rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
264	else
265		rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
266
267	if (rc)
268		pr_warn("pfunc switch error %d\n", rc);
269
270	/* It's an irq GPIO so we should be able to just block here,
271	 * I'll do that later after I've properly tested the IRQ code for
272	 * platform functions
273	 */
274	timeout = jiffies + HZ/10;
275	while(!time_after(jiffies, timeout)) {
276		args.count = 1;
277		args.u[0].p = &done;
278		pmf_call_one(pfunc_slewing_done, &args);
279		if (done)
280			break;
281		usleep_range(500, 500);
282	}
283	if (done == 0)
284		pr_warn("Timeout in clock slewing !\n");
285
286	/* If frequency is going down, last ramp the voltage */
287	if (speed_mode > g5_pmode_cur)
288		g5_switch_volt(speed_mode);
289
290	g5_pmode_cur = speed_mode;
291	ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
292
293	return 0;
294}
295
296static int g5_pfunc_query_freq(void)
297{
298	struct pmf_args args;
299	u32 val = 0;
300
301	args.count = 1;
302	args.u[0].p = &val;
303	pmf_call_one(pfunc_cpu_getfreq, &args);
304	return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
305}
306
307
308/*
309 * Common interface to the cpufreq core
310 */
311
312static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
313{
314	return g5_switch_freq(index);
315}
316
317static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
318{
319	return g5_cpu_freqs[g5_pmode_cur].frequency;
320}
321
322static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
323{
324	cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
325	return 0;
326}
327
328static struct cpufreq_driver g5_cpufreq_driver = {
329	.name		= "powermac",
330	.flags		= CPUFREQ_CONST_LOOPS,
331	.init		= g5_cpufreq_cpu_init,
332	.verify		= cpufreq_generic_frequency_table_verify,
333	.target_index	= g5_cpufreq_target,
334	.get		= g5_cpufreq_get_speed,
335};
336
337
338#ifdef CONFIG_PMAC_SMU
339
340static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
341{
342	unsigned int psize, ssize;
343	unsigned long max_freq;
344	char *freq_method, *volt_method;
345	const u32 *valp;
346	u32 pvr_hi;
347	int use_volts_vdnap = 0;
348	int use_volts_smu = 0;
349	int rc = -ENODEV;
350
351	/* Check supported platforms */
352	if (of_machine_is_compatible("PowerMac8,1") ||
353	    of_machine_is_compatible("PowerMac8,2") ||
354	    of_machine_is_compatible("PowerMac9,1") ||
355	    of_machine_is_compatible("PowerMac12,1"))
356		use_volts_smu = 1;
357	else if (of_machine_is_compatible("PowerMac11,2"))
358		use_volts_vdnap = 1;
359	else
360		return -ENODEV;
361
362	/* Check 970FX for now */
363	valp = of_get_property(cpunode, "cpu-version", NULL);
364	if (!valp) {
365		DBG("No cpu-version property !\n");
366		goto bail_noprops;
367	}
368	pvr_hi = (*valp) >> 16;
369	if (pvr_hi != 0x3c && pvr_hi != 0x44) {
370		pr_err("Unsupported CPU version\n");
371		goto bail_noprops;
372	}
373
374	/* Look for the powertune data in the device-tree */
375	g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
376	if (!g5_pmode_data) {
377		DBG("No power-mode-data !\n");
378		goto bail_noprops;
379	}
380	g5_pmode_max = psize / sizeof(u32) - 1;
381
382	if (use_volts_smu) {
383		const struct smu_sdbp_header *shdr;
384
385		/* Look for the FVT table */
386		shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
387		if (!shdr)
388			goto bail_noprops;
389		g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
390		ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
391		g5_fvt_count = ssize / sizeof(*g5_fvt_table);
392		g5_fvt_cur = 0;
393
394		/* Sanity checking */
395		if (g5_fvt_count < 1 || g5_pmode_max < 1)
396			goto bail_noprops;
397
398		g5_switch_volt = g5_smu_switch_volt;
399		volt_method = "SMU";
400	} else if (use_volts_vdnap) {
401		struct device_node *root;
402
403		root = of_find_node_by_path("/");
404		if (root == NULL) {
405			pr_err("Can't find root of device tree\n");
406			goto bail_noprops;
407		}
408		pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
409		pfunc_vdnap0_complete =
410			pmf_find_function(root, "slewing-done");
411		of_node_put(root);
412		if (pfunc_set_vdnap0 == NULL ||
413		    pfunc_vdnap0_complete == NULL) {
414			pr_err("Can't find required platform function\n");
415			goto bail_noprops;
416		}
417
418		g5_switch_volt = g5_vdnap_switch_volt;
419		volt_method = "GPIO";
420	} else {
421		g5_switch_volt = g5_dummy_switch_volt;
422		volt_method = "none";
423	}
424
425	/*
426	 * From what I see, clock-frequency is always the maximal frequency.
427	 * The current driver can not slew sysclk yet, so we really only deal
428	 * with powertune steps for now. We also only implement full freq and
429	 * half freq in this version. So far, I haven't yet seen a machine
430	 * supporting anything else.
431	 */
432	valp = of_get_property(cpunode, "clock-frequency", NULL);
433	if (!valp)
434		return -ENODEV;
435	max_freq = (*valp)/1000;
436	g5_cpu_freqs[0].frequency = max_freq;
437	g5_cpu_freqs[1].frequency = max_freq/2;
438
439	/* Set callbacks */
440	transition_latency = 12000;
441	g5_switch_freq = g5_scom_switch_freq;
442	g5_query_freq = g5_scom_query_freq;
443	freq_method = "SCOM";
444
445	/* Force apply current frequency to make sure everything is in
446	 * sync (voltage is right for example). Firmware may leave us with
447	 * a strange setting ...
448	 */
449	g5_switch_volt(CPUFREQ_HIGH);
450	msleep(10);
451	g5_pmode_cur = -1;
452	g5_switch_freq(g5_query_freq());
453
454	pr_info("Registering G5 CPU frequency driver\n");
455	pr_info("Frequency method: %s, Voltage method: %s\n",
456		freq_method, volt_method);
457	pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
458		g5_cpu_freqs[1].frequency/1000,
459		g5_cpu_freqs[0].frequency/1000,
460		g5_cpu_freqs[g5_pmode_cur].frequency/1000);
461
462	rc = cpufreq_register_driver(&g5_cpufreq_driver);
463
464	/* We keep the CPU node on hold... hopefully, Apple G5 don't have
465	 * hotplug CPU with a dynamic device-tree ...
466	 */
467	return rc;
468
469 bail_noprops:
470	of_node_put(cpunode);
471
472	return rc;
473}
474
475#endif /* CONFIG_PMAC_SMU */
476
477
478static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
479{
480	struct device_node *cpuid = NULL, *hwclock = NULL;
481	const u8 *eeprom = NULL;
482	const u32 *valp;
483	u64 max_freq, min_freq, ih, il;
484	int has_volt = 1, rc = 0;
485
486	DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
487	    " RackMac3,1...\n");
488
489	/* Lookup the cpuid eeprom node */
490        cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
491	if (cpuid != NULL)
492		eeprom = of_get_property(cpuid, "cpuid", NULL);
493	if (eeprom == NULL) {
494		pr_err("Can't find cpuid EEPROM !\n");
495		rc = -ENODEV;
496		goto bail;
497	}
498
499	/* Lookup the i2c hwclock */
500	for_each_node_by_name(hwclock, "i2c-hwclock") {
501		const char *loc = of_get_property(hwclock,
502				"hwctrl-location", NULL);
503		if (loc == NULL)
504			continue;
505		if (strcmp(loc, "CPU CLOCK"))
506			continue;
507		if (!of_property_present(hwclock, "platform-get-frequency"))
508			continue;
509		break;
510	}
511	if (hwclock == NULL) {
512		pr_err("Can't find i2c clock chip !\n");
513		rc = -ENODEV;
514		goto bail;
515	}
516
517	DBG("cpufreq: i2c clock chip found: %pOF\n", hwclock);
518
519	/* Now get all the platform functions */
520	pfunc_cpu_getfreq =
521		pmf_find_function(hwclock, "get-frequency");
522	pfunc_cpu_setfreq_high =
523		pmf_find_function(hwclock, "set-frequency-high");
524	pfunc_cpu_setfreq_low =
525		pmf_find_function(hwclock, "set-frequency-low");
526	pfunc_slewing_done =
527		pmf_find_function(hwclock, "slewing-done");
528	pfunc_cpu0_volt_high =
529		pmf_find_function(hwclock, "set-voltage-high-0");
530	pfunc_cpu0_volt_low =
531		pmf_find_function(hwclock, "set-voltage-low-0");
532	pfunc_cpu1_volt_high =
533		pmf_find_function(hwclock, "set-voltage-high-1");
534	pfunc_cpu1_volt_low =
535		pmf_find_function(hwclock, "set-voltage-low-1");
536
537	/* Check we have minimum requirements */
538	if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
539	    pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
540		pr_err("Can't find platform functions !\n");
541		rc = -ENODEV;
542		goto bail;
543	}
544
545	/* Check that we have complete sets */
546	if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
547		pmf_put_function(pfunc_cpu0_volt_high);
548		pmf_put_function(pfunc_cpu0_volt_low);
549		pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
550		has_volt = 0;
551	}
552	if (!has_volt ||
553	    pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
554		pmf_put_function(pfunc_cpu1_volt_high);
555		pmf_put_function(pfunc_cpu1_volt_low);
556		pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
557	}
558
559	/* Note: The device tree also contains a "platform-set-values"
560	 * function for which I haven't quite figured out the usage. It
561	 * might have to be called on init and/or wakeup, I'm not too sure
562	 * but things seem to work fine without it so far ...
563	 */
564
565	/* Get max frequency from device-tree */
566	valp = of_get_property(cpunode, "clock-frequency", NULL);
567	if (!valp) {
568		pr_err("Can't find CPU frequency !\n");
569		rc = -ENODEV;
570		goto bail;
571	}
572
573	max_freq = (*valp)/1000;
574
575	/* Now calculate reduced frequency by using the cpuid input freq
576	 * ratio. This requires 64 bits math unless we are willing to lose
577	 * some precision
578	 */
579	ih = *((u32 *)(eeprom + 0x10));
580	il = *((u32 *)(eeprom + 0x20));
581
582	/* Check for machines with no useful settings */
583	if (il == ih) {
584		pr_warn("No low frequency mode available on this model !\n");
585		rc = -ENODEV;
586		goto bail;
587	}
588
589	min_freq = 0;
590	if (ih != 0 && il != 0)
591		min_freq = (max_freq * il) / ih;
592
593	/* Sanity check */
594	if (min_freq >= max_freq || min_freq < 1000) {
595		pr_err("Can't calculate low frequency !\n");
596		rc = -ENXIO;
597		goto bail;
598	}
599	g5_cpu_freqs[0].frequency = max_freq;
600	g5_cpu_freqs[1].frequency = min_freq;
601
602	/* Based on a measurement on Xserve G5, rounded up. */
603	transition_latency = 10 * NSEC_PER_MSEC;
604
605	/* Set callbacks */
606	g5_switch_volt = g5_pfunc_switch_volt;
607	g5_switch_freq = g5_pfunc_switch_freq;
608	g5_query_freq = g5_pfunc_query_freq;
609
610	/* Force apply current frequency to make sure everything is in
611	 * sync (voltage is right for example). Firmware may leave us with
612	 * a strange setting ...
613	 */
614	g5_switch_volt(CPUFREQ_HIGH);
615	msleep(10);
616	g5_pmode_cur = -1;
617	g5_switch_freq(g5_query_freq());
618
619	pr_info("Registering G5 CPU frequency driver\n");
620	pr_info("Frequency method: i2c/pfunc, Voltage method: %s\n",
621		has_volt ? "i2c/pfunc" : "none");
622	pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
623		g5_cpu_freqs[1].frequency/1000,
624		g5_cpu_freqs[0].frequency/1000,
625		g5_cpu_freqs[g5_pmode_cur].frequency/1000);
626
627	rc = cpufreq_register_driver(&g5_cpufreq_driver);
628 bail:
629	if (rc != 0) {
630		pmf_put_function(pfunc_cpu_getfreq);
631		pmf_put_function(pfunc_cpu_setfreq_high);
632		pmf_put_function(pfunc_cpu_setfreq_low);
633		pmf_put_function(pfunc_slewing_done);
634		pmf_put_function(pfunc_cpu0_volt_high);
635		pmf_put_function(pfunc_cpu0_volt_low);
636		pmf_put_function(pfunc_cpu1_volt_high);
637		pmf_put_function(pfunc_cpu1_volt_low);
638	}
639	of_node_put(hwclock);
640	of_node_put(cpuid);
641	of_node_put(cpunode);
642
643	return rc;
644}
645
646static int __init g5_cpufreq_init(void)
647{
648	struct device_node *cpunode;
649	int rc = 0;
650
651	/* Get first CPU node */
652	cpunode = of_cpu_device_node_get(0);
653	if (cpunode == NULL) {
654		pr_err("Can't find any CPU node\n");
655		return -ENODEV;
656	}
657
658	if (of_machine_is_compatible("PowerMac7,2") ||
659	    of_machine_is_compatible("PowerMac7,3") ||
660	    of_machine_is_compatible("RackMac3,1"))
661		rc = g5_pm72_cpufreq_init(cpunode);
662#ifdef CONFIG_PMAC_SMU
663	else
664		rc = g5_neo2_cpufreq_init(cpunode);
665#endif /* CONFIG_PMAC_SMU */
666
667	return rc;
668}
669
670module_init(g5_cpufreq_init);
671
672
673MODULE_DESCRIPTION("cpufreq driver for SMU & 970FX based G5 Macs");
674MODULE_LICENSE("GPL");