ti-eqep.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2019 David Lechner <david@lechnology.com>
  4 *
  5 * Counter driver for Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP)
  6 */
  7
  8#include <linux/bitops.h>
  9#include <linux/clk.h>
 10#include <linux/counter.h>
 11#include <linux/interrupt.h>
 12#include <linux/kernel.h>
 13#include <linux/mod_devicetable.h>
 14#include <linux/module.h>
 15#include <linux/platform_device.h>
 16#include <linux/pm_runtime.h>
 17#include <linux/regmap.h>
 18#include <linux/types.h>
 19
 20/* 32-bit registers */
 21#define QPOSCNT		0x0
 22#define QPOSINIT	0x4
 23#define QPOSMAX		0x8
 24#define QPOSCMP		0xc
 25#define QPOSILAT	0x10
 26#define QPOSSLAT	0x14
 27#define QPOSLAT		0x18
 28#define QUTMR		0x1c
 29#define QUPRD		0x20
 30
 31/* 16-bit registers */
 32#define QWDTMR		0x0	/* 0x24 */
 33#define QWDPRD		0x2	/* 0x26 */
 34#define QDECCTL		0x4	/* 0x28 */
 35#define QEPCTL		0x6	/* 0x2a */
 36#define QCAPCTL		0x8	/* 0x2c */
 37#define QPOSCTL		0xa	/* 0x2e */
 38#define QEINT		0xc	/* 0x30 */
 39#define QFLG		0xe	/* 0x32 */
 40#define QCLR		0x10	/* 0x34 */
 41#define QFRC		0x12	/* 0x36 */
 42#define QEPSTS		0x14	/* 0x38 */
 43#define QCTMR		0x16	/* 0x3a */
 44#define QCPRD		0x18	/* 0x3c */
 45#define QCTMRLAT	0x1a	/* 0x3e */
 46#define QCPRDLAT	0x1c	/* 0x40 */
 47
 48#define QDECCTL_QSRC_SHIFT	14
 49#define QDECCTL_QSRC		GENMASK(15, 14)
 50#define QDECCTL_SOEN		BIT(13)
 51#define QDECCTL_SPSEL		BIT(12)
 52#define QDECCTL_XCR		BIT(11)
 53#define QDECCTL_SWAP		BIT(10)
 54#define QDECCTL_IGATE		BIT(9)
 55#define QDECCTL_QAP		BIT(8)
 56#define QDECCTL_QBP		BIT(7)
 57#define QDECCTL_QIP		BIT(6)
 58#define QDECCTL_QSP		BIT(5)
 59
 60#define QEPCTL_FREE_SOFT	GENMASK(15, 14)
 61#define QEPCTL_PCRM		GENMASK(13, 12)
 62#define QEPCTL_SEI		GENMASK(11, 10)
 63#define QEPCTL_IEI		GENMASK(9, 8)
 64#define QEPCTL_SWI		BIT(7)
 65#define QEPCTL_SEL		BIT(6)
 66#define QEPCTL_IEL		GENMASK(5, 4)
 67#define QEPCTL_PHEN		BIT(3)
 68#define QEPCTL_QCLM		BIT(2)
 69#define QEPCTL_UTE		BIT(1)
 70#define QEPCTL_WDE		BIT(0)
 71
 72#define QEINT_UTO		BIT(11)
 73#define QEINT_IEL		BIT(10)
 74#define QEINT_SEL		BIT(9)
 75#define QEINT_PCM		BIT(8)
 76#define QEINT_PCR		BIT(7)
 77#define QEINT_PCO		BIT(6)
 78#define QEINT_PCU		BIT(5)
 79#define QEINT_WTO		BIT(4)
 80#define QEINT_QDC		BIT(3)
 81#define QEINT_PHE		BIT(2)
 82#define QEINT_PCE		BIT(1)
 83
 84#define QFLG_UTO		BIT(11)
 85#define QFLG_IEL		BIT(10)
 86#define QFLG_SEL		BIT(9)
 87#define QFLG_PCM		BIT(8)
 88#define QFLG_PCR		BIT(7)
 89#define QFLG_PCO		BIT(6)
 90#define QFLG_PCU		BIT(5)
 91#define QFLG_WTO		BIT(4)
 92#define QFLG_QDC		BIT(3)
 93#define QFLG_PHE		BIT(2)
 94#define QFLG_PCE		BIT(1)
 95#define QFLG_INT		BIT(0)
 96
 97#define QCLR_UTO		BIT(11)
 98#define QCLR_IEL		BIT(10)
 99#define QCLR_SEL		BIT(9)
100#define QCLR_PCM		BIT(8)
101#define QCLR_PCR		BIT(7)
102#define QCLR_PCO		BIT(6)
103#define QCLR_PCU		BIT(5)
104#define QCLR_WTO		BIT(4)
105#define QCLR_QDC		BIT(3)
106#define QCLR_PHE		BIT(2)
107#define QCLR_PCE		BIT(1)
108#define QCLR_INT		BIT(0)
109
110#define QEPSTS_UPEVNT		BIT(7)
111#define QEPSTS_FDF		BIT(6)
112#define QEPSTS_QDF		BIT(5)
113#define QEPSTS_QDLF		BIT(4)
114#define QEPSTS_COEF		BIT(3)
115#define QEPSTS_CDEF		BIT(2)
116#define QEPSTS_FIMF		BIT(1)
117#define QEPSTS_PCEF		BIT(0)
118
119/* EQEP Inputs */
120enum {
121	TI_EQEP_SIGNAL_QEPA,	/* QEPA/XCLK */
122	TI_EQEP_SIGNAL_QEPB,	/* QEPB/XDIR */
123};
124
125/* Position Counter Input Modes */
126enum ti_eqep_count_func {
127	TI_EQEP_COUNT_FUNC_QUAD_COUNT,
128	TI_EQEP_COUNT_FUNC_DIR_COUNT,
129	TI_EQEP_COUNT_FUNC_UP_COUNT,
130	TI_EQEP_COUNT_FUNC_DOWN_COUNT,
131};
132
133struct ti_eqep_cnt {
134	struct regmap *regmap32;
135	struct regmap *regmap16;
136};
137
138static int ti_eqep_count_read(struct counter_device *counter,
139			      struct counter_count *count, u64 *val)
140{
141	struct ti_eqep_cnt *priv = counter_priv(counter);
142	u32 cnt;
143
144	regmap_read(priv->regmap32, QPOSCNT, &cnt);
145	*val = cnt;
146
147	return 0;
148}
149
150static int ti_eqep_count_write(struct counter_device *counter,
151			       struct counter_count *count, u64 val)
152{
153	struct ti_eqep_cnt *priv = counter_priv(counter);
154	u32 max;
155
156	regmap_read(priv->regmap32, QPOSMAX, &max);
157	if (val > max)
158		return -EINVAL;
159
160	return regmap_write(priv->regmap32, QPOSCNT, val);
161}
162
163static int ti_eqep_function_read(struct counter_device *counter,
164				 struct counter_count *count,
165				 enum counter_function *function)
166{
167	struct ti_eqep_cnt *priv = counter_priv(counter);
168	u32 qdecctl;
169
170	regmap_read(priv->regmap16, QDECCTL, &qdecctl);
171
172	switch ((qdecctl & QDECCTL_QSRC) >> QDECCTL_QSRC_SHIFT) {
173	case TI_EQEP_COUNT_FUNC_QUAD_COUNT:
174		*function = COUNTER_FUNCTION_QUADRATURE_X4;
175		break;
176	case TI_EQEP_COUNT_FUNC_DIR_COUNT:
177		*function = COUNTER_FUNCTION_PULSE_DIRECTION;
178		break;
179	case TI_EQEP_COUNT_FUNC_UP_COUNT:
180		*function = COUNTER_FUNCTION_INCREASE;
181		break;
182	case TI_EQEP_COUNT_FUNC_DOWN_COUNT:
183		*function = COUNTER_FUNCTION_DECREASE;
184		break;
185	}
186
187	return 0;
188}
189
190static int ti_eqep_function_write(struct counter_device *counter,
191				  struct counter_count *count,
192				  enum counter_function function)
193{
194	struct ti_eqep_cnt *priv = counter_priv(counter);
195	enum ti_eqep_count_func qsrc;
196
197	switch (function) {
198	case COUNTER_FUNCTION_QUADRATURE_X4:
199		qsrc = TI_EQEP_COUNT_FUNC_QUAD_COUNT;
200		break;
201	case COUNTER_FUNCTION_PULSE_DIRECTION:
202		qsrc = TI_EQEP_COUNT_FUNC_DIR_COUNT;
203		break;
204	case COUNTER_FUNCTION_INCREASE:
205		qsrc = TI_EQEP_COUNT_FUNC_UP_COUNT;
206		break;
207	case COUNTER_FUNCTION_DECREASE:
208		qsrc = TI_EQEP_COUNT_FUNC_DOWN_COUNT;
209		break;
210	default:
211		/* should never reach this path */
212		return -EINVAL;
213	}
214
215	return regmap_write_bits(priv->regmap16, QDECCTL, QDECCTL_QSRC,
216				 qsrc << QDECCTL_QSRC_SHIFT);
217}
218
219static int ti_eqep_action_read(struct counter_device *counter,
220			       struct counter_count *count,
221			       struct counter_synapse *synapse,
222			       enum counter_synapse_action *action)
223{
224	struct ti_eqep_cnt *priv = counter_priv(counter);
225	enum counter_function function;
226	u32 qdecctl;
227	int err;
228
229	err = ti_eqep_function_read(counter, count, &function);
230	if (err)
231		return err;
232
233	switch (function) {
234	case COUNTER_FUNCTION_QUADRATURE_X4:
235		/* In quadrature mode, the rising and falling edge of both
236		 * QEPA and QEPB trigger QCLK.
237		 */
238		*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
239		return 0;
240	case COUNTER_FUNCTION_PULSE_DIRECTION:
241		/* In direction-count mode only rising edge of QEPA is counted
242		 * and QEPB gives direction.
243		 */
244		switch (synapse->signal->id) {
245		case TI_EQEP_SIGNAL_QEPA:
246			*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
247			return 0;
248		case TI_EQEP_SIGNAL_QEPB:
249			*action = COUNTER_SYNAPSE_ACTION_NONE;
250			return 0;
251		default:
252			/* should never reach this path */
253			return -EINVAL;
254		}
255	case COUNTER_FUNCTION_INCREASE:
256	case COUNTER_FUNCTION_DECREASE:
257		/* In up/down-count modes only QEPA is counted and QEPB is not
258		 * used.
259		 */
260		switch (synapse->signal->id) {
261		case TI_EQEP_SIGNAL_QEPA:
262			err = regmap_read(priv->regmap16, QDECCTL, &qdecctl);
263			if (err)
264				return err;
265
266			if (qdecctl & QDECCTL_XCR)
267				*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
268			else
269				*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
270			return 0;
271		case TI_EQEP_SIGNAL_QEPB:
272			*action = COUNTER_SYNAPSE_ACTION_NONE;
273			return 0;
274		default:
275			/* should never reach this path */
276			return -EINVAL;
277		}
278	default:
279		/* should never reach this path */
280		return -EINVAL;
281	}
282}
283
284static int ti_eqep_events_configure(struct counter_device *counter)
285{
286	struct ti_eqep_cnt *priv = counter_priv(counter);
287	struct counter_event_node *event_node;
288	u32 qeint = 0;
289
290	list_for_each_entry(event_node, &counter->events_list, l) {
291		switch (event_node->event) {
292		case COUNTER_EVENT_OVERFLOW:
293			qeint |= QEINT_PCO;
294			break;
295		case COUNTER_EVENT_UNDERFLOW:
296			qeint |= QEINT_PCU;
297			break;
298		case COUNTER_EVENT_DIRECTION_CHANGE:
299			qeint |= QEINT_QDC;
300			break;
301		}
302	}
303
304	return regmap_write(priv->regmap16, QEINT, qeint);
305}
306
307static int ti_eqep_watch_validate(struct counter_device *counter,
308				  const struct counter_watch *watch)
309{
310	switch (watch->event) {
311	case COUNTER_EVENT_OVERFLOW:
312	case COUNTER_EVENT_UNDERFLOW:
313	case COUNTER_EVENT_DIRECTION_CHANGE:
314		if (watch->channel != 0)
315			return -EINVAL;
316
317		return 0;
318	default:
319		return -EINVAL;
320	}
321}
322
323static const struct counter_ops ti_eqep_counter_ops = {
324	.count_read	= ti_eqep_count_read,
325	.count_write	= ti_eqep_count_write,
326	.function_read	= ti_eqep_function_read,
327	.function_write	= ti_eqep_function_write,
328	.action_read	= ti_eqep_action_read,
329	.events_configure = ti_eqep_events_configure,
330	.watch_validate	= ti_eqep_watch_validate,
331};
332
333static int ti_eqep_position_ceiling_read(struct counter_device *counter,
334					 struct counter_count *count,
335					 u64 *ceiling)
336{
337	struct ti_eqep_cnt *priv = counter_priv(counter);
338	u32 qposmax;
339
340	regmap_read(priv->regmap32, QPOSMAX, &qposmax);
341
342	*ceiling = qposmax;
343
344	return 0;
345}
346
347static int ti_eqep_position_ceiling_write(struct counter_device *counter,
348					  struct counter_count *count,
349					  u64 ceiling)
350{
351	struct ti_eqep_cnt *priv = counter_priv(counter);
352
353	if (ceiling != (u32)ceiling)
354		return -ERANGE;
355
356	regmap_write(priv->regmap32, QPOSMAX, ceiling);
357
358	return 0;
359}
360
361static int ti_eqep_position_enable_read(struct counter_device *counter,
362					struct counter_count *count, u8 *enable)
363{
364	struct ti_eqep_cnt *priv = counter_priv(counter);
365	u32 qepctl;
366
367	regmap_read(priv->regmap16, QEPCTL, &qepctl);
368
369	*enable = !!(qepctl & QEPCTL_PHEN);
370
371	return 0;
372}
373
374static int ti_eqep_position_enable_write(struct counter_device *counter,
375					 struct counter_count *count, u8 enable)
376{
377	struct ti_eqep_cnt *priv = counter_priv(counter);
378
379	regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, enable ? -1 : 0);
380
381	return 0;
382}
383
384static int ti_eqep_direction_read(struct counter_device *counter,
385				  struct counter_count *count,
386				  enum counter_count_direction *direction)
387{
388	struct ti_eqep_cnt *priv = counter_priv(counter);
389	u32 qepsts;
390
391	regmap_read(priv->regmap16, QEPSTS, &qepsts);
392
393	*direction = (qepsts & QEPSTS_QDF) ? COUNTER_COUNT_DIRECTION_FORWARD
394					   : COUNTER_COUNT_DIRECTION_BACKWARD;
395
396	return 0;
397}
398
399static struct counter_comp ti_eqep_position_ext[] = {
400	COUNTER_COMP_CEILING(ti_eqep_position_ceiling_read,
401			     ti_eqep_position_ceiling_write),
402	COUNTER_COMP_ENABLE(ti_eqep_position_enable_read,
403			    ti_eqep_position_enable_write),
404	COUNTER_COMP_DIRECTION(ti_eqep_direction_read),
405};
406
407static struct counter_signal ti_eqep_signals[] = {
408	[TI_EQEP_SIGNAL_QEPA] = {
409		.id = TI_EQEP_SIGNAL_QEPA,
410		.name = "QEPA"
411	},
412	[TI_EQEP_SIGNAL_QEPB] = {
413		.id = TI_EQEP_SIGNAL_QEPB,
414		.name = "QEPB"
415	},
416};
417
418static const enum counter_function ti_eqep_position_functions[] = {
419	COUNTER_FUNCTION_QUADRATURE_X4,
420	COUNTER_FUNCTION_PULSE_DIRECTION,
421	COUNTER_FUNCTION_INCREASE,
422	COUNTER_FUNCTION_DECREASE,
423};
424
425static const enum counter_synapse_action ti_eqep_position_synapse_actions[] = {
426	COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
427	COUNTER_SYNAPSE_ACTION_RISING_EDGE,
428	COUNTER_SYNAPSE_ACTION_NONE,
429};
430
431static struct counter_synapse ti_eqep_position_synapses[] = {
432	{
433		.actions_list	= ti_eqep_position_synapse_actions,
434		.num_actions	= ARRAY_SIZE(ti_eqep_position_synapse_actions),
435		.signal		= &ti_eqep_signals[TI_EQEP_SIGNAL_QEPA],
436	},
437	{
438		.actions_list	= ti_eqep_position_synapse_actions,
439		.num_actions	= ARRAY_SIZE(ti_eqep_position_synapse_actions),
440		.signal		= &ti_eqep_signals[TI_EQEP_SIGNAL_QEPB],
441	},
442};
443
444static struct counter_count ti_eqep_counts[] = {
445	{
446		.id		= 0,
447		.name		= "QPOSCNT",
448		.functions_list	= ti_eqep_position_functions,
449		.num_functions	= ARRAY_SIZE(ti_eqep_position_functions),
450		.synapses	= ti_eqep_position_synapses,
451		.num_synapses	= ARRAY_SIZE(ti_eqep_position_synapses),
452		.ext		= ti_eqep_position_ext,
453		.num_ext	= ARRAY_SIZE(ti_eqep_position_ext),
454	},
455};
456
457static irqreturn_t ti_eqep_irq_handler(int irq, void *dev_id)
458{
459	struct counter_device *counter = dev_id;
460	struct ti_eqep_cnt *priv = counter_priv(counter);
461	u32 qflg;
462
463	regmap_read(priv->regmap16, QFLG, &qflg);
464
465	if (qflg & QFLG_PCO)
466		counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0);
467
468	if (qflg & QFLG_PCU)
469		counter_push_event(counter, COUNTER_EVENT_UNDERFLOW, 0);
470
471	if (qflg & QFLG_QDC)
472		counter_push_event(counter, COUNTER_EVENT_DIRECTION_CHANGE, 0);
473
474	regmap_write(priv->regmap16, QCLR, qflg);
475
476	return IRQ_HANDLED;
477}
478
479static const struct regmap_config ti_eqep_regmap32_config = {
480	.name = "32-bit",
481	.reg_bits = 32,
482	.val_bits = 32,
483	.reg_stride = 4,
484	.max_register = QUPRD,
485};
486
487static const struct regmap_config ti_eqep_regmap16_config = {
488	.name = "16-bit",
489	.reg_bits = 16,
490	.val_bits = 16,
491	.reg_stride = 2,
492	.max_register = QCPRDLAT,
493};
494
495static int ti_eqep_probe(struct platform_device *pdev)
496{
497	struct device *dev = &pdev->dev;
498	struct counter_device *counter;
499	struct ti_eqep_cnt *priv;
500	void __iomem *base;
501	struct clk *clk;
502	int err, irq;
503
504	counter = devm_counter_alloc(dev, sizeof(*priv));
505	if (!counter)
506		return -ENOMEM;
507	priv = counter_priv(counter);
508
509	base = devm_platform_ioremap_resource(pdev, 0);
510	if (IS_ERR(base))
511		return PTR_ERR(base);
512
513	priv->regmap32 = devm_regmap_init_mmio(dev, base,
514					       &ti_eqep_regmap32_config);
515	if (IS_ERR(priv->regmap32))
516		return PTR_ERR(priv->regmap32);
517
518	priv->regmap16 = devm_regmap_init_mmio(dev, base + 0x24,
519					       &ti_eqep_regmap16_config);
520	if (IS_ERR(priv->regmap16))
521		return PTR_ERR(priv->regmap16);
522
523	irq = platform_get_irq(pdev, 0);
524	if (irq < 0)
525		return irq;
526
527	err = devm_request_threaded_irq(dev, irq, NULL, ti_eqep_irq_handler,
528					IRQF_ONESHOT, dev_name(dev), counter);
529	if (err < 0)
530		return dev_err_probe(dev, err, "failed to request IRQ\n");
531
532	counter->name = dev_name(dev);
533	counter->parent = dev;
534	counter->ops = &ti_eqep_counter_ops;
535	counter->counts = ti_eqep_counts;
536	counter->num_counts = ARRAY_SIZE(ti_eqep_counts);
537	counter->signals = ti_eqep_signals;
538	counter->num_signals = ARRAY_SIZE(ti_eqep_signals);
539
540	platform_set_drvdata(pdev, counter);
541
542	/*
543	 * Need to make sure power is turned on. On AM33xx, this comes from the
544	 * parent PWMSS bus driver. On AM17xx, this comes from the PSC power
545	 * domain.
546	 */
547	pm_runtime_enable(dev);
548	pm_runtime_get_sync(dev);
549
550	clk = devm_clk_get_enabled(dev, NULL);
551	if (IS_ERR(clk))
552		return dev_err_probe(dev, PTR_ERR(clk), "failed to enable clock\n");
553
554	err = counter_add(counter);
555	if (err < 0) {
556		pm_runtime_put_sync(dev);
557		pm_runtime_disable(dev);
558		return err;
559	}
560
561	return 0;
562}
563
564static void ti_eqep_remove(struct platform_device *pdev)
565{
566	struct counter_device *counter = platform_get_drvdata(pdev);
567	struct device *dev = &pdev->dev;
568
569	counter_unregister(counter);
570	pm_runtime_put_sync(dev);
571	pm_runtime_disable(dev);
572}
573
574static const struct of_device_id ti_eqep_of_match[] = {
575	{ .compatible = "ti,am3352-eqep", },
576	{ .compatible = "ti,am62-eqep", },
577	{ },
578};
579MODULE_DEVICE_TABLE(of, ti_eqep_of_match);
580
581static struct platform_driver ti_eqep_driver = {
582	.probe = ti_eqep_probe,
583	.remove = ti_eqep_remove,
584	.driver = {
585		.name = "ti-eqep-cnt",
586		.of_match_table = ti_eqep_of_match,
587	},
588};
589module_platform_driver(ti_eqep_driver);
590
591MODULE_AUTHOR("David Lechner <david@lechnology.com>");
592MODULE_DESCRIPTION("TI eQEP counter driver");
593MODULE_LICENSE("GPL v2");
594MODULE_IMPORT_NS("COUNTER");