rz-mtu3-cnt.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Renesas RZ/G2L MTU3a Counter driver
  4 *
  5 * Copyright (C) 2022 Renesas Electronics Corporation
  6 */
  7
  8#include <linux/clk.h>
  9#include <linux/counter.h>
 10#include <linux/mfd/rz-mtu3.h>
 11#include <linux/module.h>
 12#include <linux/platform_device.h>
 13#include <linux/pm_runtime.h>
 14#include <linux/types.h>
 15
 16/*
 17 * Register descriptions
 18 *   TSR: Timer Status Register
 19 *   TMDR1: Timer Mode Register 1
 20 *   TMDR3: Timer Mode Register 3
 21 *   TIOR: Timer I/O Control Register
 22 *   TCR: Timer Control Register
 23 *   TCNT: Timer Counter
 24 *   TGRA: Timer general register A
 25 *   TCNTLW: Timer Longword Counter
 26 *   TGRALW: Timer longword general register A
 27 */
 28
 29#define RZ_MTU3_TSR_TCFD	BIT(7) /* Count Direction Flag */
 30
 31#define RZ_MTU3_TMDR1_PH_CNT_MODE_1	(4) /* Phase counting mode 1 */
 32#define RZ_MTU3_TMDR1_PH_CNT_MODE_2	(5) /* Phase counting mode 2 */
 33#define RZ_MTU3_TMDR1_PH_CNT_MODE_3	(6) /* Phase counting mode 3 */
 34#define RZ_MTU3_TMDR1_PH_CNT_MODE_4	(7) /* Phase counting mode 4 */
 35#define RZ_MTU3_TMDR1_PH_CNT_MODE_5	(9) /* Phase counting mode 5 */
 36#define RZ_MTU3_TMDR1_PH_CNT_MODE_MASK	(0xf)
 37
 38/*
 39 * LWA: MTU1/MTU2 Combination Longword Access Control
 40 * 0: 16-bit, 1: 32-bit
 41 */
 42#define RZ_MTU3_TMDR3_LWA	(0)
 43
 44/*
 45 * PHCKSEL: External Input Phase Clock Select
 46 * 0: MTCLKA and MTCLKB, 1: MTCLKC and MTCLKD
 47 */
 48#define RZ_MTU3_TMDR3_PHCKSEL	(1)
 49
 50#define RZ_MTU3_16_BIT_MTU1_CH	(0)
 51#define RZ_MTU3_16_BIT_MTU2_CH	(1)
 52#define RZ_MTU3_32_BIT_CH	(2)
 53
 54#define RZ_MTU3_TIOR_NO_OUTPUT	(0) /* Output prohibited */
 55#define RZ_MTU3_TIOR_IC_BOTH	(10) /* Input capture at both edges */
 56
 57#define SIGNAL_A_ID	(0)
 58#define SIGNAL_B_ID	(1)
 59#define SIGNAL_C_ID	(2)
 60#define SIGNAL_D_ID	(3)
 61
 62#define RZ_MTU3_MAX_HW_CNTR_CHANNELS	(2)
 63#define RZ_MTU3_MAX_LOGICAL_CNTR_CHANNELS	(3)
 64
 65/**
 66 * struct rz_mtu3_cnt - MTU3 counter private data
 67 *
 68 * @clk: MTU3 module clock
 69 * @lock: Lock to prevent concurrent access for ceiling and count
 70 * @ch: HW channels for the counters
 71 * @count_is_enabled: Enabled state of Counter value channel
 72 * @mtu_16bit_max: Cache for 16-bit counters
 73 * @mtu_32bit_max: Cache for 32-bit counters
 74 */
 75struct rz_mtu3_cnt {
 76	struct clk *clk;
 77	struct mutex lock;
 78	struct rz_mtu3_channel *ch;
 79	bool count_is_enabled[RZ_MTU3_MAX_LOGICAL_CNTR_CHANNELS];
 80	union {
 81		u16 mtu_16bit_max[RZ_MTU3_MAX_HW_CNTR_CHANNELS];
 82		u32 mtu_32bit_max;
 83	};
 84};
 85
 86static const enum counter_function rz_mtu3_count_functions[] = {
 87	COUNTER_FUNCTION_QUADRATURE_X4,
 88	COUNTER_FUNCTION_PULSE_DIRECTION,
 89	COUNTER_FUNCTION_QUADRATURE_X2_B,
 90};
 91
 92static inline size_t rz_mtu3_get_hw_ch(const size_t id)
 93{
 94	return (id == RZ_MTU3_32_BIT_CH) ? 0 : id;
 95}
 96
 97static inline struct rz_mtu3_channel *rz_mtu3_get_ch(struct counter_device *counter, int id)
 98{
 99	struct rz_mtu3_cnt *const priv = counter_priv(counter);
100	const size_t ch_id = rz_mtu3_get_hw_ch(id);
101
102	return &priv->ch[ch_id];
103}
104
105static bool rz_mtu3_is_counter_invalid(struct counter_device *counter, int id)
106{
107	struct rz_mtu3_cnt *const priv = counter_priv(counter);
108	unsigned long tmdr;
109
110	pm_runtime_get_sync(counter->parent);
111	tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
112	pm_runtime_put(counter->parent);
113
114	if (id == RZ_MTU3_32_BIT_CH && test_bit(RZ_MTU3_TMDR3_LWA, &tmdr))
115		return false;
116
117	if (id != RZ_MTU3_32_BIT_CH && !test_bit(RZ_MTU3_TMDR3_LWA, &tmdr))
118		return false;
119
120	return true;
121}
122
123static int rz_mtu3_lock_if_counter_is_valid(struct counter_device *counter,
124					    struct rz_mtu3_channel *const ch,
125					    struct rz_mtu3_cnt *const priv,
126					    int id)
127{
128	mutex_lock(&priv->lock);
129
130	if (ch->is_busy && !priv->count_is_enabled[id]) {
131		mutex_unlock(&priv->lock);
132		return -EINVAL;
133	}
134
135	if (rz_mtu3_is_counter_invalid(counter, id)) {
136		mutex_unlock(&priv->lock);
137		return -EBUSY;
138	}
139
140	return 0;
141}
142
143static int rz_mtu3_lock_if_count_is_enabled(struct rz_mtu3_channel *const ch,
144					    struct rz_mtu3_cnt *const priv,
145					    int id)
146{
147	mutex_lock(&priv->lock);
148
149	if (ch->is_busy && !priv->count_is_enabled[id]) {
150		mutex_unlock(&priv->lock);
151		return -EINVAL;
152	}
153
154	return 0;
155}
156
157static int rz_mtu3_count_read(struct counter_device *counter,
158			      struct counter_count *count, u64 *val)
159{
160	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
161	struct rz_mtu3_cnt *const priv = counter_priv(counter);
162	int ret;
163
164	ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id);
165	if (ret)
166		return ret;
167
168	pm_runtime_get_sync(counter->parent);
169	if (count->id == RZ_MTU3_32_BIT_CH)
170		*val = rz_mtu3_32bit_ch_read(ch, RZ_MTU3_TCNTLW);
171	else
172		*val = rz_mtu3_16bit_ch_read(ch, RZ_MTU3_TCNT);
173	pm_runtime_put(counter->parent);
174	mutex_unlock(&priv->lock);
175
176	return 0;
177}
178
179static int rz_mtu3_count_write(struct counter_device *counter,
180			       struct counter_count *count, const u64 val)
181{
182	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
183	struct rz_mtu3_cnt *const priv = counter_priv(counter);
184	int ret;
185
186	ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id);
187	if (ret)
188		return ret;
189
190	pm_runtime_get_sync(counter->parent);
191	if (count->id == RZ_MTU3_32_BIT_CH)
192		rz_mtu3_32bit_ch_write(ch, RZ_MTU3_TCNTLW, val);
193	else
194		rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TCNT, val);
195	pm_runtime_put(counter->parent);
196	mutex_unlock(&priv->lock);
197
198	return 0;
199}
200
201static int rz_mtu3_count_function_read_helper(struct rz_mtu3_channel *const ch,
202					      struct counter_device *const counter,
203					      enum counter_function *function)
204{
205	u8 timer_mode;
206
207	pm_runtime_get_sync(counter->parent);
208	timer_mode = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TMDR1);
209	pm_runtime_put(counter->parent);
210
211	switch (timer_mode & RZ_MTU3_TMDR1_PH_CNT_MODE_MASK) {
212	case RZ_MTU3_TMDR1_PH_CNT_MODE_1:
213		*function = COUNTER_FUNCTION_QUADRATURE_X4;
214		return 0;
215	case RZ_MTU3_TMDR1_PH_CNT_MODE_2:
216		*function = COUNTER_FUNCTION_PULSE_DIRECTION;
217		return 0;
218	case RZ_MTU3_TMDR1_PH_CNT_MODE_4:
219		*function = COUNTER_FUNCTION_QUADRATURE_X2_B;
220		return 0;
221	default:
222		/*
223		 * TODO:
224		 *  - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_3
225		 *  - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_5
226		 */
227		return -EINVAL;
228	}
229}
230
231static int rz_mtu3_count_function_read(struct counter_device *counter,
232				       struct counter_count *count,
233				       enum counter_function *function)
234{
235	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
236	struct rz_mtu3_cnt *const priv = counter_priv(counter);
237	int ret;
238
239	ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
240	if (ret)
241		return ret;
242
243	ret = rz_mtu3_count_function_read_helper(ch, counter, function);
244	mutex_unlock(&priv->lock);
245
246	return ret;
247}
248
249static int rz_mtu3_count_function_write(struct counter_device *counter,
250					struct counter_count *count,
251					enum counter_function function)
252{
253	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
254	struct rz_mtu3_cnt *const priv = counter_priv(counter);
255	u8 timer_mode;
256	int ret;
257
258	ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
259	if (ret)
260		return ret;
261
262	switch (function) {
263	case COUNTER_FUNCTION_QUADRATURE_X4:
264		timer_mode = RZ_MTU3_TMDR1_PH_CNT_MODE_1;
265		break;
266	case COUNTER_FUNCTION_PULSE_DIRECTION:
267		timer_mode = RZ_MTU3_TMDR1_PH_CNT_MODE_2;
268		break;
269	case COUNTER_FUNCTION_QUADRATURE_X2_B:
270		timer_mode = RZ_MTU3_TMDR1_PH_CNT_MODE_4;
271		break;
272	default:
273		/*
274		 * TODO:
275		 *  - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_3
276		 *  - need to add RZ_MTU3_TMDR1_PH_CNT_MODE_5
277		 */
278		mutex_unlock(&priv->lock);
279		return -EINVAL;
280	}
281
282	pm_runtime_get_sync(counter->parent);
283	rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TMDR1, timer_mode);
284	pm_runtime_put(counter->parent);
285	mutex_unlock(&priv->lock);
286
287	return 0;
288}
289
290static int rz_mtu3_count_direction_read(struct counter_device *counter,
291					struct counter_count *count,
292					enum counter_count_direction *direction)
293{
294	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
295	struct rz_mtu3_cnt *const priv = counter_priv(counter);
296	int ret;
297	u8 tsr;
298
299	ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
300	if (ret)
301		return ret;
302
303	pm_runtime_get_sync(counter->parent);
304	tsr = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TSR);
305	pm_runtime_put(counter->parent);
306
307	*direction = (tsr & RZ_MTU3_TSR_TCFD) ?
308		COUNTER_COUNT_DIRECTION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD;
309	mutex_unlock(&priv->lock);
310
311	return 0;
312}
313
314static int rz_mtu3_count_ceiling_read(struct counter_device *counter,
315				      struct counter_count *count,
316				      u64 *ceiling)
317{
318	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
319	struct rz_mtu3_cnt *const priv = counter_priv(counter);
320	const size_t ch_id = rz_mtu3_get_hw_ch(count->id);
321	int ret;
322
323	ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id);
324	if (ret)
325		return ret;
326
327	switch (count->id) {
328	case RZ_MTU3_16_BIT_MTU1_CH:
329	case RZ_MTU3_16_BIT_MTU2_CH:
330		*ceiling = priv->mtu_16bit_max[ch_id];
331		break;
332	case RZ_MTU3_32_BIT_CH:
333		*ceiling = priv->mtu_32bit_max;
334		break;
335	default:
336		/* should never reach this path */
337		mutex_unlock(&priv->lock);
338		return -EINVAL;
339	}
340
341	mutex_unlock(&priv->lock);
342	return 0;
343}
344
345static int rz_mtu3_count_ceiling_write(struct counter_device *counter,
346				       struct counter_count *count,
347				       u64 ceiling)
348{
349	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
350	struct rz_mtu3_cnt *const priv = counter_priv(counter);
351	const size_t ch_id = rz_mtu3_get_hw_ch(count->id);
352	int ret;
353
354	ret = rz_mtu3_lock_if_counter_is_valid(counter, ch, priv, count->id);
355	if (ret)
356		return ret;
357
358	switch (count->id) {
359	case RZ_MTU3_16_BIT_MTU1_CH:
360	case RZ_MTU3_16_BIT_MTU2_CH:
361		if (ceiling > U16_MAX) {
362			mutex_unlock(&priv->lock);
363			return -ERANGE;
364		}
365		priv->mtu_16bit_max[ch_id] = ceiling;
366		break;
367	case RZ_MTU3_32_BIT_CH:
368		if (ceiling > U32_MAX) {
369			mutex_unlock(&priv->lock);
370			return -ERANGE;
371		}
372		priv->mtu_32bit_max = ceiling;
373		break;
374	default:
375		/* should never reach this path */
376		mutex_unlock(&priv->lock);
377		return -EINVAL;
378	}
379
380	pm_runtime_get_sync(counter->parent);
381	if (count->id == RZ_MTU3_32_BIT_CH)
382		rz_mtu3_32bit_ch_write(ch, RZ_MTU3_TGRALW, ceiling);
383	else
384		rz_mtu3_16bit_ch_write(ch, RZ_MTU3_TGRA, ceiling);
385
386	rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TCR, RZ_MTU3_TCR_CCLR_TGRA);
387	pm_runtime_put(counter->parent);
388	mutex_unlock(&priv->lock);
389
390	return 0;
391}
392
393static void rz_mtu3_32bit_cnt_setting(struct counter_device *counter)
394{
395	struct rz_mtu3_channel *const ch1 = rz_mtu3_get_ch(counter, 0);
396	struct rz_mtu3_channel *const ch2 = rz_mtu3_get_ch(counter, 1);
397
398	/* Phase counting mode 1 is used as default in initialization. */
399	rz_mtu3_8bit_ch_write(ch1, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_PH_CNT_MODE_1);
400
401	rz_mtu3_8bit_ch_write(ch1, RZ_MTU3_TCR, RZ_MTU3_TCR_CCLR_TGRA);
402	rz_mtu3_8bit_ch_write(ch1, RZ_MTU3_TIOR, RZ_MTU3_TIOR_IC_BOTH);
403
404	rz_mtu3_enable(ch1);
405	rz_mtu3_enable(ch2);
406}
407
408static void rz_mtu3_16bit_cnt_setting(struct counter_device *counter, int id)
409{
410	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, id);
411
412	/* Phase counting mode 1 is used as default in initialization. */
413	rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_PH_CNT_MODE_1);
414
415	rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TCR, RZ_MTU3_TCR_CCLR_TGRA);
416	rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TIOR, RZ_MTU3_TIOR_NO_OUTPUT);
417	rz_mtu3_enable(ch);
418}
419
420static int rz_mtu3_initialize_counter(struct counter_device *counter, int id)
421{
422	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, id);
423	struct rz_mtu3_channel *const ch1 = rz_mtu3_get_ch(counter, 0);
424	struct rz_mtu3_channel *const ch2 = rz_mtu3_get_ch(counter, 1);
425
426	switch (id) {
427	case RZ_MTU3_16_BIT_MTU1_CH:
428	case RZ_MTU3_16_BIT_MTU2_CH:
429		if (!rz_mtu3_request_channel(ch))
430			return -EBUSY;
431
432		rz_mtu3_16bit_cnt_setting(counter, id);
433		return 0;
434	case RZ_MTU3_32_BIT_CH:
435		/*
436		 * 32-bit phase counting need MTU1 and MTU2 to create 32-bit
437		 * cascade counter.
438		 */
439		if (!rz_mtu3_request_channel(ch1))
440			return -EBUSY;
441
442		if (!rz_mtu3_request_channel(ch2)) {
443			rz_mtu3_release_channel(ch1);
444			return -EBUSY;
445		}
446
447		rz_mtu3_32bit_cnt_setting(counter);
448		return 0;
449	default:
450		/* should never reach this path */
451		return -EINVAL;
452	}
453}
454
455static void rz_mtu3_terminate_counter(struct counter_device *counter, int id)
456{
457	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, id);
458	struct rz_mtu3_channel *const ch1 = rz_mtu3_get_ch(counter, 0);
459	struct rz_mtu3_channel *const ch2 = rz_mtu3_get_ch(counter, 1);
460
461	if (id == RZ_MTU3_32_BIT_CH) {
462		rz_mtu3_release_channel(ch2);
463		rz_mtu3_release_channel(ch1);
464		rz_mtu3_disable(ch2);
465		rz_mtu3_disable(ch1);
466	} else {
467		rz_mtu3_release_channel(ch);
468		rz_mtu3_disable(ch);
469	}
470}
471
472static int rz_mtu3_count_enable_read(struct counter_device *counter,
473				     struct counter_count *count, u8 *enable)
474{
475	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
476	struct rz_mtu3_channel *const ch1 = rz_mtu3_get_ch(counter, 0);
477	struct rz_mtu3_channel *const ch2 = rz_mtu3_get_ch(counter, 1);
478	struct rz_mtu3_cnt *const priv = counter_priv(counter);
479	int ret;
480
481	ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
482	if (ret)
483		return ret;
484
485	if (count->id == RZ_MTU3_32_BIT_CH)
486		*enable = rz_mtu3_is_enabled(ch1) && rz_mtu3_is_enabled(ch2);
487	else
488		*enable = rz_mtu3_is_enabled(ch);
489
490	mutex_unlock(&priv->lock);
491
492	return 0;
493}
494
495static int rz_mtu3_count_enable_write(struct counter_device *counter,
496				      struct counter_count *count, u8 enable)
497{
498	struct rz_mtu3_cnt *const priv = counter_priv(counter);
499	int ret = 0;
500
501	mutex_lock(&priv->lock);
502
503	if (priv->count_is_enabled[count->id] == enable)
504		goto exit;
505
506	if (enable) {
507		pm_runtime_get_sync(counter->parent);
508		ret = rz_mtu3_initialize_counter(counter, count->id);
509		if (ret == 0)
510			priv->count_is_enabled[count->id] = true;
511	} else {
512		rz_mtu3_terminate_counter(counter, count->id);
513		priv->count_is_enabled[count->id] = false;
514		pm_runtime_put(counter->parent);
515	}
516
517exit:
518	mutex_unlock(&priv->lock);
519
520	return ret;
521}
522
523static int rz_mtu3_lock_if_ch0_is_enabled(struct rz_mtu3_cnt *const priv)
524{
525	mutex_lock(&priv->lock);
526	if (priv->ch->is_busy && !(priv->count_is_enabled[RZ_MTU3_16_BIT_MTU1_CH] ||
527				   priv->count_is_enabled[RZ_MTU3_32_BIT_CH])) {
528		mutex_unlock(&priv->lock);
529		return -EINVAL;
530	}
531
532	return 0;
533}
534
535static int rz_mtu3_cascade_counts_enable_get(struct counter_device *counter,
536					     u8 *cascade_enable)
537{
538	struct rz_mtu3_cnt *const priv = counter_priv(counter);
539	unsigned long tmdr;
540	int ret;
541
542	ret = rz_mtu3_lock_if_ch0_is_enabled(priv);
543	if (ret)
544		return ret;
545
546	pm_runtime_get_sync(counter->parent);
547	tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
548	pm_runtime_put(counter->parent);
549	*cascade_enable = test_bit(RZ_MTU3_TMDR3_LWA, &tmdr);
550	mutex_unlock(&priv->lock);
551
552	return 0;
553}
554
555static int rz_mtu3_cascade_counts_enable_set(struct counter_device *counter,
556					     u8 cascade_enable)
557{
558	struct rz_mtu3_cnt *const priv = counter_priv(counter);
559	int ret;
560
561	ret = rz_mtu3_lock_if_ch0_is_enabled(priv);
562	if (ret)
563		return ret;
564
565	pm_runtime_get_sync(counter->parent);
566	rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3,
567				      RZ_MTU3_TMDR3_LWA, cascade_enable);
568	pm_runtime_put(counter->parent);
569	mutex_unlock(&priv->lock);
570
571	return 0;
572}
573
574static int rz_mtu3_ext_input_phase_clock_select_get(struct counter_device *counter,
575						    u32 *ext_input_phase_clock_select)
576{
577	struct rz_mtu3_cnt *const priv = counter_priv(counter);
578	unsigned long tmdr;
579	int ret;
580
581	ret = rz_mtu3_lock_if_ch0_is_enabled(priv);
582	if (ret)
583		return ret;
584
585	pm_runtime_get_sync(counter->parent);
586	tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
587	pm_runtime_put(counter->parent);
588	*ext_input_phase_clock_select = test_bit(RZ_MTU3_TMDR3_PHCKSEL, &tmdr);
589	mutex_unlock(&priv->lock);
590
591	return 0;
592}
593
594static int rz_mtu3_ext_input_phase_clock_select_set(struct counter_device *counter,
595						    u32 ext_input_phase_clock_select)
596{
597	struct rz_mtu3_cnt *const priv = counter_priv(counter);
598	int ret;
599
600	ret = rz_mtu3_lock_if_ch0_is_enabled(priv);
601	if (ret)
602		return ret;
603
604	pm_runtime_get_sync(counter->parent);
605	rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3,
606				      RZ_MTU3_TMDR3_PHCKSEL,
607				      ext_input_phase_clock_select);
608	pm_runtime_put(counter->parent);
609	mutex_unlock(&priv->lock);
610
611	return 0;
612}
613
614static struct counter_comp rz_mtu3_count_ext[] = {
615	COUNTER_COMP_DIRECTION(rz_mtu3_count_direction_read),
616	COUNTER_COMP_ENABLE(rz_mtu3_count_enable_read,
617			    rz_mtu3_count_enable_write),
618	COUNTER_COMP_CEILING(rz_mtu3_count_ceiling_read,
619			     rz_mtu3_count_ceiling_write),
620};
621
622static const enum counter_synapse_action rz_mtu3_synapse_actions[] = {
623	COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
624	COUNTER_SYNAPSE_ACTION_RISING_EDGE,
625	COUNTER_SYNAPSE_ACTION_NONE,
626};
627
628static int rz_mtu3_action_read(struct counter_device *counter,
629			       struct counter_count *count,
630			       struct counter_synapse *synapse,
631			       enum counter_synapse_action *action)
632{
633	const bool is_signal_ab = (synapse->signal->id == SIGNAL_A_ID) ||
634				  (synapse->signal->id == SIGNAL_B_ID);
635	struct rz_mtu3_channel *const ch = rz_mtu3_get_ch(counter, count->id);
636	struct rz_mtu3_cnt *const priv = counter_priv(counter);
637	enum counter_function function;
638	bool mtclkc_mtclkd;
639	unsigned long tmdr;
640	int ret;
641
642	ret = rz_mtu3_lock_if_count_is_enabled(ch, priv, count->id);
643	if (ret)
644		return ret;
645
646	ret = rz_mtu3_count_function_read_helper(ch, counter, &function);
647	if (ret) {
648		mutex_unlock(&priv->lock);
649		return ret;
650	}
651
652	/* Default action mode */
653	*action = COUNTER_SYNAPSE_ACTION_NONE;
654
655	if (count->id != RZ_MTU3_16_BIT_MTU1_CH) {
656		tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
657		mtclkc_mtclkd = test_bit(RZ_MTU3_TMDR3_PHCKSEL, &tmdr);
658		if ((mtclkc_mtclkd && is_signal_ab) ||
659		    (!mtclkc_mtclkd && !is_signal_ab)) {
660			mutex_unlock(&priv->lock);
661			return 0;
662		}
663	}
664
665	switch (function) {
666	case COUNTER_FUNCTION_PULSE_DIRECTION:
667		/*
668		 * Rising edges on signal A (signal C) updates the respective
669		 * count. The input level of signal B (signal D) determines
670		 * direction.
671		 */
672		if (synapse->signal->id == SIGNAL_A_ID ||
673		    synapse->signal->id == SIGNAL_C_ID)
674			*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
675		break;
676	case COUNTER_FUNCTION_QUADRATURE_X2_B:
677		/*
678		 * Any state transition on quadrature pair signal B (signal D)
679		 * updates the respective count.
680		 */
681		if (synapse->signal->id == SIGNAL_B_ID ||
682		    synapse->signal->id == SIGNAL_D_ID)
683			*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
684		break;
685	case COUNTER_FUNCTION_QUADRATURE_X4:
686		/* counts up/down on both edges of A (C)  and B (D) signal */
687		*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
688		break;
689	default:
690		/* should never reach this path */
691		mutex_unlock(&priv->lock);
692		return -EINVAL;
693	}
694
695	mutex_unlock(&priv->lock);
696
697	return 0;
698}
699
700static const struct counter_ops rz_mtu3_cnt_ops = {
701	.count_read = rz_mtu3_count_read,
702	.count_write = rz_mtu3_count_write,
703	.function_read = rz_mtu3_count_function_read,
704	.function_write = rz_mtu3_count_function_write,
705	.action_read = rz_mtu3_action_read,
706};
707
708#define RZ_MTU3_PHASE_SIGNAL(_id, _name) {		\
709	.id = (_id),				\
710	.name = (_name),			\
711}
712
713static struct counter_signal rz_mtu3_signals[] = {
714	RZ_MTU3_PHASE_SIGNAL(SIGNAL_A_ID, "MTU1 MTCLKA"),
715	RZ_MTU3_PHASE_SIGNAL(SIGNAL_B_ID, "MTU1 MTCLKB"),
716	RZ_MTU3_PHASE_SIGNAL(SIGNAL_C_ID, "MTU2 MTCLKC"),
717	RZ_MTU3_PHASE_SIGNAL(SIGNAL_D_ID, "MTU2 MTCLKD"),
718};
719
720static struct counter_synapse rz_mtu3_mtu1_count_synapses[] = {
721	{
722		.actions_list = rz_mtu3_synapse_actions,
723		.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
724		.signal = rz_mtu3_signals,
725	},
726	{
727		.actions_list = rz_mtu3_synapse_actions,
728		.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
729		.signal = rz_mtu3_signals + 1,
730	}
731};
732
733static struct counter_synapse rz_mtu3_mtu2_count_synapses[] = {
734	{
735		.actions_list = rz_mtu3_synapse_actions,
736		.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
737		.signal = rz_mtu3_signals,
738	},
739	{
740		.actions_list = rz_mtu3_synapse_actions,
741		.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
742		.signal = rz_mtu3_signals + 1,
743	},
744	{
745		.actions_list = rz_mtu3_synapse_actions,
746		.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
747		.signal = rz_mtu3_signals + 2,
748	},
749	{
750		.actions_list = rz_mtu3_synapse_actions,
751		.num_actions = ARRAY_SIZE(rz_mtu3_synapse_actions),
752		.signal = rz_mtu3_signals + 3,
753	}
754};
755
756static struct counter_count rz_mtu3_counts[] = {
757	{
758		.id = RZ_MTU3_16_BIT_MTU1_CH,
759		.name = "Channel 1 Count",
760		.functions_list = rz_mtu3_count_functions,
761		.num_functions = ARRAY_SIZE(rz_mtu3_count_functions),
762		.synapses = rz_mtu3_mtu1_count_synapses,
763		.num_synapses = ARRAY_SIZE(rz_mtu3_mtu1_count_synapses),
764		.ext = rz_mtu3_count_ext,
765		.num_ext = ARRAY_SIZE(rz_mtu3_count_ext),
766	},
767	{
768		.id = RZ_MTU3_16_BIT_MTU2_CH,
769		.name = "Channel 2 Count",
770		.functions_list = rz_mtu3_count_functions,
771		.num_functions = ARRAY_SIZE(rz_mtu3_count_functions),
772		.synapses = rz_mtu3_mtu2_count_synapses,
773		.num_synapses = ARRAY_SIZE(rz_mtu3_mtu2_count_synapses),
774		.ext = rz_mtu3_count_ext,
775		.num_ext = ARRAY_SIZE(rz_mtu3_count_ext),
776	},
777	{
778		.id = RZ_MTU3_32_BIT_CH,
779		.name = "Channel 1 and 2 (cascaded) Count",
780		.functions_list = rz_mtu3_count_functions,
781		.num_functions = ARRAY_SIZE(rz_mtu3_count_functions),
782		.synapses = rz_mtu3_mtu2_count_synapses,
783		.num_synapses = ARRAY_SIZE(rz_mtu3_mtu2_count_synapses),
784		.ext = rz_mtu3_count_ext,
785		.num_ext = ARRAY_SIZE(rz_mtu3_count_ext),
786	}
787};
788
789static const char *const rz_mtu3_ext_input_phase_clock_select[] = {
790	"MTCLKA-MTCLKB",
791	"MTCLKC-MTCLKD",
792};
793
794static DEFINE_COUNTER_ENUM(rz_mtu3_ext_input_phase_clock_select_enum,
795			   rz_mtu3_ext_input_phase_clock_select);
796
797static struct counter_comp rz_mtu3_device_ext[] = {
798	COUNTER_COMP_DEVICE_BOOL("cascade_counts_enable",
799				 rz_mtu3_cascade_counts_enable_get,
800				 rz_mtu3_cascade_counts_enable_set),
801	COUNTER_COMP_DEVICE_ENUM("external_input_phase_clock_select",
802				 rz_mtu3_ext_input_phase_clock_select_get,
803				 rz_mtu3_ext_input_phase_clock_select_set,
804				 rz_mtu3_ext_input_phase_clock_select_enum),
805};
806
807static int rz_mtu3_cnt_pm_runtime_suspend(struct device *dev)
808{
809	struct clk *const clk = dev_get_drvdata(dev);
810
811	clk_disable_unprepare(clk);
812
813	return 0;
814}
815
816static int rz_mtu3_cnt_pm_runtime_resume(struct device *dev)
817{
818	struct clk *const clk = dev_get_drvdata(dev);
819
820	clk_prepare_enable(clk);
821
822	return 0;
823}
824
825static DEFINE_RUNTIME_DEV_PM_OPS(rz_mtu3_cnt_pm_ops,
826				 rz_mtu3_cnt_pm_runtime_suspend,
827				 rz_mtu3_cnt_pm_runtime_resume, NULL);
828
829static void rz_mtu3_cnt_pm_disable(void *data)
830{
831	struct device *dev = data;
832
833	pm_runtime_disable(dev);
834	pm_runtime_set_suspended(dev);
835}
836
837static int rz_mtu3_cnt_probe(struct platform_device *pdev)
838{
839	struct rz_mtu3 *ddata = dev_get_drvdata(pdev->dev.parent);
840	struct device *dev = &pdev->dev;
841	struct counter_device *counter;
842	struct rz_mtu3_channel *ch;
843	struct rz_mtu3_cnt *priv;
844	unsigned int i;
845	int ret;
846
847	counter = devm_counter_alloc(dev, sizeof(*priv));
848	if (!counter)
849		return -ENOMEM;
850
851	priv = counter_priv(counter);
852	priv->clk = ddata->clk;
853	priv->mtu_32bit_max = U32_MAX;
854	priv->ch = &ddata->channels[RZ_MTU3_CHAN_1];
855	ch = &priv->ch[0];
856	for (i = 0; i < RZ_MTU3_MAX_HW_CNTR_CHANNELS; i++) {
857		ch->dev = dev;
858		priv->mtu_16bit_max[i] = U16_MAX;
859		ch++;
860	}
861
862	mutex_init(&priv->lock);
863	platform_set_drvdata(pdev, priv->clk);
864	clk_prepare_enable(priv->clk);
865	pm_runtime_set_active(&pdev->dev);
866	pm_runtime_enable(&pdev->dev);
867	ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_cnt_pm_disable, dev);
868	if (ret < 0)
869		goto disable_clock;
870
871	counter->name = dev_name(dev);
872	counter->parent = dev;
873	counter->ops = &rz_mtu3_cnt_ops;
874	counter->counts = rz_mtu3_counts;
875	counter->num_counts = ARRAY_SIZE(rz_mtu3_counts);
876	counter->signals = rz_mtu3_signals;
877	counter->num_signals = ARRAY_SIZE(rz_mtu3_signals);
878	counter->ext = rz_mtu3_device_ext;
879	counter->num_ext = ARRAY_SIZE(rz_mtu3_device_ext);
880
881	/* Register Counter device */
882	ret = devm_counter_add(dev, counter);
883	if (ret < 0) {
884		dev_err_probe(dev, ret, "Failed to add counter\n");
885		goto disable_clock;
886	}
887
888	return 0;
889
890disable_clock:
891	clk_disable_unprepare(priv->clk);
892
893	return ret;
894}
895
896static struct platform_driver rz_mtu3_cnt_driver = {
897	.probe = rz_mtu3_cnt_probe,
898	.driver = {
899		.name = "rz-mtu3-counter",
900		.pm = pm_ptr(&rz_mtu3_cnt_pm_ops),
901	},
902};
903module_platform_driver(rz_mtu3_cnt_driver);
904
905MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
906MODULE_ALIAS("platform:rz-mtu3-counter");
907MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a counter driver");
908MODULE_LICENSE("GPL");
909MODULE_IMPORT_NS("COUNTER");