timer-ti-dm.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * linux/arch/arm/plat-omap/dmtimer.c
   4 *
   5 * OMAP Dual-Mode Timers
   6 *
   7 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
   8 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   9 * Thara Gopinath <thara@ti.com>
  10 *
  11 * dmtimer adaptation to platform_driver.
  12 *
  13 * Copyright (C) 2005 Nokia Corporation
  14 * OMAP2 support by Juha Yrjola
  15 * API improvements and OMAP2 clock framework support by Timo Teras
  16 *
  17 * Copyright (C) 2009 Texas Instruments
  18 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  19 */
  20
  21#include <linux/clk.h>
  22#include <linux/clk-provider.h>
  23#include <linux/cpu_pm.h>
  24#include <linux/module.h>
  25#include <linux/io.h>
  26#include <linux/device.h>
  27#include <linux/err.h>
  28#include <linux/pm_runtime.h>
  29#include <linux/of.h>
  30#include <linux/platform_device.h>
  31#include <linux/platform_data/dmtimer-omap.h>
  32
  33#include <clocksource/timer-ti-dm.h>
  34#include <linux/delay.h>
  35
  36/*
  37 * timer errata flags
  38 *
  39 * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
  40 * errata prevents us from using posted mode on these devices, unless the
  41 * timer counter register is never read. For more details please refer to
  42 * the OMAP3/4/5 errata documents.
  43 */
  44#define OMAP_TIMER_ERRATA_I103_I767			0x80000000
  45
  46/* posted mode types */
  47#define OMAP_TIMER_NONPOSTED			0x00
  48#define OMAP_TIMER_POSTED			0x01
  49
  50/* register offsets with the write pending bit encoded */
  51#define	WPSHIFT					16
  52
  53#define OMAP_TIMER_WAKEUP_EN_REG		(_OMAP_TIMER_WAKEUP_EN_OFFSET \
  54							| (WP_NONE << WPSHIFT))
  55
  56#define OMAP_TIMER_CTRL_REG			(_OMAP_TIMER_CTRL_OFFSET \
  57							| (WP_TCLR << WPSHIFT))
  58
  59#define OMAP_TIMER_COUNTER_REG			(_OMAP_TIMER_COUNTER_OFFSET \
  60							| (WP_TCRR << WPSHIFT))
  61
  62#define OMAP_TIMER_LOAD_REG			(_OMAP_TIMER_LOAD_OFFSET \
  63							| (WP_TLDR << WPSHIFT))
  64
  65#define OMAP_TIMER_TRIGGER_REG			(_OMAP_TIMER_TRIGGER_OFFSET \
  66							| (WP_TTGR << WPSHIFT))
  67
  68#define OMAP_TIMER_WRITE_PEND_REG		(_OMAP_TIMER_WRITE_PEND_OFFSET \
  69							| (WP_NONE << WPSHIFT))
  70
  71#define OMAP_TIMER_MATCH_REG			(_OMAP_TIMER_MATCH_OFFSET \
  72							| (WP_TMAR << WPSHIFT))
  73
  74#define OMAP_TIMER_CAPTURE_REG			(_OMAP_TIMER_CAPTURE_OFFSET \
  75							| (WP_NONE << WPSHIFT))
  76
  77#define OMAP_TIMER_IF_CTRL_REG			(_OMAP_TIMER_IF_CTRL_OFFSET \
  78							| (WP_NONE << WPSHIFT))
  79
  80#define OMAP_TIMER_CAPTURE2_REG			(_OMAP_TIMER_CAPTURE2_OFFSET \
  81							| (WP_NONE << WPSHIFT))
  82
  83#define OMAP_TIMER_TICK_POS_REG			(_OMAP_TIMER_TICK_POS_OFFSET \
  84							| (WP_TPIR << WPSHIFT))
  85
  86#define OMAP_TIMER_TICK_NEG_REG			(_OMAP_TIMER_TICK_NEG_OFFSET \
  87							| (WP_TNIR << WPSHIFT))
  88
  89#define OMAP_TIMER_TICK_COUNT_REG		(_OMAP_TIMER_TICK_COUNT_OFFSET \
  90							| (WP_TCVR << WPSHIFT))
  91
  92#define OMAP_TIMER_TICK_INT_MASK_SET_REG				\
  93		(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
  94
  95#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG				\
  96		(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
  97
  98struct timer_regs {
  99	u32 ocp_cfg;
 100	u32 tidr;
 101	u32 tier;
 102	u32 twer;
 103	u32 tclr;
 104	u32 tcrr;
 105	u32 tldr;
 106	u32 ttrg;
 107	u32 twps;
 108	u32 tmar;
 109	u32 tcar1;
 110	u32 tsicr;
 111	u32 tcar2;
 112	u32 tpir;
 113	u32 tnir;
 114	u32 tcvr;
 115	u32 tocr;
 116	u32 towr;
 117};
 118
 119struct dmtimer {
 120	struct omap_dm_timer cookie;
 121	int id;
 122	int irq;
 123	struct clk *fclk;
 124
 125	void __iomem	*io_base;
 126	int		irq_stat;	/* TISR/IRQSTATUS interrupt status */
 127	int		irq_ena;	/* irq enable */
 128	int		irq_dis;	/* irq disable, only on v2 ip */
 129	void __iomem	*pend;		/* write pending */
 130	void __iomem	*func_base;	/* function register base */
 131
 132	atomic_t enabled;
 133	unsigned reserved:1;
 134	unsigned posted:1;
 135	unsigned omap1:1;
 136	struct timer_regs context;
 137	int revision;
 138	u32 capability;
 139	u32 errata;
 140	struct platform_device *pdev;
 141	struct list_head node;
 142	struct notifier_block nb;
 143	struct notifier_block fclk_nb;
 144	unsigned long fclk_rate;
 145};
 146
 147static u32 omap_reserved_systimers;
 148static LIST_HEAD(omap_timer_list);
 149static DEFINE_SPINLOCK(dm_timer_lock);
 150
 151enum {
 152	REQUEST_ANY = 0,
 153	REQUEST_BY_ID,
 154	REQUEST_BY_CAP,
 155	REQUEST_BY_NODE,
 156};
 157
 158/**
 159 * dmtimer_read - read timer registers in posted and non-posted mode
 160 * @timer:	timer pointer over which read operation to perform
 161 * @reg:	lowest byte holds the register offset
 162 *
 163 * The posted mode bit is encoded in reg. Note that in posted mode, write
 164 * pending bit must be checked. Otherwise a read of a non completed write
 165 * will produce an error.
 166 */
 167static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg)
 168{
 169	u16 wp, offset;
 170
 171	wp = reg >> WPSHIFT;
 172	offset = reg & 0xff;
 173
 174	/* Wait for a possible write pending bit in posted mode */
 175	if (wp && timer->posted)
 176		while (readl_relaxed(timer->pend) & wp)
 177			cpu_relax();
 178
 179	return readl_relaxed(timer->func_base + offset);
 180}
 181
 182/**
 183 * dmtimer_write - write timer registers in posted and non-posted mode
 184 * @timer:      timer pointer over which write operation is to perform
 185 * @reg:        lowest byte holds the register offset
 186 * @val:        data to write into the register
 187 *
 188 * The posted mode bit is encoded in reg. Note that in posted mode, the write
 189 * pending bit must be checked. Otherwise a write on a register which has a
 190 * pending write will be lost.
 191 */
 192static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val)
 193{
 194	u16 wp, offset;
 195
 196	wp = reg >> WPSHIFT;
 197	offset = reg & 0xff;
 198
 199	/* Wait for a possible write pending bit in posted mode */
 200	if (wp && timer->posted)
 201		while (readl_relaxed(timer->pend) & wp)
 202			cpu_relax();
 203
 204	writel_relaxed(val, timer->func_base + offset);
 205}
 206
 207static inline void __omap_dm_timer_init_regs(struct dmtimer *timer)
 208{
 209	u32 tidr;
 210
 211	/* Assume v1 ip if bits [31:16] are zero */
 212	tidr = readl_relaxed(timer->io_base);
 213	if (!(tidr >> 16)) {
 214		timer->revision = 1;
 215		timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
 216		timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
 217		timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET;
 218		timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
 219		timer->func_base = timer->io_base;
 220	} else {
 221		timer->revision = 2;
 222		timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET;
 223		timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET;
 224		timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET;
 225		timer->pend = timer->io_base +
 226			_OMAP_TIMER_WRITE_PEND_OFFSET +
 227				OMAP_TIMER_V2_FUNC_OFFSET;
 228		timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
 229	}
 230}
 231
 232/*
 233 * __omap_dm_timer_enable_posted - enables write posted mode
 234 * @timer:      pointer to timer instance handle
 235 *
 236 * Enables the write posted mode for the timer. When posted mode is enabled
 237 * writes to certain timer registers are immediately acknowledged by the
 238 * internal bus and hence prevents stalling the CPU waiting for the write to
 239 * complete. Enabling this feature can improve performance for writing to the
 240 * timer registers.
 241 */
 242static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer)
 243{
 244	if (timer->posted)
 245		return;
 246
 247	if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
 248		timer->posted = OMAP_TIMER_NONPOSTED;
 249		dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0);
 250		return;
 251	}
 252
 253	dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED);
 254	timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
 255	timer->posted = OMAP_TIMER_POSTED;
 256}
 257
 258static inline void __omap_dm_timer_stop(struct dmtimer *timer)
 259{
 260	u32 l;
 261
 262	l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 263	if (l & OMAP_TIMER_CTRL_ST) {
 264		l &= ~0x1;
 265		dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 266#ifdef CONFIG_ARCH_OMAP2PLUS
 267		/* Readback to make sure write has completed */
 268		dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 269		/*
 270		 * Wait for functional clock period x 3.5 to make sure that
 271		 * timer is stopped
 272		 */
 273		udelay(3500000 / timer->fclk_rate + 1);
 274#endif
 275	}
 276
 277	/* Ack possibly pending interrupt */
 278	dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW);
 279}
 280
 281static inline void __omap_dm_timer_int_enable(struct dmtimer *timer,
 282					      unsigned int value)
 283{
 284	dmtimer_write(timer, timer->irq_ena, value);
 285	dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
 286}
 287
 288static inline unsigned int
 289__omap_dm_timer_read_counter(struct dmtimer *timer)
 290{
 291	return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG);
 292}
 293
 294static inline void __omap_dm_timer_write_status(struct dmtimer *timer,
 295						unsigned int value)
 296{
 297	dmtimer_write(timer, timer->irq_stat, value);
 298}
 299
 300static void omap_timer_restore_context(struct dmtimer *timer)
 301{
 302	dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg);
 303
 304	dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer);
 305	dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr);
 306	dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
 307	dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
 308	dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
 309	dmtimer_write(timer, timer->irq_ena, timer->context.tier);
 310	dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
 311}
 312
 313static void omap_timer_save_context(struct dmtimer *timer)
 314{
 315	timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
 316
 317	timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 318	timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
 319	timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
 320	timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
 321	timer->context.tier = dmtimer_read(timer, timer->irq_ena);
 322	timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
 323}
 324
 325static int omap_timer_context_notifier(struct notifier_block *nb,
 326				       unsigned long cmd, void *v)
 327{
 328	struct dmtimer *timer;
 329
 330	timer = container_of(nb, struct dmtimer, nb);
 331
 332	switch (cmd) {
 333	case CPU_CLUSTER_PM_ENTER:
 334		if ((timer->capability & OMAP_TIMER_ALWON) ||
 335		    !atomic_read(&timer->enabled))
 336			break;
 337		omap_timer_save_context(timer);
 338		break;
 339	case CPU_CLUSTER_PM_ENTER_FAILED:	/* No need to restore context */
 340		break;
 341	case CPU_CLUSTER_PM_EXIT:
 342		if ((timer->capability & OMAP_TIMER_ALWON) ||
 343		    !atomic_read(&timer->enabled))
 344			break;
 345		omap_timer_restore_context(timer);
 346		break;
 347	}
 348
 349	return NOTIFY_OK;
 350}
 351
 352static int omap_timer_fclk_notifier(struct notifier_block *nb,
 353				    unsigned long event, void *data)
 354{
 355	struct clk_notifier_data *clk_data = data;
 356	struct dmtimer *timer = container_of(nb, struct dmtimer, fclk_nb);
 357
 358	switch (event) {
 359	case POST_RATE_CHANGE:
 360		timer->fclk_rate = clk_data->new_rate;
 361		return NOTIFY_OK;
 362	default:
 363		return NOTIFY_DONE;
 364	}
 365}
 366
 367static int omap_dm_timer_reset(struct dmtimer *timer)
 368{
 369	u32 l, timeout = 100000;
 370
 371	if (timer->revision != 1)
 372		return -EINVAL;
 373
 374	dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 375
 376	do {
 377		l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
 378	} while (!l && timeout--);
 379
 380	if (!timeout) {
 381		dev_err(&timer->pdev->dev, "Timer failed to reset\n");
 382		return -ETIMEDOUT;
 383	}
 384
 385	/* Configure timer for smart-idle mode */
 386	l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
 387	l |= 0x2 << 0x3;
 388	dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l);
 389
 390	timer->posted = 0;
 391
 392	return 0;
 393}
 394
 395/*
 396 * Functions exposed to PWM and remoteproc drivers via platform_data.
 397 * Do not use these in the driver, these will get deprecated and will
 398 * will be replaced by Linux generic framework functions such as
 399 * chained interrupts and clock framework.
 400 */
 401static struct dmtimer *to_dmtimer(struct omap_dm_timer *cookie)
 402{
 403	if (!cookie)
 404		return NULL;
 405
 406	return container_of(cookie, struct dmtimer, cookie);
 407}
 408
 409static int omap_dm_timer_set_source(struct omap_dm_timer *cookie, int source)
 410{
 411	int ret;
 412	const char *parent_name;
 413	struct clk *parent;
 414	struct dmtimer_platform_data *pdata;
 415	struct dmtimer *timer;
 416
 417	timer = to_dmtimer(cookie);
 418	if (unlikely(!timer) || IS_ERR(timer->fclk))
 419		return -EINVAL;
 420
 421	switch (source) {
 422	case OMAP_TIMER_SRC_SYS_CLK:
 423		parent_name = "timer_sys_ck";
 424		break;
 425	case OMAP_TIMER_SRC_32_KHZ:
 426		parent_name = "timer_32k_ck";
 427		break;
 428	case OMAP_TIMER_SRC_EXT_CLK:
 429		parent_name = "timer_ext_ck";
 430		break;
 431	default:
 432		return -EINVAL;
 433	}
 434
 435	pdata = timer->pdev->dev.platform_data;
 436
 437	/*
 438	 * FIXME: Used for OMAP1 devices only because they do not currently
 439	 * use the clock framework to set the parent clock. To be removed
 440	 * once OMAP1 migrated to using clock framework for dmtimers
 441	 */
 442	if (timer->omap1 && pdata && pdata->set_timer_src)
 443		return pdata->set_timer_src(timer->pdev, source);
 444
 445#if defined(CONFIG_COMMON_CLK)
 446	/* Check if the clock has configurable parents */
 447	if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
 448		return 0;
 449#endif
 450
 451	parent = clk_get(&timer->pdev->dev, parent_name);
 452	if (IS_ERR(parent)) {
 453		pr_err("%s: %s not found\n", __func__, parent_name);
 454		return -EINVAL;
 455	}
 456
 457	ret = clk_set_parent(timer->fclk, parent);
 458	if (ret < 0)
 459		pr_err("%s: failed to set %s as parent\n", __func__,
 460			parent_name);
 461
 462	clk_put(parent);
 463
 464	return ret;
 465}
 466
 467static void omap_dm_timer_enable(struct omap_dm_timer *cookie)
 468{
 469	struct dmtimer *timer = to_dmtimer(cookie);
 470	struct device *dev = &timer->pdev->dev;
 471	int rc;
 472
 473	rc = pm_runtime_resume_and_get(dev);
 474	if (rc)
 475		dev_err(dev, "could not enable timer\n");
 476}
 477
 478static void omap_dm_timer_disable(struct omap_dm_timer *cookie)
 479{
 480	struct dmtimer *timer = to_dmtimer(cookie);
 481	struct device *dev = &timer->pdev->dev;
 482
 483	pm_runtime_put_sync(dev);
 484}
 485
 486static int omap_dm_timer_prepare(struct dmtimer *timer)
 487{
 488	struct device *dev = &timer->pdev->dev;
 489	int rc;
 490
 491	rc = pm_runtime_resume_and_get(dev);
 492	if (rc)
 493		return rc;
 494
 495	if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
 496		rc = omap_dm_timer_reset(timer);
 497		if (rc) {
 498			pm_runtime_put_sync(dev);
 499			return rc;
 500		}
 501	}
 502
 503	__omap_dm_timer_enable_posted(timer);
 504	pm_runtime_put_sync(dev);
 505
 506	return 0;
 507}
 508
 509static inline u32 omap_dm_timer_reserved_systimer(int id)
 510{
 511	return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
 512}
 513
 514static struct dmtimer *_omap_dm_timer_request(int req_type, void *data)
 515{
 516	struct dmtimer *timer = NULL, *t;
 517	struct device_node *np = NULL;
 518	unsigned long flags;
 519	u32 cap = 0;
 520	int id = 0;
 521
 522	switch (req_type) {
 523	case REQUEST_BY_ID:
 524		id = *(int *)data;
 525		break;
 526	case REQUEST_BY_CAP:
 527		cap = *(u32 *)data;
 528		break;
 529	case REQUEST_BY_NODE:
 530		np = (struct device_node *)data;
 531		break;
 532	default:
 533		/* REQUEST_ANY */
 534		break;
 535	}
 536
 537	spin_lock_irqsave(&dm_timer_lock, flags);
 538	list_for_each_entry(t, &omap_timer_list, node) {
 539		if (t->reserved)
 540			continue;
 541
 542		switch (req_type) {
 543		case REQUEST_BY_ID:
 544			if (id == t->pdev->id) {
 545				timer = t;
 546				timer->reserved = 1;
 547				goto found;
 548			}
 549			break;
 550		case REQUEST_BY_CAP:
 551			if (cap == (t->capability & cap)) {
 552				/*
 553				 * If timer is not NULL, we have already found
 554				 * one timer. But it was not an exact match
 555				 * because it had more capabilities than what
 556				 * was required. Therefore, unreserve the last
 557				 * timer found and see if this one is a better
 558				 * match.
 559				 */
 560				if (timer)
 561					timer->reserved = 0;
 562				timer = t;
 563				timer->reserved = 1;
 564
 565				/* Exit loop early if we find an exact match */
 566				if (t->capability == cap)
 567					goto found;
 568			}
 569			break;
 570		case REQUEST_BY_NODE:
 571			if (np == t->pdev->dev.of_node) {
 572				timer = t;
 573				timer->reserved = 1;
 574				goto found;
 575			}
 576			break;
 577		default:
 578			/* REQUEST_ANY */
 579			timer = t;
 580			timer->reserved = 1;
 581			goto found;
 582		}
 583	}
 584found:
 585	spin_unlock_irqrestore(&dm_timer_lock, flags);
 586
 587	if (timer && omap_dm_timer_prepare(timer)) {
 588		timer->reserved = 0;
 589		timer = NULL;
 590	}
 591
 592	if (!timer)
 593		pr_debug("%s: timer request failed!\n", __func__);
 594
 595	return timer;
 596}
 597
 598static struct omap_dm_timer *omap_dm_timer_request(void)
 599{
 600	struct dmtimer *timer;
 601
 602	timer = _omap_dm_timer_request(REQUEST_ANY, NULL);
 603	if (!timer)
 604		return NULL;
 605
 606	return &timer->cookie;
 607}
 608
 609static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 610{
 611	struct dmtimer *timer;
 612
 613	/* Requesting timer by ID is not supported when device tree is used */
 614	if (of_have_populated_dt()) {
 615		pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
 616			__func__);
 617		return NULL;
 618	}
 619
 620	timer = _omap_dm_timer_request(REQUEST_BY_ID, &id);
 621	if (!timer)
 622		return NULL;
 623
 624	return &timer->cookie;
 625}
 626
 627/**
 628 * omap_dm_timer_request_by_node - Request a timer by device-tree node
 629 * @np:		Pointer to device-tree timer node
 630 *
 631 * Request a timer based upon a device node pointer. Returns pointer to
 632 * timer handle on success and a NULL pointer on failure.
 633 */
 634static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
 635{
 636	struct dmtimer *timer;
 637
 638	if (!np)
 639		return NULL;
 640
 641	timer = _omap_dm_timer_request(REQUEST_BY_NODE, np);
 642	if (!timer)
 643		return NULL;
 644
 645	return &timer->cookie;
 646}
 647
 648static int omap_dm_timer_free(struct omap_dm_timer *cookie)
 649{
 650	struct dmtimer *timer;
 651	struct device *dev;
 652	int rc;
 653
 654	timer = to_dmtimer(cookie);
 655	if (unlikely(!timer))
 656		return -EINVAL;
 657
 658	WARN_ON(!timer->reserved);
 659	timer->reserved = 0;
 660
 661	dev = &timer->pdev->dev;
 662	rc = pm_runtime_resume_and_get(dev);
 663	if (rc)
 664		return rc;
 665
 666	/* Clear timer configuration */
 667	dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
 668
 669	pm_runtime_put_sync(dev);
 670
 671	return 0;
 672}
 673
 674static int omap_dm_timer_get_irq(struct omap_dm_timer *cookie)
 675{
 676	struct dmtimer *timer = to_dmtimer(cookie);
 677	if (timer)
 678		return timer->irq;
 679	return -EINVAL;
 680}
 681
 682#if defined(CONFIG_ARCH_OMAP1)
 683#include <linux/soc/ti/omap1-io.h>
 684
 685static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
 686{
 687	return NULL;
 688}
 689
 690/**
 691 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 692 * @inputmask: current value of idlect mask
 693 */
 694__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 695{
 696	int i = 0;
 697	struct dmtimer *timer = NULL;
 698	unsigned long flags;
 699
 700	/* If ARMXOR cannot be idled this function call is unnecessary */
 701	if (!(inputmask & (1 << 1)))
 702		return inputmask;
 703
 704	/* If any active timer is using ARMXOR return modified mask */
 705	spin_lock_irqsave(&dm_timer_lock, flags);
 706	list_for_each_entry(timer, &omap_timer_list, node) {
 707		u32 l;
 708
 709		l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 710		if (l & OMAP_TIMER_CTRL_ST) {
 711			if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 712				inputmask &= ~(1 << 1);
 713			else
 714				inputmask &= ~(1 << 2);
 715		}
 716		i++;
 717	}
 718	spin_unlock_irqrestore(&dm_timer_lock, flags);
 719
 720	return inputmask;
 721}
 722
 723#else
 724
 725static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie)
 726{
 727	struct dmtimer *timer = to_dmtimer(cookie);
 728
 729	if (timer && !IS_ERR(timer->fclk))
 730		return timer->fclk;
 731	return NULL;
 732}
 733
 734__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 735{
 736	BUG();
 737
 738	return 0;
 739}
 740
 741#endif
 742
 743static int omap_dm_timer_start(struct omap_dm_timer *cookie)
 744{
 745	struct dmtimer *timer;
 746	struct device *dev;
 747	int rc;
 748	u32 l;
 749
 750	timer = to_dmtimer(cookie);
 751	if (unlikely(!timer))
 752		return -EINVAL;
 753
 754	dev = &timer->pdev->dev;
 755
 756	rc = pm_runtime_resume_and_get(dev);
 757	if (rc)
 758		return rc;
 759
 760	l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 761	if (!(l & OMAP_TIMER_CTRL_ST)) {
 762		l |= OMAP_TIMER_CTRL_ST;
 763		dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 764	}
 765
 766	return 0;
 767}
 768
 769static int omap_dm_timer_stop(struct omap_dm_timer *cookie)
 770{
 771	struct dmtimer *timer;
 772	struct device *dev;
 773
 774	timer = to_dmtimer(cookie);
 775	if (unlikely(!timer))
 776		return -EINVAL;
 777
 778	dev = &timer->pdev->dev;
 779
 780	__omap_dm_timer_stop(timer);
 781
 782	pm_runtime_put_sync(dev);
 783
 784	return 0;
 785}
 786
 787static int omap_dm_timer_set_load(struct omap_dm_timer *cookie,
 788				  unsigned int load)
 789{
 790	struct dmtimer *timer;
 791	struct device *dev;
 792	int rc;
 793
 794	timer = to_dmtimer(cookie);
 795	if (unlikely(!timer))
 796		return -EINVAL;
 797
 798	dev = &timer->pdev->dev;
 799	rc = pm_runtime_resume_and_get(dev);
 800	if (rc)
 801		return rc;
 802
 803	dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load);
 804
 805	pm_runtime_put_sync(dev);
 806
 807	return 0;
 808}
 809
 810static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable,
 811				   unsigned int match)
 812{
 813	struct dmtimer *timer;
 814	struct device *dev;
 815	int rc;
 816	u32 l;
 817
 818	timer = to_dmtimer(cookie);
 819	if (unlikely(!timer))
 820		return -EINVAL;
 821
 822	dev = &timer->pdev->dev;
 823	rc = pm_runtime_resume_and_get(dev);
 824	if (rc)
 825		return rc;
 826
 827	l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 828	if (enable)
 829		l |= OMAP_TIMER_CTRL_CE;
 830	else
 831		l &= ~OMAP_TIMER_CTRL_CE;
 832	dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match);
 833	dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 834
 835	pm_runtime_put_sync(dev);
 836
 837	return 0;
 838}
 839
 840static int omap_dm_timer_set_cap(struct omap_dm_timer *cookie,
 841					int autoreload, bool config_period)
 842{
 843	struct dmtimer *timer;
 844	struct device *dev;
 845	int rc;
 846	u32 l;
 847
 848	timer = to_dmtimer(cookie);
 849	if (unlikely(!timer))
 850		return -EINVAL;
 851
 852	dev = &timer->pdev->dev;
 853	rc = pm_runtime_resume_and_get(dev);
 854	if (rc)
 855		return rc;
 856	/*
 857	 *  1. Select autoreload mode. TIMER_TCLR[1] AR bit.
 858	 *  2. TIMER_TCLR[14]: Sets the functionality of the TIMER IO pin.
 859	 *  3. TIMER_TCLR[13] : Capture mode select bit.
 860	 *  3. TIMER_TCLR[9-8] : Select transition capture mode.
 861	 */
 862
 863	l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 864
 865	if (autoreload)
 866		l |= OMAP_TIMER_CTRL_AR;
 867
 868	l |= OMAP_TIMER_CTRL_CAPTMODE | OMAP_TIMER_CTRL_GPOCFG;
 869
 870	if (config_period == true)
 871		l |= OMAP_TIMER_CTRL_TCM_LOWTOHIGH; /* Time Period config */
 872	else
 873		l |= OMAP_TIMER_CTRL_TCM_BOTHEDGES; /* Duty Cycle config */
 874
 875	dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 876
 877	pm_runtime_put_sync(dev);
 878
 879	return 0;
 880}
 881
 882static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on,
 883				 int toggle, int trigger, int autoreload)
 884{
 885	struct dmtimer *timer;
 886	struct device *dev;
 887	int rc;
 888	u32 l;
 889
 890	timer = to_dmtimer(cookie);
 891	if (unlikely(!timer))
 892		return -EINVAL;
 893
 894	dev = &timer->pdev->dev;
 895	rc = pm_runtime_resume_and_get(dev);
 896	if (rc)
 897		return rc;
 898
 899	l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 900	l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 901	       OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
 902	if (def_on)
 903		l |= OMAP_TIMER_CTRL_SCPWM;
 904	if (toggle)
 905		l |= OMAP_TIMER_CTRL_PT;
 906	l |= trigger << 10;
 907	if (autoreload)
 908		l |= OMAP_TIMER_CTRL_AR;
 909	dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 910
 911	pm_runtime_put_sync(dev);
 912
 913	return 0;
 914}
 915
 916static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *cookie)
 917{
 918	struct dmtimer *timer;
 919	struct device *dev;
 920	int rc;
 921	u32 l;
 922
 923	timer = to_dmtimer(cookie);
 924	if (unlikely(!timer))
 925		return -EINVAL;
 926
 927	dev = &timer->pdev->dev;
 928	rc = pm_runtime_resume_and_get(dev);
 929	if (rc)
 930		return rc;
 931
 932	l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 933
 934	pm_runtime_put_sync(dev);
 935
 936	return l;
 937}
 938
 939static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie,
 940				       int prescaler)
 941{
 942	struct dmtimer *timer;
 943	struct device *dev;
 944	int rc;
 945	u32 l;
 946
 947	timer = to_dmtimer(cookie);
 948	if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
 949		return -EINVAL;
 950
 951	dev = &timer->pdev->dev;
 952	rc = pm_runtime_resume_and_get(dev);
 953	if (rc)
 954		return rc;
 955
 956	l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
 957	l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 958	if (prescaler >= 0) {
 959		l |= OMAP_TIMER_CTRL_PRE;
 960		l |= prescaler << 2;
 961	}
 962	dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
 963
 964	pm_runtime_put_sync(dev);
 965
 966	return 0;
 967}
 968
 969static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie,
 970					unsigned int value)
 971{
 972	struct dmtimer *timer;
 973	struct device *dev;
 974	int rc;
 975
 976	timer = to_dmtimer(cookie);
 977	if (unlikely(!timer))
 978		return -EINVAL;
 979
 980	dev = &timer->pdev->dev;
 981	rc = pm_runtime_resume_and_get(dev);
 982	if (rc)
 983		return rc;
 984
 985	__omap_dm_timer_int_enable(timer, value);
 986
 987	pm_runtime_put_sync(dev);
 988
 989	return 0;
 990}
 991
 992/**
 993 * omap_dm_timer_set_int_disable - disable timer interrupts
 994 * @cookie:	pointer to timer cookie
 995 * @mask:	bit mask of interrupts to be disabled
 996 *
 997 * Disables the specified timer interrupts for a timer.
 998 */
 999static int omap_dm_timer_set_int_disable(struct omap_dm_timer *cookie, u32 mask)
1000{
1001	struct dmtimer *timer;
1002	struct device *dev;
1003	u32 l = mask;
1004	int rc;
1005
1006	timer = to_dmtimer(cookie);
1007	if (unlikely(!timer))
1008		return -EINVAL;
1009
1010	dev = &timer->pdev->dev;
1011	rc = pm_runtime_resume_and_get(dev);
1012	if (rc)
1013		return rc;
1014
1015	if (timer->revision == 1)
1016		l = dmtimer_read(timer, timer->irq_ena) & ~mask;
1017
1018	dmtimer_write(timer, timer->irq_dis, l);
1019	l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
1020	dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
1021
1022	pm_runtime_put_sync(dev);
1023
1024	return 0;
1025}
1026
1027static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *cookie)
1028{
1029	struct dmtimer *timer;
1030	unsigned int l;
1031
1032	timer = to_dmtimer(cookie);
1033	if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1034		pr_err("%s: timer not available or enabled.\n", __func__);
1035		return 0;
1036	}
1037
1038	l = dmtimer_read(timer, timer->irq_stat);
1039
1040	return l;
1041}
1042
1043static int omap_dm_timer_write_status(struct omap_dm_timer *cookie, unsigned int value)
1044{
1045	struct dmtimer *timer;
1046
1047	timer = to_dmtimer(cookie);
1048	if (unlikely(!timer || !atomic_read(&timer->enabled)))
1049		return -EINVAL;
1050
1051	__omap_dm_timer_write_status(timer, value);
1052
1053	return 0;
1054}
1055
1056static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *cookie)
1057{
1058	struct dmtimer *timer;
1059
1060	timer = to_dmtimer(cookie);
1061	if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1062		pr_err("%s: timer not iavailable or enabled.\n", __func__);
1063		return 0;
1064	}
1065
1066	return __omap_dm_timer_read_counter(timer);
1067}
1068
1069static inline unsigned int __omap_dm_timer_cap(struct dmtimer *timer, int idx)
1070{
1071	return idx == 0 ? dmtimer_read(timer, OMAP_TIMER_CAPTURE_REG) :
1072			  dmtimer_read(timer, OMAP_TIMER_CAPTURE2_REG);
1073}
1074
1075static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsigned int value)
1076{
1077	struct dmtimer *timer;
1078	struct device *dev;
1079
1080	timer = to_dmtimer(cookie);
1081	if (unlikely(!timer)) {
1082		pr_err("%s: timer not available.\n", __func__);
1083		return -EINVAL;
1084	}
1085
1086	dev = &timer->pdev->dev;
1087
1088	pm_runtime_resume_and_get(dev);
1089	dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value);
1090	pm_runtime_put_sync(dev);
1091
1092	/* Save the context */
1093	timer->context.tcrr = value;
1094	return 0;
1095}
1096
1097/**
1098 * omap_dm_timer_cap_counter() - Calculate the high count or period count depending on the
1099 * configuration.
1100 * @cookie:Pointer to OMAP DM timer
1101 * @is_period:Whether to configure timer in period or duty cycle mode
1102 *
1103 * Return high count or period count if timer is enabled else appropriate error.
1104 */
1105static unsigned int omap_dm_timer_cap_counter(struct omap_dm_timer *cookie,	bool is_period)
1106{
1107	struct dmtimer *timer;
1108	unsigned int cap1 = 0;
1109	unsigned int cap2 = 0;
1110	u32 l, ret;
1111
1112	timer = to_dmtimer(cookie);
1113	if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1114		pr_err("%s:timer is not available or enabled.%p\n", __func__, (void *)timer);
1115		return -EINVAL;
1116	}
1117
1118	/* Stop the timer */
1119	omap_dm_timer_stop(cookie);
1120
1121	/* Clear the timer counter value to 0 */
1122	ret = omap_dm_timer_write_counter(cookie, 0);
1123	if (ret)
1124		return ret;
1125
1126	/* Sets the timer capture configuration for period/duty cycle calculation */
1127	ret = omap_dm_timer_set_cap(cookie, true, is_period);
1128	if (ret) {
1129		pr_err("%s: Failed to set timer capture configuration.\n", __func__);
1130		return ret;
1131	}
1132	/* Start the timer */
1133	omap_dm_timer_start(cookie);
1134
1135	/*
1136	 * 1 sec delay is given so as to provide
1137	 * enough time to capture low frequency signals.
1138	 */
1139	msleep(1000);
1140
1141	cap1 = __omap_dm_timer_cap(timer, 0);
1142	cap2 = __omap_dm_timer_cap(timer, 1);
1143
1144	/*
1145	 *  Clears the TCLR configuration.
1146	 *  The start bit must be set to 1 as the timer is already in start mode.
1147	 */
1148	l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
1149	l &= ~(0xffff) | 0x1;
1150	dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
1151
1152	return (cap2-cap1);
1153}
1154
1155static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
1156{
1157	struct dmtimer *timer = dev_get_drvdata(dev);
1158
1159	atomic_set(&timer->enabled, 0);
1160
1161	if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
1162		return 0;
1163
1164	omap_timer_save_context(timer);
1165
1166	return 0;
1167}
1168
1169static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
1170{
1171	struct dmtimer *timer = dev_get_drvdata(dev);
1172
1173	if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
1174		omap_timer_restore_context(timer);
1175
1176	atomic_set(&timer->enabled, 1);
1177
1178	return 0;
1179}
1180
1181static const struct dev_pm_ops omap_dm_timer_pm_ops = {
1182	SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend,
1183			   omap_dm_timer_runtime_resume, NULL)
1184};
1185
1186static const struct of_device_id omap_timer_match[];
1187
1188/**
1189 * omap_dm_timer_probe - probe function called for every registered device
1190 * @pdev:	pointer to current timer platform device
1191 *
1192 * Called by driver framework at the end of device registration for all
1193 * timer devices.
1194 */
1195static int omap_dm_timer_probe(struct platform_device *pdev)
1196{
1197	unsigned long flags;
1198	struct dmtimer *timer;
1199	struct device *dev = &pdev->dev;
1200	const struct dmtimer_platform_data *pdata;
1201	int ret;
1202
1203	pdata = of_device_get_match_data(dev);
1204	if (!pdata)
1205		pdata = dev_get_platdata(dev);
1206	else
1207		dev->platform_data = (void *)pdata;
1208
1209	if (!pdata) {
1210		dev_err(dev, "%s: no platform data.\n", __func__);
1211		return -ENODEV;
1212	}
1213
1214	timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
1215	if (!timer)
1216		return  -ENOMEM;
1217
1218	timer->irq = platform_get_irq(pdev, 0);
1219	if (timer->irq < 0) {
1220		if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
1221			dev_info(dev, "Did not find timer interrupt, timer usable in PWM mode only\n");
1222		else
1223			return timer->irq;
1224	}
1225
1226	timer->io_base = devm_platform_ioremap_resource(pdev, 0);
1227	if (IS_ERR(timer->io_base))
1228		return PTR_ERR(timer->io_base);
1229
1230	platform_set_drvdata(pdev, timer);
1231
1232	if (dev->of_node) {
1233		if (of_property_read_bool(dev->of_node, "ti,timer-alwon"))
1234			timer->capability |= OMAP_TIMER_ALWON;
1235		if (of_property_read_bool(dev->of_node, "ti,timer-dsp"))
1236			timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
1237		if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
1238			timer->capability |= OMAP_TIMER_HAS_PWM;
1239		if (of_property_read_bool(dev->of_node, "ti,timer-secure"))
1240			timer->capability |= OMAP_TIMER_SECURE;
1241	} else {
1242		timer->id = pdev->id;
1243		timer->capability = pdata->timer_capability;
1244		timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
1245	}
1246
1247	timer->omap1 = timer->capability & OMAP_TIMER_NEEDS_RESET;
1248
1249	/* OMAP1 devices do not yet use the clock framework for dmtimers */
1250	if (!timer->omap1) {
1251		timer->fclk = devm_clk_get(dev, "fck");
1252		if (IS_ERR(timer->fclk))
1253			return PTR_ERR(timer->fclk);
1254
1255		timer->fclk_nb.notifier_call = omap_timer_fclk_notifier;
1256		ret = devm_clk_notifier_register(dev, timer->fclk,
1257						 &timer->fclk_nb);
1258		if (ret)
1259			return ret;
1260
1261		timer->fclk_rate = clk_get_rate(timer->fclk);
1262	} else {
1263		timer->fclk = ERR_PTR(-ENODEV);
1264	}
1265
1266	if (!(timer->capability & OMAP_TIMER_ALWON)) {
1267		timer->nb.notifier_call = omap_timer_context_notifier;
1268		cpu_pm_register_notifier(&timer->nb);
1269	}
1270
1271	timer->errata = pdata->timer_errata;
1272
1273	timer->pdev = pdev;
1274
1275	pm_runtime_enable(dev);
1276
1277	if (!timer->reserved) {
1278		ret = pm_runtime_resume_and_get(dev);
1279		if (ret) {
1280			dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
1281				__func__);
1282			goto err_disable;
1283		}
1284		__omap_dm_timer_init_regs(timer);
1285
1286		/* Clear timer configuration */
1287		dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
1288
1289		pm_runtime_put(dev);
1290	}
1291
1292	/* add the timer element to the list */
1293	spin_lock_irqsave(&dm_timer_lock, flags);
1294	list_add_tail(&timer->node, &omap_timer_list);
1295	spin_unlock_irqrestore(&dm_timer_lock, flags);
1296
1297	dev_dbg(dev, "Device Probed.\n");
1298
1299	return 0;
1300
1301err_disable:
1302	pm_runtime_disable(dev);
1303	return ret;
1304}
1305
1306/**
1307 * omap_dm_timer_remove - cleanup a registered timer device
1308 * @pdev:	pointer to current timer platform device
1309 *
1310 * Called by driver framework whenever a timer device is unregistered.
1311 * In addition to freeing platform resources it also deletes the timer
1312 * entry from the local list.
1313 */
1314static void omap_dm_timer_remove(struct platform_device *pdev)
1315{
1316	struct dmtimer *timer;
1317	unsigned long flags;
1318	int ret = -EINVAL;
1319
1320	spin_lock_irqsave(&dm_timer_lock, flags);
1321	list_for_each_entry(timer, &omap_timer_list, node)
1322		if (!strcmp(dev_name(&timer->pdev->dev),
1323			    dev_name(&pdev->dev))) {
1324			if (!(timer->capability & OMAP_TIMER_ALWON))
1325				cpu_pm_unregister_notifier(&timer->nb);
1326			list_del(&timer->node);
1327			ret = 0;
1328			break;
1329		}
1330	spin_unlock_irqrestore(&dm_timer_lock, flags);
1331
1332	pm_runtime_disable(&pdev->dev);
1333
1334	if (ret)
1335		dev_err(&pdev->dev, "Unable to determine timer entry in list of drivers on remove\n");
1336}
1337
1338static const struct omap_dm_timer_ops dmtimer_ops = {
1339	.request_by_node = omap_dm_timer_request_by_node,
1340	.request_specific = omap_dm_timer_request_specific,
1341	.request = omap_dm_timer_request,
1342	.set_source = omap_dm_timer_set_source,
1343	.get_irq = omap_dm_timer_get_irq,
1344	.set_int_enable = omap_dm_timer_set_int_enable,
1345	.set_int_disable = omap_dm_timer_set_int_disable,
1346	.free = omap_dm_timer_free,
1347	.enable = omap_dm_timer_enable,
1348	.disable = omap_dm_timer_disable,
1349	.get_fclk = omap_dm_timer_get_fclk,
1350	.start = omap_dm_timer_start,
1351	.stop = omap_dm_timer_stop,
1352	.set_load = omap_dm_timer_set_load,
1353	.set_match = omap_dm_timer_set_match,
1354	.set_pwm = omap_dm_timer_set_pwm,
1355	.get_pwm_status = omap_dm_timer_get_pwm_status,
1356	.set_prescaler = omap_dm_timer_set_prescaler,
1357	.read_counter = omap_dm_timer_read_counter,
1358	.write_counter = omap_dm_timer_write_counter,
1359	.read_status = omap_dm_timer_read_status,
1360	.write_status = omap_dm_timer_write_status,
1361	.set_cap = omap_dm_timer_set_cap,
1362	.get_cap_status = omap_dm_timer_get_pwm_status,
1363	.read_cap = omap_dm_timer_cap_counter,
1364};
1365
1366static const struct dmtimer_platform_data omap3plus_pdata = {
1367	.timer_errata = OMAP_TIMER_ERRATA_I103_I767,
1368	.timer_ops = &dmtimer_ops,
1369};
1370
1371static const struct dmtimer_platform_data am6_pdata = {
1372	.timer_ops = &dmtimer_ops,
1373};
1374
1375static const struct of_device_id omap_timer_match[] = {
1376	{
1377		.compatible = "ti,omap2420-timer",
1378	},
1379	{
1380		.compatible = "ti,omap3430-timer",
1381		.data = &omap3plus_pdata,
1382	},
1383	{
1384		.compatible = "ti,omap4430-timer",
1385		.data = &omap3plus_pdata,
1386	},
1387	{
1388		.compatible = "ti,omap5430-timer",
1389		.data = &omap3plus_pdata,
1390	},
1391	{
1392		.compatible = "ti,am335x-timer",
1393		.data = &omap3plus_pdata,
1394	},
1395	{
1396		.compatible = "ti,am335x-timer-1ms",
1397		.data = &omap3plus_pdata,
1398	},
1399	{
1400		.compatible = "ti,dm816-timer",
1401		.data = &omap3plus_pdata,
1402	},
1403	{
1404		.compatible = "ti,am654-timer",
1405		.data = &am6_pdata,
1406	},
1407	{},
1408};
1409MODULE_DEVICE_TABLE(of, omap_timer_match);
1410
1411static struct platform_driver omap_dm_timer_driver = {
1412	.probe  = omap_dm_timer_probe,
1413	.remove = omap_dm_timer_remove,
1414	.driver = {
1415		.name   = "omap_timer",
1416		.of_match_table = omap_timer_match,
1417		.pm = &omap_dm_timer_pm_ops,
1418	},
1419};
1420
1421module_platform_driver(omap_dm_timer_driver);
1422
1423MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
1424MODULE_AUTHOR("Texas Instruments Inc");