timer-stm32-lp.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
  4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
  5 *	    Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
  6 */
  7
  8#include <linux/bitfield.h>
  9#include <linux/clk.h>
 10#include <linux/clockchips.h>
 11#include <linux/interrupt.h>
 12#include <linux/mfd/stm32-lptimer.h>
 13#include <linux/module.h>
 14#include <linux/of_address.h>
 15#include <linux/of_irq.h>
 16#include <linux/platform_device.h>
 17#include <linux/pm_wakeirq.h>
 18
 19#define CFGR_PSC_OFFSET		9
 20#define STM32_LP_RATING		1000
 21#define STM32_TARGET_CLKRATE	(32000 * HZ)
 22#define STM32_LP_MAX_PSC	7
 23
 24struct stm32_lp_private {
 25	struct regmap *reg;
 26	struct clock_event_device clkevt;
 27	unsigned long period;
 28	u32 psc;
 29	struct device *dev;
 30	struct clk *clk;
 31	u32 version;
 32};
 33
 34static struct stm32_lp_private*
 35to_priv(struct clock_event_device *clkevt)
 36{
 37	return container_of(clkevt, struct stm32_lp_private, clkevt);
 38}
 39
 40static int stm32_clkevent_lp_shutdown(struct clock_event_device *clkevt)
 41{
 42	struct stm32_lp_private *priv = to_priv(clkevt);
 43
 44	regmap_write(priv->reg, STM32_LPTIM_CR, 0);
 45	regmap_write(priv->reg, STM32_LPTIM_IER, 0);
 46	/* clear pending flags */
 47	regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF);
 48
 49	return 0;
 50}
 51
 52static int stm32mp25_clkevent_lp_set_evt(struct stm32_lp_private *priv, unsigned long evt)
 53{
 54	int ret;
 55	u32 val;
 56
 57	regmap_read(priv->reg, STM32_LPTIM_CR, &val);
 58	if (!FIELD_GET(STM32_LPTIM_ENABLE, val)) {
 59		/* Enable LPTIMER to be able to write into IER and ARR registers */
 60		regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE);
 61		/*
 62		 * After setting the ENABLE bit, a delay of two counter clock cycles is needed
 63		 * before the LPTIM is actually enabled. For 32KHz rate, this makes approximately
 64		 * 62.5 micro-seconds, round it up.
 65		 */
 66		udelay(63);
 67	}
 68	/* set next event counter */
 69	regmap_write(priv->reg, STM32_LPTIM_ARR, evt);
 70	/* enable ARR interrupt */
 71	regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE);
 72
 73	/* Poll DIEROK and ARROK to ensure register access has completed */
 74	ret = regmap_read_poll_timeout_atomic(priv->reg, STM32_LPTIM_ISR, val,
 75					      (val & STM32_LPTIM_DIEROK_ARROK) ==
 76					      STM32_LPTIM_DIEROK_ARROK,
 77					      10, 500);
 78	if (ret) {
 79		dev_err(priv->dev, "access to LPTIM timed out\n");
 80		/* Disable LPTIMER */
 81		regmap_write(priv->reg, STM32_LPTIM_CR, 0);
 82		return ret;
 83	}
 84	/* Clear DIEROK and ARROK flags */
 85	regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_DIEROKCF_ARROKCF);
 86
 87	return 0;
 88}
 89
 90static void stm32_clkevent_lp_set_evt(struct stm32_lp_private *priv, unsigned long evt)
 91{
 92	/* disable LPTIMER to be able to write into IER register*/
 93	regmap_write(priv->reg, STM32_LPTIM_CR, 0);
 94	/* enable ARR interrupt */
 95	regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE);
 96	/* enable LPTIMER to be able to write into ARR register */
 97	regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE);
 98	/* set next event counter */
 99	regmap_write(priv->reg, STM32_LPTIM_ARR, evt);
100}
101
102static int stm32_clkevent_lp_set_timer(unsigned long evt,
103				       struct clock_event_device *clkevt,
104				       int is_periodic)
105{
106	struct stm32_lp_private *priv = to_priv(clkevt);
107	int ret;
108
109	if (priv->version == STM32_LPTIM_VERR_23) {
110		ret = stm32mp25_clkevent_lp_set_evt(priv, evt);
111		if (ret)
112			return ret;
113	} else {
114		stm32_clkevent_lp_set_evt(priv, evt);
115	}
116
117	/* start counter */
118	if (is_periodic)
119		regmap_write(priv->reg, STM32_LPTIM_CR,
120			     STM32_LPTIM_CNTSTRT | STM32_LPTIM_ENABLE);
121	else
122		regmap_write(priv->reg, STM32_LPTIM_CR,
123			     STM32_LPTIM_SNGSTRT | STM32_LPTIM_ENABLE);
124
125	return 0;
126}
127
128static int stm32_clkevent_lp_set_next_event(unsigned long evt,
129					    struct clock_event_device *clkevt)
130{
131	return stm32_clkevent_lp_set_timer(evt, clkevt,
132					   clockevent_state_periodic(clkevt));
133}
134
135static int stm32_clkevent_lp_set_periodic(struct clock_event_device *clkevt)
136{
137	struct stm32_lp_private *priv = to_priv(clkevt);
138
139	return stm32_clkevent_lp_set_timer(priv->period, clkevt, true);
140}
141
142static int stm32_clkevent_lp_set_oneshot(struct clock_event_device *clkevt)
143{
144	struct stm32_lp_private *priv = to_priv(clkevt);
145
146	return stm32_clkevent_lp_set_timer(priv->period, clkevt, false);
147}
148
149static irqreturn_t stm32_clkevent_lp_irq_handler(int irq, void *dev_id)
150{
151	struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
152	struct stm32_lp_private *priv = to_priv(clkevt);
153
154	regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF);
155
156	if (clkevt->event_handler)
157		clkevt->event_handler(clkevt);
158
159	return IRQ_HANDLED;
160}
161
162static void stm32_clkevent_lp_set_prescaler(struct stm32_lp_private *priv,
163					    unsigned long *rate)
164{
165	int i;
166
167	for (i = 0; i <= STM32_LP_MAX_PSC; i++) {
168		if (DIV_ROUND_CLOSEST(*rate, 1 << i) < STM32_TARGET_CLKRATE)
169			break;
170	}
171
172	regmap_write(priv->reg, STM32_LPTIM_CFGR, i << CFGR_PSC_OFFSET);
173
174	/* Adjust rate and period given the prescaler value */
175	*rate = DIV_ROUND_CLOSEST(*rate, (1 << i));
176	priv->period = DIV_ROUND_UP(*rate, HZ);
177	priv->psc = i;
178}
179
180static void stm32_clkevent_lp_suspend(struct clock_event_device *clkevt)
181{
182	struct stm32_lp_private *priv = to_priv(clkevt);
183
184	stm32_clkevent_lp_shutdown(clkevt);
185
186	/* balance clk_prepare_enable() from the probe */
187	clk_disable_unprepare(priv->clk);
188}
189
190static void stm32_clkevent_lp_resume(struct clock_event_device *clkevt)
191{
192	struct stm32_lp_private *priv = to_priv(clkevt);
193
194	clk_prepare_enable(priv->clk);
195
196	/* restore prescaler */
197	regmap_write(priv->reg, STM32_LPTIM_CFGR, priv->psc << CFGR_PSC_OFFSET);
198}
199
200static void stm32_clkevent_lp_init(struct stm32_lp_private *priv,
201				  struct device_node *np, unsigned long rate)
202{
203	priv->clkevt.name = np->full_name;
204	priv->clkevt.cpumask = cpu_possible_mask;
205	priv->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
206				CLOCK_EVT_FEAT_ONESHOT;
207	priv->clkevt.set_state_shutdown = stm32_clkevent_lp_shutdown;
208	priv->clkevt.set_state_periodic = stm32_clkevent_lp_set_periodic;
209	priv->clkevt.set_state_oneshot = stm32_clkevent_lp_set_oneshot;
210	priv->clkevt.set_next_event = stm32_clkevent_lp_set_next_event;
211	priv->clkevt.rating = STM32_LP_RATING;
212	priv->clkevt.suspend = stm32_clkevent_lp_suspend;
213	priv->clkevt.resume = stm32_clkevent_lp_resume;
214	priv->clkevt.owner = THIS_MODULE;
215
216	clockevents_config_and_register(&priv->clkevt, rate, 0x1,
217					STM32_LPTIM_MAX_ARR);
218}
219
220static int stm32_clkevent_lp_probe(struct platform_device *pdev)
221{
222	struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
223	struct stm32_lp_private *priv;
224	unsigned long rate;
225	int ret, irq;
226
227	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
228	if (!priv)
229		return -ENOMEM;
230
231	priv->reg = ddata->regmap;
232	priv->version = ddata->version;
233	priv->clk = ddata->clk;
234	ret = clk_prepare_enable(priv->clk);
235	if (ret)
236		return -EINVAL;
237
238	rate = clk_get_rate(priv->clk);
239	if (!rate) {
240		ret = -EINVAL;
241		goto out_clk_disable;
242	}
243
244	irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
245	if (irq <= 0) {
246		ret = irq;
247		goto out_clk_disable;
248	}
249
250	if (of_property_read_bool(pdev->dev.parent->of_node, "wakeup-source")) {
251		device_set_wakeup_capable(&pdev->dev, true);
252
253		ret = dev_pm_set_wake_irq(&pdev->dev, irq);
254		if (ret)
255			goto out_clk_disable;
256	}
257
258	ret = devm_request_irq(&pdev->dev, irq, stm32_clkevent_lp_irq_handler,
259			       IRQF_TIMER, pdev->name, &priv->clkevt);
260	if (ret)
261		goto out_clk_disable;
262
263	stm32_clkevent_lp_set_prescaler(priv, &rate);
264
265	stm32_clkevent_lp_init(priv, pdev->dev.parent->of_node, rate);
266
267	priv->dev = &pdev->dev;
268
269	return 0;
270
271out_clk_disable:
272	clk_disable_unprepare(priv->clk);
273	return ret;
274}
275
276static const struct of_device_id stm32_clkevent_lp_of_match[] = {
277	{ .compatible = "st,stm32-lptimer-timer", },
278	{},
279};
280MODULE_DEVICE_TABLE(of, stm32_clkevent_lp_of_match);
281
282static struct platform_driver stm32_clkevent_lp_driver = {
283	.probe  = stm32_clkevent_lp_probe,
284	.driver	= {
285		.name = "stm32-lptimer-timer",
286		.of_match_table = stm32_clkevent_lp_of_match,
287		.suppress_bind_attrs = true,
288	},
289};
290module_platform_driver(stm32_clkevent_lp_driver);
291
292MODULE_DESCRIPTION("STMicroelectronics STM32 clockevent low power driver");