timer-nxp-pit.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
  4 * Copyright 2018,2021-2025 NXP
  5 */
  6#include <linux/interrupt.h>
  7#include <linux/clockchips.h>
  8#include <linux/cpuhotplug.h>
  9#include <linux/clk.h>
 10#include <linux/of_address.h>
 11#include <linux/of_irq.h>
 12#include <linux/sched_clock.h>
 13#include <linux/platform_device.h>
 14
 15/*
 16 * Each pit takes 0x10 Bytes register space
 17 */
 18#define PIT0_OFFSET	0x100
 19#define PIT_CH(n)       (PIT0_OFFSET + 0x10 * (n))
 20
 21#define PITMCR(__base)	(__base)
 22
 23#define PITMCR_FRZ	BIT(0)
 24#define PITMCR_MDIS	BIT(1)
 25
 26#define PITLDVAL(__base)	(__base)
 27#define PITTCTRL(__base)	((__base) + 0x08)
 28
 29#define PITCVAL_OFFSET	0x04
 30#define PITCVAL(__base)	((__base) + 0x04)
 31
 32#define PITTCTRL_TEN			BIT(0)
 33#define PITTCTRL_TIE			BIT(1)
 34
 35#define PITTFLG(__base)	((__base) + 0x0c)
 36
 37#define PITTFLG_TIF			BIT(0)
 38
 39struct pit_timer {
 40	void __iomem *clksrc_base;
 41	void __iomem *clkevt_base;
 42	struct clock_event_device ced;
 43	struct clocksource cs;
 44	int rate;
 45};
 46
 47struct pit_timer_data {
 48	int max_pit_instances;
 49};
 50
 51static DEFINE_PER_CPU(struct pit_timer *, pit_timers);
 52
 53/*
 54 * Global structure for multiple PITs initialization
 55 */
 56static int pit_instances;
 57static int max_pit_instances = 1;
 58
 59static void __iomem *sched_clock_base;
 60
 61static inline struct pit_timer *ced_to_pit(struct clock_event_device *ced)
 62{
 63	return container_of(ced, struct pit_timer, ced);
 64}
 65
 66static inline struct pit_timer *cs_to_pit(struct clocksource *cs)
 67{
 68	return container_of(cs, struct pit_timer, cs);
 69}
 70
 71static inline void pit_module_enable(void __iomem *base)
 72{
 73	writel(0, PITMCR(base));
 74}
 75
 76static inline void pit_module_disable(void __iomem *base)
 77{
 78	writel(PITMCR_MDIS, PITMCR(base));
 79}
 80
 81static inline void pit_timer_enable(void __iomem *base, bool tie)
 82{
 83	u32 val = PITTCTRL_TEN | (tie ? PITTCTRL_TIE : 0);
 84
 85	writel(val, PITTCTRL(base));
 86}
 87
 88static inline void pit_timer_disable(void __iomem *base)
 89{
 90	writel(0, PITTCTRL(base));
 91}
 92
 93static inline void pit_timer_set_counter(void __iomem *base, unsigned int cnt)
 94{
 95	writel(cnt, PITLDVAL(base));
 96}
 97
 98static inline void pit_timer_irqack(struct pit_timer *pit)
 99{
100	writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base));
101}
102
103static u64 notrace pit_read_sched_clock(void)
104{
105	return ~readl(sched_clock_base);
106}
107
108static u64 pit_timer_clocksource_read(struct clocksource *cs)
109{
110	struct pit_timer *pit = cs_to_pit(cs);
111
112	return (u64)~readl(PITCVAL(pit->clksrc_base));
113}
114
115static int pit_clocksource_init(struct pit_timer *pit, const char *name,
116				void __iomem *base, unsigned long rate)
117{
118	/*
119	 * The channels 0 and 1 can be chained to build a 64-bit
120	 * timer. Let's use the channel 2 as a clocksource and leave
121	 * the channels 0 and 1 unused for anyone else who needs them
122	 */
123	pit->clksrc_base = base + PIT_CH(2);
124	pit->cs.name = name;
125	pit->cs.rating = 300;
126	pit->cs.read = pit_timer_clocksource_read;
127	pit->cs.mask = CLOCKSOURCE_MASK(32);
128	pit->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
129
130	/* set the max load value and start the clock source counter */
131	pit_timer_disable(pit->clksrc_base);
132	pit_timer_set_counter(pit->clksrc_base, ~0);
133	pit_timer_enable(pit->clksrc_base, 0);
134
135	sched_clock_base = pit->clksrc_base + PITCVAL_OFFSET;
136	sched_clock_register(pit_read_sched_clock, 32, rate);
137
138	return clocksource_register_hz(&pit->cs, rate);
139}
140
141static int pit_set_next_event(unsigned long delta, struct clock_event_device *ced)
142{
143	struct pit_timer *pit = ced_to_pit(ced);
144
145	/*
146	 * set a new value to PITLDVAL register will not restart the timer,
147	 * to abort the current cycle and start a timer period with the new
148	 * value, the timer must be disabled and enabled again.
149	 * and the PITLAVAL should be set to delta minus one according to pit
150	 * hardware requirement.
151	 */
152	pit_timer_disable(pit->clkevt_base);
153	pit_timer_set_counter(pit->clkevt_base, delta - 1);
154	pit_timer_enable(pit->clkevt_base, true);
155
156	return 0;
157}
158
159static int pit_shutdown(struct clock_event_device *ced)
160{
161	struct pit_timer *pit = ced_to_pit(ced);
162
163	pit_timer_disable(pit->clkevt_base);
164
165	return 0;
166}
167
168static int pit_set_periodic(struct clock_event_device *ced)
169{
170	struct pit_timer *pit = ced_to_pit(ced);
171
172	pit_set_next_event(pit->rate / HZ, ced);
173
174	return 0;
175}
176
177static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
178{
179	struct clock_event_device *ced = dev_id;
180	struct pit_timer *pit = ced_to_pit(ced);
181
182	pit_timer_irqack(pit);
183
184	/*
185	 * pit hardware doesn't support oneshot, it will generate an interrupt
186	 * and reload the counter value from PITLDVAL when PITCVAL reach zero,
187	 * and start the counter again. So software need to disable the timer
188	 * to stop the counter loop in ONESHOT mode.
189	 */
190	if (likely(clockevent_state_oneshot(ced)))
191		pit_timer_disable(pit->clkevt_base);
192
193	ced->event_handler(ced);
194
195	return IRQ_HANDLED;
196}
197
198static int pit_clockevent_per_cpu_init(struct pit_timer *pit, const char *name,
199				       void __iomem *base, unsigned long rate,
200				       int irq, unsigned int cpu)
201{
202	int ret;
203
204	/*
205	 * The channels 0 and 1 can be chained to build a 64-bit
206	 * timer. Let's use the channel 3 as a clockevent and leave
207	 * the channels 0 and 1 unused for anyone else who needs them
208	 */
209	pit->clkevt_base = base + PIT_CH(3);
210	pit->rate = rate;
211
212	pit_timer_disable(pit->clkevt_base);
213
214	pit_timer_irqack(pit);
215
216	ret = request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_NOBALANCING,
217			  name, &pit->ced);
218	if (ret)
219		return ret;
220
221	pit->ced.cpumask = cpumask_of(cpu);
222	pit->ced.irq = irq;
223
224	pit->ced.name = name;
225	pit->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
226	pit->ced.set_state_shutdown = pit_shutdown;
227	pit->ced.set_state_periodic = pit_set_periodic;
228	pit->ced.set_next_event	= pit_set_next_event;
229	pit->ced.rating	= 300;
230
231	per_cpu(pit_timers, cpu) = pit;
232
233	return 0;
234}
235
236static void pit_clockevent_per_cpu_exit(struct pit_timer *pit, unsigned int cpu)
237{
238	pit_timer_disable(pit->clkevt_base);
239	free_irq(pit->ced.irq, &pit->ced);
240	per_cpu(pit_timers, cpu) = NULL;
241}
242
243static int pit_clockevent_starting_cpu(unsigned int cpu)
244{
245	struct pit_timer *pit = per_cpu(pit_timers, cpu);
246	int ret;
247
248	if (!pit)
249		return 0;
250
251	ret = irq_force_affinity(pit->ced.irq, cpumask_of(cpu));
252	if (ret) {
253		pit_clockevent_per_cpu_exit(pit, cpu);
254		return ret;
255	}
256
257	/*
258	 * The value for the LDVAL register trigger is calculated as:
259	 * LDVAL trigger = (period / clock period) - 1
260	 * The pit is a 32-bit down count timer, when the counter value
261	 * reaches 0, it will generate an interrupt, thus the minimal
262	 * LDVAL trigger value is 1. And then the min_delta is
263	 * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
264	 */
265	clockevents_config_and_register(&pit->ced, pit->rate, 2, 0xffffffff);
266
267	return 0;
268}
269
270static int pit_timer_init(struct device_node *np)
271{
272	struct pit_timer *pit;
273	struct clk *pit_clk;
274	void __iomem *timer_base;
275	const char *name = of_node_full_name(np);
276	unsigned long clk_rate;
277	int irq, ret;
278
279	pit = kzalloc(sizeof(*pit), GFP_KERNEL);
280	if (!pit)
281		return -ENOMEM;
282
283	ret = -ENXIO;
284	timer_base = of_iomap(np, 0);
285	if (!timer_base) {
286		pr_err("Failed to iomap\n");
287		goto out_kfree;
288	}
289
290	ret = -EINVAL;
291	irq = irq_of_parse_and_map(np, 0);
292	if (irq <= 0) {
293		pr_err("Failed to irq_of_parse_and_map\n");
294		goto out_iounmap;
295	}
296
297	pit_clk = of_clk_get(np, 0);
298	if (IS_ERR(pit_clk)) {
299		ret = PTR_ERR(pit_clk);
300		goto out_irq_dispose_mapping;
301	}
302
303	ret = clk_prepare_enable(pit_clk);
304	if (ret)
305		goto out_clk_put;
306
307	clk_rate = clk_get_rate(pit_clk);
308
309	pit_module_disable(timer_base);
310
311	ret = pit_clocksource_init(pit, name, timer_base, clk_rate);
312	if (ret) {
313		pr_err("Failed to initialize clocksource '%pOF'\n", np);
314		goto out_pit_module_disable;
315	}
316
317	ret = pit_clockevent_per_cpu_init(pit, name, timer_base, clk_rate, irq, pit_instances);
318	if (ret) {
319		pr_err("Failed to initialize clockevent '%pOF'\n", np);
320		goto out_pit_clocksource_unregister;
321	}
322
323	/* enable the pit module */
324	pit_module_enable(timer_base);
325
326	pit_instances++;
327
328	if (pit_instances == max_pit_instances) {
329		ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "PIT timer:starting",
330					pit_clockevent_starting_cpu, NULL);
331		if (ret < 0)
332			goto out_pit_clocksource_unregister;
333	}
334
335	return 0;
336
337out_pit_clocksource_unregister:
338	clocksource_unregister(&pit->cs);
339out_pit_module_disable:
340	pit_module_disable(timer_base);
341	clk_disable_unprepare(pit_clk);
342out_clk_put:
343	clk_put(pit_clk);
344out_irq_dispose_mapping:
345	irq_dispose_mapping(irq);
346out_iounmap:
347	iounmap(timer_base);
348out_kfree:
349	kfree(pit);
350
351	return ret;
352}
353
354static int pit_timer_probe(struct platform_device *pdev)
355{
356	const struct pit_timer_data *pit_timer_data;
357
358	pit_timer_data = of_device_get_match_data(&pdev->dev);
359	if (pit_timer_data)
360		max_pit_instances = pit_timer_data->max_pit_instances;
361
362	return pit_timer_init(pdev->dev.of_node);
363}
364
365static struct pit_timer_data s32g2_data = { .max_pit_instances = 2 };
366
367static const struct of_device_id pit_timer_of_match[] = {
368	{ .compatible = "nxp,s32g2-pit", .data = &s32g2_data },
369	{ }
370};
371MODULE_DEVICE_TABLE(of, pit_timer_of_match);
372
373static struct platform_driver nxp_pit_driver = {
374	.driver = {
375		.name = "nxp-pit",
376		.of_match_table = pit_timer_of_match,
377		.suppress_bind_attrs = true,
378	},
379	.probe = pit_timer_probe,
380};
381builtin_platform_driver(nxp_pit_driver);
382
383TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);