arm_global_timer.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * drivers/clocksource/arm_global_timer.c
  4 *
  5 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
  6 * Author: Stuart Menefy <stuart.menefy@st.com>
  7 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
  8 */
  9
 10#include <linux/init.h>
 11#include <linux/interrupt.h>
 12#include <linux/bitfield.h>
 13#include <linux/clocksource.h>
 14#include <linux/clockchips.h>
 15#include <linux/cpu.h>
 16#include <linux/clk.h>
 17#include <linux/delay.h>
 18#include <linux/err.h>
 19#include <linux/io.h>
 20#include <linux/of.h>
 21#include <linux/of_irq.h>
 22#include <linux/of_address.h>
 23#include <linux/sched_clock.h>
 24
 25#include <asm/cputype.h>
 26
 27#define GT_COUNTER0	0x00
 28#define GT_COUNTER1	0x04
 29
 30#define GT_CONTROL	0x08
 31#define GT_CONTROL_TIMER_ENABLE		BIT(0)  /* this bit is NOT banked */
 32#define GT_CONTROL_COMP_ENABLE		BIT(1)	/* banked */
 33#define GT_CONTROL_IRQ_ENABLE		BIT(2)	/* banked */
 34#define GT_CONTROL_AUTO_INC		BIT(3)	/* banked */
 35#define GT_CONTROL_PRESCALER_MASK	GENMASK(15, 8)
 36
 37#define GT_INT_STATUS	0x0c
 38#define GT_INT_STATUS_EVENT_FLAG	BIT(0)
 39
 40#define GT_COMP0	0x10
 41#define GT_COMP1	0x14
 42#define GT_AUTO_INC	0x18
 43
 44#define MAX_F_ERR 50
 45/*
 46 * We are expecting to be clocked by the ARM peripheral clock.
 47 *
 48 * Note: it is assumed we are using a prescaler value of zero, so this is
 49 * the units for all operations.
 50 */
 51static void __iomem *gt_base;
 52static struct notifier_block gt_clk_rate_change_nb;
 53static u32 gt_psv_new, gt_psv_bck;
 54static unsigned long gt_target_rate;
 55static int gt_ppi;
 56static struct clock_event_device __percpu *gt_evt;
 57
 58/*
 59 * To get the value from the Global Timer Counter register proceed as follows:
 60 * 1. Read the upper 32-bit timer counter register
 61 * 2. Read the lower 32-bit timer counter register
 62 * 3. Read the upper 32-bit timer counter register again. If the value is
 63 *  different to the 32-bit upper value read previously, go back to step 2.
 64 *  Otherwise the 64-bit timer counter value is correct.
 65 */
 66static u64 notrace _gt_counter_read(void)
 67{
 68	u64 counter;
 69	u32 lower;
 70	u32 upper, old_upper;
 71
 72	upper = readl_relaxed(gt_base + GT_COUNTER1);
 73	do {
 74		old_upper = upper;
 75		lower = readl_relaxed(gt_base + GT_COUNTER0);
 76		upper = readl_relaxed(gt_base + GT_COUNTER1);
 77	} while (upper != old_upper);
 78
 79	counter = upper;
 80	counter <<= 32;
 81	counter |= lower;
 82	return counter;
 83}
 84
 85static u64 gt_counter_read(void)
 86{
 87	return _gt_counter_read();
 88}
 89
 90/*
 91 * To ensure that updates to comparator value register do not set the
 92 * Interrupt Status Register proceed as follows:
 93 * 1. Clear the Comp Enable bit in the Timer Control Register.
 94 * 2. Write the lower 32-bit Comparator Value Register.
 95 * 3. Write the upper 32-bit Comparator Value Register.
 96 * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
 97 */
 98static void gt_compare_set(unsigned long delta, int periodic)
 99{
100	u64 counter = gt_counter_read();
101	unsigned long ctrl;
102
103	counter += delta;
104	ctrl = readl(gt_base + GT_CONTROL);
105	ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
106		  GT_CONTROL_AUTO_INC);
107	ctrl |= GT_CONTROL_TIMER_ENABLE;
108	writel_relaxed(ctrl, gt_base + GT_CONTROL);
109	writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
110	writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
111
112	if (periodic) {
113		writel_relaxed(delta, gt_base + GT_AUTO_INC);
114		ctrl |= GT_CONTROL_AUTO_INC;
115	}
116
117	ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
118	writel_relaxed(ctrl, gt_base + GT_CONTROL);
119}
120
121static int gt_clockevent_shutdown(struct clock_event_device *evt)
122{
123	unsigned long ctrl;
124
125	ctrl = readl(gt_base + GT_CONTROL);
126	ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
127		  GT_CONTROL_AUTO_INC);
128	writel(ctrl, gt_base + GT_CONTROL);
129	return 0;
130}
131
132static int gt_clockevent_set_periodic(struct clock_event_device *evt)
133{
134	gt_compare_set(DIV_ROUND_CLOSEST(gt_target_rate, HZ), 1);
135	return 0;
136}
137
138static int gt_clockevent_set_next_event(unsigned long evt,
139					struct clock_event_device *unused)
140{
141	gt_compare_set(evt, 0);
142	return 0;
143}
144
145static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
146{
147	struct clock_event_device *evt = dev_id;
148
149	if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
150				GT_INT_STATUS_EVENT_FLAG))
151		return IRQ_NONE;
152
153	/**
154	 * ERRATA 740657( Global Timer can send 2 interrupts for
155	 * the same event in single-shot mode)
156	 * Workaround:
157	 *	Either disable single-shot mode.
158	 *	Or
159	 *	Modify the Interrupt Handler to avoid the
160	 *	offending sequence. This is achieved by clearing
161	 *	the Global Timer flag _after_ having incremented
162	 *	the Comparator register	value to a higher value.
163	 */
164	if (clockevent_state_oneshot(evt))
165		gt_compare_set(ULONG_MAX, 0);
166
167	writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
168	evt->event_handler(evt);
169
170	return IRQ_HANDLED;
171}
172
173static int gt_starting_cpu(unsigned int cpu)
174{
175	struct clock_event_device *clk = this_cpu_ptr(gt_evt);
176
177	clk->name = "arm_global_timer";
178	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
179		CLOCK_EVT_FEAT_PERCPU;
180	clk->set_state_shutdown = gt_clockevent_shutdown;
181	clk->set_state_periodic = gt_clockevent_set_periodic;
182	clk->set_state_oneshot = gt_clockevent_shutdown;
183	clk->set_state_oneshot_stopped = gt_clockevent_shutdown;
184	clk->set_next_event = gt_clockevent_set_next_event;
185	clk->cpumask = cpumask_of(cpu);
186	clk->rating = 300;
187	clk->irq = gt_ppi;
188	clockevents_config_and_register(clk, gt_target_rate,
189					1, 0xffffffff);
190	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
191	return 0;
192}
193
194static int gt_dying_cpu(unsigned int cpu)
195{
196	struct clock_event_device *clk = this_cpu_ptr(gt_evt);
197
198	disable_percpu_irq(clk->irq);
199	return 0;
200}
201
202static u64 gt_clocksource_read(struct clocksource *cs)
203{
204	return gt_counter_read();
205}
206
207static void gt_resume(struct clocksource *cs)
208{
209	unsigned long ctrl;
210
211	ctrl = readl(gt_base + GT_CONTROL);
212	if (!(ctrl & GT_CONTROL_TIMER_ENABLE))
213		/* re-enable timer on resume */
214		writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
215}
216
217static struct clocksource gt_clocksource = {
218	.name	= "arm_global_timer",
219	.rating	= 300,
220	.read	= gt_clocksource_read,
221	.mask	= CLOCKSOURCE_MASK(64),
222	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
223	.resume = gt_resume,
224};
225
226#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
227static u64 notrace gt_sched_clock_read(void)
228{
229	return _gt_counter_read();
230}
231#endif
232
233static unsigned long gt_read_long(void)
234{
235	return readl_relaxed(gt_base + GT_COUNTER0);
236}
237
238static struct delay_timer gt_delay_timer = {
239	.read_current_timer = gt_read_long,
240};
241
242static void gt_write_presc(u32 psv)
243{
244	u32 reg;
245
246	reg = readl(gt_base + GT_CONTROL);
247	reg &= ~GT_CONTROL_PRESCALER_MASK;
248	reg |= FIELD_PREP(GT_CONTROL_PRESCALER_MASK, psv);
249	writel(reg, gt_base + GT_CONTROL);
250}
251
252static u32 gt_read_presc(void)
253{
254	u32 reg;
255
256	reg = readl(gt_base + GT_CONTROL);
257	return FIELD_GET(GT_CONTROL_PRESCALER_MASK, reg);
258}
259
260static void __init gt_delay_timer_init(void)
261{
262	gt_delay_timer.freq = gt_target_rate;
263	register_current_timer_delay(&gt_delay_timer);
264}
265
266static int __init gt_clocksource_init(unsigned int psv)
267{
268	writel(0, gt_base + GT_CONTROL);
269	writel(0, gt_base + GT_COUNTER0);
270	writel(0, gt_base + GT_COUNTER1);
271	/* set prescaler and enable timer on all the cores */
272	writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK, psv - 1) |
273	       GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
274
275#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
276	sched_clock_register(gt_sched_clock_read, 64, gt_target_rate);
277#endif
278	return clocksource_register_hz(&gt_clocksource, gt_target_rate);
279}
280
281static int gt_clk_rate_change_cb(struct notifier_block *nb,
282				 unsigned long event, void *data)
283{
284	struct clk_notifier_data *ndata = data;
285
286	switch (event) {
287	case PRE_RATE_CHANGE:
288	{
289		unsigned long psv;
290
291		psv = DIV_ROUND_CLOSEST(ndata->new_rate, gt_target_rate);
292		if (!psv ||
293		    abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR)
294			return NOTIFY_BAD;
295
296		psv--;
297
298		/* prescaler within legal range? */
299		if (!FIELD_FIT(GT_CONTROL_PRESCALER_MASK, psv))
300			return NOTIFY_BAD;
301
302		/*
303		 * store timer clock ctrl register so we can restore it in case
304		 * of an abort.
305		 */
306		gt_psv_bck = gt_read_presc();
307		gt_psv_new = psv;
308		/* scale down: adjust divider in post-change notification */
309		if (ndata->new_rate < ndata->old_rate)
310			return NOTIFY_DONE;
311
312		/* scale up: adjust divider now - before frequency change */
313		gt_write_presc(psv);
314		break;
315	}
316	case POST_RATE_CHANGE:
317		/* scale up: pre-change notification did the adjustment */
318		if (ndata->new_rate > ndata->old_rate)
319			return NOTIFY_OK;
320
321		/* scale down: adjust divider now - after frequency change */
322		gt_write_presc(gt_psv_new);
323		break;
324
325	case ABORT_RATE_CHANGE:
326		/* we have to undo the adjustment in case we scale up */
327		if (ndata->new_rate < ndata->old_rate)
328			return NOTIFY_OK;
329
330		/* restore original register value */
331		gt_write_presc(gt_psv_bck);
332		break;
333	default:
334		return NOTIFY_DONE;
335	}
336
337	return NOTIFY_DONE;
338}
339
340struct gt_prescaler_config {
341	const char *compatible;
342	unsigned long prescaler;
343};
344
345static const struct gt_prescaler_config gt_prescaler_configs[] = {
346	/*
347	 * On am43 the global timer clock is a child of the clock used for CPU
348	 * OPPs, so the initial prescaler has to be compatible with all OPPs
349	 * which are 300, 600, 720, 800 and 1000 with a fixed divider of 2, this
350	 * gives us a GCD of 10. Initial frequency is 1000, so the prescaler is
351	 * 50.
352	 */
353	{ .compatible = "ti,am43", .prescaler = 50 },
354	{ .compatible = "xlnx,zynq-7000", .prescaler = 2 },
355	{ .compatible = NULL }
356};
357
358static unsigned long gt_get_initial_prescaler_value(struct device_node *np)
359{
360	const struct gt_prescaler_config *config;
361
362	if (CONFIG_ARM_GT_INITIAL_PRESCALER_VAL != 0)
363		return CONFIG_ARM_GT_INITIAL_PRESCALER_VAL;
364
365	for (config = gt_prescaler_configs; config->compatible; config++) {
366		if (of_machine_is_compatible(config->compatible))
367			return config->prescaler;
368	}
369
370	return 1;
371}
372
373static int __init global_timer_of_register(struct device_node *np)
374{
375	struct clk *gt_clk;
376	static unsigned long gt_clk_rate;
377	int err;
378	unsigned long psv;
379
380	/*
381	 * In A9 r2p0 the comparators for each processor with the global timer
382	 * fire when the timer value is greater than or equal to. In previous
383	 * revisions the comparators fired when the timer value was equal to.
384	 */
385	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
386	    && (read_cpuid_id() & 0xf0000f) < 0x200000) {
387		pr_warn("global-timer: non support for this cpu version.\n");
388		return -ENOSYS;
389	}
390
391	gt_ppi = irq_of_parse_and_map(np, 0);
392	if (!gt_ppi) {
393		pr_warn("global-timer: unable to parse irq\n");
394		return -EINVAL;
395	}
396
397	gt_base = of_iomap(np, 0);
398	if (!gt_base) {
399		pr_warn("global-timer: invalid base address\n");
400		return -ENXIO;
401	}
402
403	gt_clk = of_clk_get(np, 0);
404	if (!IS_ERR(gt_clk)) {
405		err = clk_prepare_enable(gt_clk);
406		if (err)
407			goto out_unmap;
408	} else {
409		pr_warn("global-timer: clk not found\n");
410		err = -EINVAL;
411		goto out_unmap;
412	}
413
414	psv = gt_get_initial_prescaler_value(np);
415	gt_clk_rate = clk_get_rate(gt_clk);
416	gt_target_rate = gt_clk_rate / psv;
417	gt_clk_rate_change_nb.notifier_call =
418		gt_clk_rate_change_cb;
419	err = clk_notifier_register(gt_clk, &gt_clk_rate_change_nb);
420	if (err) {
421		pr_warn("Unable to register clock notifier\n");
422		goto out_clk;
423	}
424
425	gt_evt = alloc_percpu(struct clock_event_device);
426	if (!gt_evt) {
427		pr_warn("global-timer: can't allocate memory\n");
428		err = -ENOMEM;
429		goto out_clk_nb;
430	}
431
432	err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
433				 "gt", gt_evt);
434	if (err) {
435		pr_warn("global-timer: can't register interrupt %d (%d)\n",
436			gt_ppi, err);
437		goto out_free;
438	}
439
440	/* Register and immediately configure the timer on the boot CPU */
441	err = gt_clocksource_init(psv);
442	if (err)
443		goto out_irq;
444
445	err = cpuhp_setup_state(CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
446				"clockevents/arm/global_timer:starting",
447				gt_starting_cpu, gt_dying_cpu);
448	if (err)
449		goto out_irq;
450
451	gt_delay_timer_init();
452
453	return 0;
454
455out_irq:
456	free_percpu_irq(gt_ppi, gt_evt);
457out_free:
458	free_percpu(gt_evt);
459out_clk_nb:
460	clk_notifier_unregister(gt_clk, &gt_clk_rate_change_nb);
461out_clk:
462	clk_disable_unprepare(gt_clk);
463out_unmap:
464	iounmap(gt_base);
465	WARN(err, "ARM Global timer register failed (%d)\n", err);
466
467	return err;
468}
469
470/* Only tested on r2p2 and r3p0  */
471TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
472			global_timer_of_register);