pll-tmpv770x.c

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Toshiba Visconti PLL controller
 4 *
 5 * Copyright (c) 2021 TOSHIBA CORPORATION
 6 * Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
 7 *
 8 * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
 9 */
10
11#include <linux/clk-provider.h>
12#include <linux/of_address.h>
13#include <linux/slab.h>
14
15#include <dt-bindings/clock/toshiba,tmpv770x.h>
16
17#include "pll.h"
18
19/* Must be equal to the last pll ID increased by one */
20#define PLLS_NR	(TMPV770X_PLL_PIIMGERPLL + 1)
21
22static DEFINE_SPINLOCK(tmpv770x_pll_lock);
23
24static const struct visconti_pll_rate_table pipll0_rates[] __initconst = {
25	VISCONTI_PLL_RATE(840000000, 0x1, 0x0, 0x1, 0x54, 0x000000, 0x2, 0x1),
26	VISCONTI_PLL_RATE(780000000, 0x1, 0x0, 0x1, 0x4e, 0x000000, 0x2, 0x1),
27	VISCONTI_PLL_RATE(600000000, 0x1, 0x0, 0x1, 0x3c, 0x000000, 0x2, 0x1),
28	{ /* sentinel */ },
29};
30
31static const struct visconti_pll_rate_table piddrcpll_rates[] __initconst = {
32	VISCONTI_PLL_RATE(780000000, 0x1, 0x0, 0x1, 0x4e, 0x000000, 0x2, 0x1),
33	VISCONTI_PLL_RATE(760000000, 0x1, 0x0, 0x1, 0x4c, 0x000000, 0x2, 0x1),
34	{ /* sentinel */ },
35};
36
37static const struct visconti_pll_rate_table pivoifpll_rates[] __initconst = {
38	VISCONTI_PLL_RATE(165000000, 0x1, 0x0, 0x1, 0x42, 0x000000, 0x4, 0x2),
39	VISCONTI_PLL_RATE(148500000, 0x1, 0x1, 0x1, 0x3b, 0x666666, 0x4, 0x2),
40	VISCONTI_PLL_RATE(96000000, 0x1, 0x0, 0x1, 0x30, 0x000000, 0x5, 0x2),
41	VISCONTI_PLL_RATE(74250000, 0x1, 0x1, 0x1, 0x3b, 0x666666, 0x4, 0x4),
42	VISCONTI_PLL_RATE(54000000, 0x1, 0x0, 0x1, 0x36, 0x000000, 0x5, 0x4),
43	VISCONTI_PLL_RATE(48000000, 0x1, 0x0, 0x1, 0x30, 0x000000, 0x5, 0x4),
44	VISCONTI_PLL_RATE(35750000, 0x1, 0x1, 0x1, 0x32, 0x0ccccc, 0x7, 0x4),
45	{ /* sentinel */ },
46};
47
48static const struct visconti_pll_rate_table piimgerpll_rates[] __initconst = {
49	VISCONTI_PLL_RATE(165000000, 0x1, 0x0, 0x1, 0x42, 0x000000, 0x4, 0x2),
50	VISCONTI_PLL_RATE(96000000, 0x1, 0x0, 0x1, 0x30, 0x000000, 0x5, 0x2),
51	VISCONTI_PLL_RATE(54000000, 0x1, 0x0, 0x1, 0x36, 0x000000, 0x5, 0x4),
52	VISCONTI_PLL_RATE(48000000, 0x1, 0x0, 0x1, 0x30, 0x000000, 0x5, 0x4),
53	{ /* sentinel */ },
54};
55
56static const struct visconti_pll_info pll_info[] __initconst = {
57	{ TMPV770X_PLL_PIPLL0, "pipll0", "osc2-clk", 0x0, pipll0_rates },
58	{ TMPV770X_PLL_PIDDRCPLL, "piddrcpll", "osc2-clk", 0x500, piddrcpll_rates },
59	{ TMPV770X_PLL_PIVOIFPLL, "pivoifpll", "osc2-clk", 0x600, pivoifpll_rates },
60	{ TMPV770X_PLL_PIIMGERPLL, "piimgerpll", "osc2-clk", 0x700, piimgerpll_rates },
61};
62
63static void __init tmpv770x_setup_plls(struct device_node *np)
64{
65	struct visconti_pll_provider *ctx;
66	void __iomem *reg_base;
67
68	reg_base = of_iomap(np, 0);
69	if (!reg_base)
70		return;
71
72	ctx = visconti_init_pll(np, reg_base, PLLS_NR);
73	if (IS_ERR(ctx)) {
74		iounmap(reg_base);
75		return;
76	}
77
78	ctx->clk_data.hws[TMPV770X_PLL_PIPLL1] =
79		clk_hw_register_fixed_rate(NULL, "pipll1", NULL, 0, 600000000);
80	ctx->clk_data.hws[TMPV770X_PLL_PIDNNPLL] =
81		clk_hw_register_fixed_rate(NULL, "pidnnpll", NULL, 0, 500000000);
82	ctx->clk_data.hws[TMPV770X_PLL_PIETHERPLL] =
83		clk_hw_register_fixed_rate(NULL, "pietherpll", NULL, 0, 500000000);
84
85	visconti_register_plls(ctx, pll_info, ARRAY_SIZE(pll_info), &tmpv770x_pll_lock);
86}
87
88CLK_OF_DECLARE(tmpv770x_plls, "toshiba,tmpv7708-pipllct", tmpv770x_setup_plls);