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clkc-tmpv770x.c
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linux-6.19.14/drivers/clk/visconti/clkc-tmpv770x.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Toshiba Visconti clock controller 4 * 5 * Copyright (c) 2021 TOSHIBA CORPORATION 6 * Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation 7 * 8 * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 9 */ 10 11#include <linux/clk-provider.h> 12#include <linux/platform_device.h> 13 14#include <dt-bindings/clock/toshiba,tmpv770x.h> 15#include <dt-bindings/reset/toshiba,tmpv770x.h> 16 17#include "clkc.h" 18#include "reset.h" 19 20/* Must be equal to the last clock/reset ID increased by one */ 21#define CLKS_NR (TMPV770X_CLK_VIIFBS1_PROC + 1) 22#define RESETS_NR (TMPV770X_RESET_VIIFBS1_L1ISP + 1) 23 24static DEFINE_SPINLOCK(tmpv770x_clk_lock); 25static DEFINE_SPINLOCK(tmpv770x_rst_lock); 26 27static const struct clk_parent_data clks_parent_data[] = { 28 { .fw_name = "pipll1", .name = "pipll1", }, 29}; 30 31static const struct clk_parent_data pietherplls_parent_data[] = { 32 { .fw_name = "pietherpll", .name = "pietherpll", }, 33}; 34 35static const struct clk_parent_data pidnnplls_parent_data[] = { 36 { .fw_name = "pidnnpll", .name = "pidnnpll", }, 37}; 38 39static const struct visconti_fixed_clk fixed_clk_tables[] = { 40 /* PLL1 */ 41 /* PICMPT0/1, PITSC, PIUWDT, PISWDT, PISBUS, PIPMU, PIGPMU, PITMU */ 42 /* PIEMM, PIMISC, PIGCOMM, PIDCOMM, PIMBUS, PIGPIO, PIPGM */ 43 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, }, 44 /* PISBUS */ 45 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, }, 46 /* PICOBUS_CLK */ 47 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, }, 48 /* PIDNNPLL */ 49 /* CONN_CLK, PIMBUS, PICRC0/1 */ 50 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, }, 51 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, }, 52 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, }, 53}; 54 55static const struct visconti_clk_gate_table pietherpll_clk_gate_tables[] = { 56 /* pietherpll */ 57 { TMPV770X_CLK_PIETHER_2P5M, "piether_2p5m", 58 pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data), 59 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200, 60 TMPV770X_RESET_PIETHER_2P5M, }, 61 { TMPV770X_CLK_PIETHER_25M, "piether_25m", 62 pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data), 63 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20, 64 TMPV770X_RESET_PIETHER_25M, }, 65 { TMPV770X_CLK_PIETHER_50M, "piether_50m", 66 pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data), 67 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10, 68 TMPV770X_RESET_PIETHER_50M, }, 69 { TMPV770X_CLK_PIETHER_125M, "piether_125m", 70 pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data), 71 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4, 72 TMPV770X_RESET_PIETHER_125M, }, 73}; 74 75static const struct visconti_clk_gate_table pidnnpll_clk_gate_tables[] = { 76 { TMPV770X_CLK_VIIFBS0, "viifbs0", 77 pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), 78 0, 0x58, 0x158, 1, 1, 79 NO_RESET, }, 80 { TMPV770X_CLK_VIIFBS0_PROC, "viifbs0_proc", 81 pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), 82 0, 0x58, 0x158, 18, 1, 83 NO_RESET, }, 84 { TMPV770X_CLK_VIIFBS0_L1ISP, "viifbs0_l1isp", 85 pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), 86 0, 0x58, 0x158, 17, 1, 87 NO_RESET, }, 88 { TMPV770X_CLK_VIIFBS0_L2ISP, "viifbs0_l2isp", 89 pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), 90 0, 0x58, 0x158, 16, 1, 91 NO_RESET, }, 92 { TMPV770X_CLK_VIIFBS1, "viifbs1", 93 pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), 94 0, 0x58, 0x158, 5, 1, 95 NO_RESET, }, 96 { TMPV770X_CLK_VIIFBS1_PROC, "viifbs1_proc", 97 pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), 98 0, 0x58, 0x158, 22, 1, 99 NO_RESET, }, 100 { TMPV770X_CLK_VIIFBS1_L1ISP, "viifbs1_l1isp", 101 pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), 102 0, 0x58, 0x158, 21, 1, 103 NO_RESET, }, 104 { TMPV770X_CLK_VIIFBS1_L2ISP, "viifbs1_l2isp", 105 pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data), 106 0, 0x58, 0x158, 20, 1, 107 NO_RESET, }, 108}; 109 110static const struct visconti_clk_gate_table clk_gate_tables[] = { 111 { TMPV770X_CLK_HOX, "hox", 112 clks_parent_data, ARRAY_SIZE(clks_parent_data), 113 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x4c, 0x14c, 0, 1, 114 TMPV770X_RESET_HOX, }, 115 { TMPV770X_CLK_PCIE_MSTR, "pcie_mstr", 116 clks_parent_data, ARRAY_SIZE(clks_parent_data), 117 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x38, 0x138, 0, 1, 118 TMPV770X_RESET_PCIE_MSTR, }, 119 { TMPV770X_CLK_PCIE_AUX, "pcie_aux", 120 clks_parent_data, ARRAY_SIZE(clks_parent_data), 121 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x38, 0x138, 1, 24, 122 TMPV770X_RESET_PCIE_AUX, }, 123 { TMPV770X_CLK_PIINTC, "piintc", 124 clks_parent_data, ARRAY_SIZE(clks_parent_data), 125 CLK_IGNORE_UNUSED, 0x8, 0x108, 0, 2, //FIX!! 126 TMPV770X_RESET_PIINTC,}, 127 { TMPV770X_CLK_PIETHER_BUS, "piether_bus", 128 clks_parent_data, ARRAY_SIZE(clks_parent_data), 129 0, 0x34, 0x134, 0, 2, 130 TMPV770X_RESET_PIETHER_BUS, }, /* BUS_CLK */ 131 { TMPV770X_CLK_PISPI0, "pispi0", 132 clks_parent_data, ARRAY_SIZE(clks_parent_data), 133 0, 0x28, 0x128, 0, 2, 134 TMPV770X_RESET_PISPI0, }, 135 { TMPV770X_CLK_PISPI1, "pispi1", 136 clks_parent_data, ARRAY_SIZE(clks_parent_data), 137 0, 0x28, 0x128, 1, 2, 138 TMPV770X_RESET_PISPI1, }, 139 { TMPV770X_CLK_PISPI2, "pispi2", 140 clks_parent_data, ARRAY_SIZE(clks_parent_data), 141 0, 0x28, 0x128, 2, 2, 142 TMPV770X_RESET_PISPI2, }, 143 { TMPV770X_CLK_PISPI3, "pispi3", 144 clks_parent_data, ARRAY_SIZE(clks_parent_data), 145 0, 0x28, 0x128, 3, 2, 146 TMPV770X_RESET_PISPI3,}, 147 { TMPV770X_CLK_PISPI4, "pispi4", 148 clks_parent_data, ARRAY_SIZE(clks_parent_data), 149 0, 0x28, 0x128, 4, 2, 150 TMPV770X_RESET_PISPI4, }, 151 { TMPV770X_CLK_PISPI5, "pispi5", 152 clks_parent_data, ARRAY_SIZE(clks_parent_data), 153 0, 0x28, 0x128, 5, 2, 154 TMPV770X_RESET_PISPI5}, 155 { TMPV770X_CLK_PISPI6, "pispi6", 156 clks_parent_data, ARRAY_SIZE(clks_parent_data), 157 0, 0x28, 0x128, 6, 2, 158 TMPV770X_RESET_PISPI6,}, 159 { TMPV770X_CLK_PIUART0, "piuart0", 160 clks_parent_data, ARRAY_SIZE(clks_parent_data), 161 //CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2c, 0x12c, 0, 4, 162 0, 0x2c, 0x12c, 0, 4, 163 TMPV770X_RESET_PIUART0,}, 164 { TMPV770X_CLK_PIUART1, "piuart1", 165 clks_parent_data, ARRAY_SIZE(clks_parent_data), 166 //CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2c, 0x12c, 1, 4, 167 0, 0x2c, 0x12c, 1, 4, 168 TMPV770X_RESET_PIUART1, }, 169 { TMPV770X_CLK_PIUART2, "piuart2", 170 clks_parent_data, ARRAY_SIZE(clks_parent_data), 171 0, 0x2c, 0x12c, 2, 4, 172 TMPV770X_RESET_PIUART2, }, 173 { TMPV770X_CLK_PIUART3, "piuart3", 174 clks_parent_data, ARRAY_SIZE(clks_parent_data), 175 0, 0x2c, 0x12c, 3, 4, 176 TMPV770X_RESET_PIUART3, }, 177 { TMPV770X_CLK_PII2C0, "pii2c0", 178 clks_parent_data, ARRAY_SIZE(clks_parent_data), 179 0, 0x30, 0x130, 0, 4, 180 TMPV770X_RESET_PII2C0, }, 181 { TMPV770X_CLK_PII2C1, "pii2c1", 182 clks_parent_data, ARRAY_SIZE(clks_parent_data), 183 0, 0x30, 0x130, 1, 4, 184 TMPV770X_RESET_PII2C1, }, 185 { TMPV770X_CLK_PII2C2, "pii2c2", 186 clks_parent_data, ARRAY_SIZE(clks_parent_data), 187 0, 0x30, 0x130, 2, 4, 188 TMPV770X_RESET_PII2C2, }, 189 { TMPV770X_CLK_PII2C3, "pii2c3", 190 clks_parent_data, ARRAY_SIZE(clks_parent_data), 191 0, 0x30, 0x130, 3, 4, 192 TMPV770X_RESET_PII2C3,}, 193 { TMPV770X_CLK_PII2C4, "pii2c4", 194 clks_parent_data, ARRAY_SIZE(clks_parent_data), 195 0, 0x30, 0x130, 4, 4, 196 TMPV770X_RESET_PII2C4, }, 197 { TMPV770X_CLK_PII2C5, "pii2c5", 198 clks_parent_data, ARRAY_SIZE(clks_parent_data), 199 0, 0x30, 0x130, 5, 4, 200 TMPV770X_RESET_PII2C5, }, 201 { TMPV770X_CLK_PII2C6, "pii2c6", 202 clks_parent_data, ARRAY_SIZE(clks_parent_data), 203 0, 0x30, 0x130, 6, 4, 204 TMPV770X_RESET_PII2C6, }, 205 { TMPV770X_CLK_PII2C7, "pii2c7", 206 clks_parent_data, ARRAY_SIZE(clks_parent_data), 207 0, 0x30, 0x130, 7, 4, 208 TMPV770X_RESET_PII2C7, }, 209 { TMPV770X_CLK_PII2C8, "pii2c8", 210 clks_parent_data, ARRAY_SIZE(clks_parent_data), 211 0, 0x30, 0x130, 8, 4, 212 TMPV770X_RESET_PII2C8, }, 213 /* PIPCMIF */ 214 { TMPV770X_CLK_PIPCMIF, "pipcmif", 215 clks_parent_data, ARRAY_SIZE(clks_parent_data), 216 0, 0x64, 0x164, 0, 4, 217 TMPV770X_RESET_PIPCMIF, }, 218 /* PISYSTEM */ 219 { TMPV770X_CLK_WRCK, "wrck", 220 clks_parent_data, ARRAY_SIZE(clks_parent_data), 221 0, 0x68, 0x168, 9, 32, 222 NO_RESET, }, 223 { TMPV770X_CLK_PICKMON, "pickmon", 224 clks_parent_data, ARRAY_SIZE(clks_parent_data), 225 0, 0x10, 0x110, 8, 4, 226 TMPV770X_RESET_PICKMON, }, 227 { TMPV770X_CLK_SBUSCLK, "sbusclk", 228 clks_parent_data, ARRAY_SIZE(clks_parent_data), 229 0, 0x14, 0x114, 0, 4, 230 TMPV770X_RESET_SBUSCLK, }, 231 { TMPV770X_CLK_VIIF0_CFGCLK, "csi2rx0cfg", 232 clks_parent_data, ARRAY_SIZE(clks_parent_data), 233 0, 0x58, 0x158, 0, 24, 234 NO_RESET, }, 235 { TMPV770X_CLK_VIIF0_APBCLK, "csi2rx0apb", 236 clks_parent_data, ARRAY_SIZE(clks_parent_data), 237 0, 0x58, 0x158, 2, 4, 238 NO_RESET, }, 239 { TMPV770X_CLK_VIIF1_CFGCLK, "csi2rx1cfg", 240 clks_parent_data, ARRAY_SIZE(clks_parent_data), 241 0, 0x58, 0x158, 4, 24, 242 NO_RESET, }, 243 { TMPV770X_CLK_VIIF1_APBCLK, "csi2rx1apb", 244 clks_parent_data, ARRAY_SIZE(clks_parent_data), 245 0, 0x58, 0x158, 6, 4, 246 NO_RESET, }, 247}; 248 249static const struct visconti_reset_data clk_reset_data[] = { 250 [TMPV770X_RESET_PIETHER_2P5M] = { 0x434, 0x534, 4, }, 251 [TMPV770X_RESET_PIETHER_25M] = { 0x434, 0x534, 5, }, 252 [TMPV770X_RESET_PIETHER_50M] = { 0x434, 0x534, 6, }, 253 [TMPV770X_RESET_PIETHER_125M] = { 0x434, 0x534, 7, }, 254 [TMPV770X_RESET_HOX] = { 0x44c, 0x54c, 0, }, 255 [TMPV770X_RESET_PCIE_MSTR] = { 0x438, 0x538, 0, }, 256 [TMPV770X_RESET_PCIE_AUX] = { 0x438, 0x538, 1, }, 257 [TMPV770X_RESET_PIINTC] = { 0x408, 0x508, 0, }, 258 [TMPV770X_RESET_PIETHER_BUS] = { 0x434, 0x534, 0, }, 259 [TMPV770X_RESET_PISPI0] = { 0x428, 0x528, 0, }, 260 [TMPV770X_RESET_PISPI1] = { 0x428, 0x528, 1, }, 261 [TMPV770X_RESET_PISPI2] = { 0x428, 0x528, 2, }, 262 [TMPV770X_RESET_PISPI3] = { 0x428, 0x528, 3, }, 263 [TMPV770X_RESET_PISPI4] = { 0x428, 0x528, 4, }, 264 [TMPV770X_RESET_PISPI5] = { 0x428, 0x528, 5, }, 265 [TMPV770X_RESET_PISPI6] = { 0x428, 0x528, 6, }, 266 [TMPV770X_RESET_PIUART0] = { 0x42c, 0x52c, 0, }, 267 [TMPV770X_RESET_PIUART1] = { 0x42c, 0x52c, 1, }, 268 [TMPV770X_RESET_PIUART2] = { 0x42c, 0x52c, 2, }, 269 [TMPV770X_RESET_PIUART3] = { 0x42c, 0x52c, 3, }, 270 [TMPV770X_RESET_PII2C0] = { 0x430, 0x530, 0, }, 271 [TMPV770X_RESET_PII2C1] = { 0x430, 0x530, 1, }, 272 [TMPV770X_RESET_PII2C2] = { 0x430, 0x530, 2, }, 273 [TMPV770X_RESET_PII2C3] = { 0x430, 0x530, 3, }, 274 [TMPV770X_RESET_PII2C4] = { 0x430, 0x530, 4, }, 275 [TMPV770X_RESET_PII2C5] = { 0x430, 0x530, 5, }, 276 [TMPV770X_RESET_PII2C6] = { 0x430, 0x530, 6, }, 277 [TMPV770X_RESET_PII2C7] = { 0x430, 0x530, 7, }, 278 [TMPV770X_RESET_PII2C8] = { 0x430, 0x530, 8, }, 279 [TMPV770X_RESET_PIPCMIF] = { 0x464, 0x564, 0, }, 280 [TMPV770X_RESET_PICKMON] = { 0x410, 0x510, 8, }, 281 [TMPV770X_RESET_SBUSCLK] = { 0x414, 0x514, 0, }, 282 [TMPV770X_RESET_VIIFBS0] = { 0x458, 0x558, 0, }, 283 [TMPV770X_RESET_VIIFBS0_APB] = { 0x458, 0x558, 1, }, 284 [TMPV770X_RESET_VIIFBS0_L2ISP] = { 0x458, 0x558, 16, }, 285 [TMPV770X_RESET_VIIFBS0_L1ISP] = { 0x458, 0x558, 17, }, 286 [TMPV770X_RESET_VIIFBS1] = { 0x458, 0x558, 4, }, 287 [TMPV770X_RESET_VIIFBS1_APB] = { 0x458, 0x558, 5, }, 288 [TMPV770X_RESET_VIIFBS1_L2ISP] = { 0x458, 0x558, 20, }, 289 [TMPV770X_RESET_VIIFBS1_L1ISP] = { 0x458, 0x558, 21, }, 290}; 291 292static int visconti_clk_probe(struct platform_device *pdev) 293{ 294 struct device_node *np = pdev->dev.of_node; 295 struct visconti_clk_provider *ctx; 296 struct device *dev = &pdev->dev; 297 struct regmap *regmap; 298 int ret, i; 299 300 regmap = syscon_node_to_regmap(np); 301 if (IS_ERR(regmap)) 302 return PTR_ERR(regmap); 303 304 ctx = visconti_init_clk(dev, regmap, CLKS_NR); 305 if (IS_ERR(ctx)) 306 return PTR_ERR(ctx); 307 308 ret = visconti_register_reset_controller(dev, regmap, clk_reset_data, 309 RESETS_NR, 310 &visconti_reset_ops, 311 &tmpv770x_rst_lock); 312 if (ret) { 313 dev_err(dev, "Failed to register reset controller: %d\n", ret); 314 return ret; 315 } 316 317 for (i = 0; i < (ARRAY_SIZE(fixed_clk_tables)); i++) 318 ctx->clk_data.hws[fixed_clk_tables[i].id] = 319 clk_hw_register_fixed_factor(NULL, 320 fixed_clk_tables[i].name, 321 fixed_clk_tables[i].parent, 322 fixed_clk_tables[i].flag, 323 fixed_clk_tables[i].mult, 324 fixed_clk_tables[i].div); 325 326 ret = visconti_clk_register_gates(ctx, clk_gate_tables, 327 ARRAY_SIZE(clk_gate_tables), clk_reset_data, 328 &tmpv770x_clk_lock); 329 if (ret) { 330 dev_err(dev, "Failed to register main clock gate: %d\n", ret); 331 return ret; 332 } 333 334 ret = visconti_clk_register_gates(ctx, pietherpll_clk_gate_tables, 335 ARRAY_SIZE(pietherpll_clk_gate_tables), 336 clk_reset_data, &tmpv770x_clk_lock); 337 if (ret) { 338 dev_err(dev, "Failed to register pietherpll clock gate: %d\n", ret); 339 return ret; 340 } 341 342 ret = visconti_clk_register_gates(ctx, pidnnpll_clk_gate_tables, 343 ARRAY_SIZE(pidnnpll_clk_gate_tables), 344 clk_reset_data, &tmpv770x_clk_lock); 345 if (ret) { 346 dev_err(dev, "Failed to register pidnnpll clock gate: %d\n", ret); 347 return ret; 348 } 349 350 return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &ctx->clk_data); 351} 352 353static const struct of_device_id visconti_clk_ids[] = { 354 { .compatible = "toshiba,tmpv7708-pismu", }, 355 { } 356}; 357 358static struct platform_driver visconti_clk_driver = { 359 .probe = visconti_clk_probe, 360 .driver = { 361 .name = "visconti-clk", 362 .of_match_table = visconti_clk_ids, 363 }, 364}; 365 366builtin_platform_driver(visconti_clk_driver);
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