clk-icst.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Driver for the ICST307 VCO clock found in the ARM Reference designs.
  4 * We wrap the custom interface from <asm/hardware/icst.h> into the generic
  5 * clock framework.
  6 *
  7 * Copyright (C) 2012-2015 Linus Walleij
  8 *
  9 * TODO: when all ARM reference designs are migrated to generic clocks, the
 10 * ICST clock code from the ARM tree should probably be merged into this
 11 * file.
 12 */
 13#include <linux/kernel.h>
 14#include <linux/slab.h>
 15#include <linux/export.h>
 16#include <linux/err.h>
 17#include <linux/clk-provider.h>
 18#include <linux/io.h>
 19#include <linux/regmap.h>
 20#include <linux/mfd/syscon.h>
 21
 22#include "icst.h"
 23#include "clk-icst.h"
 24
 25/* Magic unlocking token used on all Versatile boards */
 26#define VERSATILE_LOCK_VAL	0xA05F
 27
 28#define VERSATILE_AUX_OSC_BITS 0x7FFFF
 29#define INTEGRATOR_AP_CM_BITS 0xFF
 30#define INTEGRATOR_AP_SYS_BITS 0xFF
 31#define INTEGRATOR_CP_CM_CORE_BITS 0x7FF
 32#define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000
 33
 34#define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
 35
 36/**
 37 * struct clk_icst - ICST VCO clock wrapper
 38 * @hw: corresponding clock hardware entry
 39 * @map: register map
 40 * @vcoreg_off: VCO register address
 41 * @lockreg_off: VCO lock register address
 42 * @params: parameters for this ICST instance
 43 * @rate: current rate
 44 * @ctype: the type of control register for the ICST
 45 */
 46struct clk_icst {
 47	struct clk_hw hw;
 48	struct regmap *map;
 49	u32 vcoreg_off;
 50	u32 lockreg_off;
 51	struct icst_params *params;
 52	unsigned long rate;
 53	enum icst_control_type ctype;
 54};
 55
 56#define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
 57
 58/**
 59 * vco_get() - get ICST VCO settings from a certain ICST
 60 * @icst: the ICST clock to get
 61 * @vco: the VCO struct to return the value in
 62 */
 63static int vco_get(struct clk_icst *icst, struct icst_vco *vco)
 64{
 65	u32 val;
 66	int ret;
 67
 68	ret = regmap_read(icst->map, icst->vcoreg_off, &val);
 69	if (ret)
 70		return ret;
 71
 72	/*
 73	 * The Integrator/AP core clock can only access the low eight
 74	 * bits of the v PLL divider. Bit 8 is tied low and always zero,
 75	 * r is hardwired to 22 and output divider s is hardwired to 1
 76	 * (divide by 2) according to the document
 77	 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and
 78	 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14.
 79	 */
 80	if (icst->ctype == ICST_INTEGRATOR_AP_CM) {
 81		vco->v = val & INTEGRATOR_AP_CM_BITS;
 82		vco->r = 22;
 83		vco->s = 1;
 84		return 0;
 85	}
 86
 87	/*
 88	 * The Integrator/AP system clock on the base board can only
 89	 * access the low eight bits of the v PLL divider. Bit 8 is tied low
 90	 * and always zero, r is hardwired to 46, and the output divider is
 91	 * hardwired to 3 (divide by 4) according to the document
 92	 * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B,
 93	 * page 3-16.
 94	 */
 95	if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
 96		vco->v = val & INTEGRATOR_AP_SYS_BITS;
 97		vco->r = 46;
 98		vco->s = 3;
 99		return 0;
100	}
101
102	/*
103	 * The Integrator/AP PCI clock is using an odd pattern to create
104	 * the child clock, basically a single bit called DIVX/Y is used
105	 * to select between two different hardwired values: setting the
106	 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the
107	 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies
108	 * 33 or 25 MHz respectively.
109	 */
110	if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
111		bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ);
112
113		vco->v = divxy ? 17 : 14;
114		vco->r = divxy ? 22 : 14;
115		vco->s = 1;
116		return 0;
117	}
118
119	/*
120	 * The Integrator/CP core clock can access the low eight bits
121	 * of the v PLL divider. Bit 8 is tied low and always zero,
122	 * r is hardwired to 22 and the output divider s is accessible
123	 * in bits 8 thru 10 according to the document
124	 * "Integrator/CM940T, CM920T, CM740T, and CM720T User Guide"
125	 * ARM DUI 0157A, page 3-20 thru 3-23 and 4-10.
126	 */
127	if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
128		vco->v = val & 0xFF;
129		vco->r = 22;
130		vco->s = (val >> 8) & 7;
131		return 0;
132	}
133
134	if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
135		vco->v = (val >> 12) & 0xFF;
136		vco->r = 22;
137		vco->s = (val >> 20) & 7;
138		return 0;
139	}
140
141	vco->v = val & 0x1ff;
142	vco->r = (val >> 9) & 0x7f;
143	vco->s = (val >> 16) & 03;
144	return 0;
145}
146
147/**
148 * vco_set() - commit changes to an ICST VCO
149 * @icst: the ICST clock to set
150 * @vco: the VCO struct to set the changes from
151 */
152static int vco_set(struct clk_icst *icst, struct icst_vco vco)
153{
154	u32 mask;
155	u32 val;
156	int ret;
157
158	/* Mask the bits used by the VCO */
159	switch (icst->ctype) {
160	case ICST_INTEGRATOR_AP_CM:
161		mask = INTEGRATOR_AP_CM_BITS;
162		val = vco.v & 0xFF;
163		if (vco.v & 0x100)
164			pr_err("ICST error: tried to set bit 8 of VDW\n");
165		if (vco.s != 1)
166			pr_err("ICST error: tried to use VOD != 1\n");
167		if (vco.r != 22)
168			pr_err("ICST error: tried to use RDW != 22\n");
169		break;
170	case ICST_INTEGRATOR_AP_SYS:
171		mask = INTEGRATOR_AP_SYS_BITS;
172		val = vco.v & 0xFF;
173		if (vco.v & 0x100)
174			pr_err("ICST error: tried to set bit 8 of VDW\n");
175		if (vco.s != 3)
176			pr_err("ICST error: tried to use VOD != 1\n");
177		if (vco.r != 46)
178			pr_err("ICST error: tried to use RDW != 22\n");
179		break;
180	case ICST_INTEGRATOR_CP_CM_CORE:
181		mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */
182		val = (vco.v & 0xFF) | vco.s << 8;
183		if (vco.v & 0x100)
184			pr_err("ICST error: tried to set bit 8 of VDW\n");
185		if (vco.r != 22)
186			pr_err("ICST error: tried to use RDW != 22\n");
187		break;
188	case ICST_INTEGRATOR_CP_CM_MEM:
189		mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */
190		val = ((vco.v & 0xFF) << 12) | (vco.s << 20);
191		if (vco.v & 0x100)
192			pr_err("ICST error: tried to set bit 8 of VDW\n");
193		if (vco.r != 22)
194			pr_err("ICST error: tried to use RDW != 22\n");
195		break;
196	default:
197		/* Regular auxiliary oscillator */
198		mask = VERSATILE_AUX_OSC_BITS;
199		val = vco.v | (vco.r << 9) | (vco.s << 16);
200		break;
201	}
202
203	pr_debug("ICST: new val = 0x%08x\n", val);
204
205	/* This magic unlocks the VCO so it can be controlled */
206	ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL);
207	if (ret)
208		return ret;
209	ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val);
210	if (ret)
211		return ret;
212	/* This locks the VCO again */
213	ret = regmap_write(icst->map, icst->lockreg_off, 0);
214	if (ret)
215		return ret;
216	return 0;
217}
218
219static unsigned long icst_recalc_rate(struct clk_hw *hw,
220				      unsigned long parent_rate)
221{
222	struct clk_icst *icst = to_icst(hw);
223	struct icst_vco vco;
224	int ret;
225
226	if (parent_rate)
227		icst->params->ref = parent_rate;
228	ret = vco_get(icst, &vco);
229	if (ret) {
230		pr_err("ICST: could not get VCO setting\n");
231		return 0;
232	}
233	icst->rate = icst_hz(icst->params, vco);
234	return icst->rate;
235}
236
237static int icst_determine_rate(struct clk_hw *hw,
238			       struct clk_rate_request *req)
239{
240	struct clk_icst *icst = to_icst(hw);
241	struct icst_vco vco;
242
243	if (icst->ctype == ICST_INTEGRATOR_AP_CM ||
244	    icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
245		if (req->rate <= 12000000)
246			req->rate = 12000000;
247		else if (req->rate >= 160000000)
248			req->rate = 160000000;
249		else {
250			/* Slam to closest megahertz */
251			req->rate = DIV_ROUND_CLOSEST(req->rate, 1000000) * 1000000;
252		}
253
254		return 0;
255	}
256
257	if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
258		if (req->rate <= 6000000)
259			req->rate = 6000000;
260		else if (req->rate >= 66000000)
261			req->rate = 66000000;
262		else {
263			/* Slam to closest 0.5 megahertz */
264			req->rate = DIV_ROUND_CLOSEST(req->rate, 500000) * 500000;
265		}
266
267		return 0;
268	}
269
270	if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
271		/* Divides between 3 and 50 MHz in steps of 0.25 MHz */
272		if (req->rate <= 3000000)
273			req->rate = 3000000;
274		else if (req->rate >= 50000000)
275			req->rate = 5000000;
276		else {
277			/* Slam to closest 0.25 MHz */
278			req->rate = DIV_ROUND_CLOSEST(req->rate, 250000) * 250000;
279		}
280
281		return 0;
282	}
283
284	if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
285		/*
286		 * If we're below or less than halfway from 25 to 33 MHz
287		 * select 25 MHz
288		 */
289		if (req->rate <= 25000000 || req->rate < 29000000)
290			req->rate = 25000000;
291		else {
292			/* Else just return the default frequency */
293			req->rate = 33000000;
294		}
295
296		return 0;
297	}
298
299	vco = icst_hz_to_vco(icst->params, req->rate);
300	req->rate = icst_hz(icst->params, vco);
301
302	return 0;
303}
304
305static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
306			 unsigned long parent_rate)
307{
308	struct clk_icst *icst = to_icst(hw);
309	struct icst_vco vco;
310
311	if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
312		/* This clock is especially primitive */
313		unsigned int val;
314		int ret;
315
316		if (rate == 25000000) {
317			val = 0;
318		} else if (rate == 33000000) {
319			val = INTEGRATOR_AP_PCI_25_33_MHZ;
320		} else {
321			pr_err("ICST: cannot set PCI frequency %lu\n",
322			       rate);
323			return -EINVAL;
324		}
325		ret = regmap_write(icst->map, icst->lockreg_off,
326				   VERSATILE_LOCK_VAL);
327		if (ret)
328			return ret;
329		ret = regmap_update_bits(icst->map, icst->vcoreg_off,
330					 INTEGRATOR_AP_PCI_25_33_MHZ,
331					 val);
332		if (ret)
333			return ret;
334		/* This locks the VCO again */
335		ret = regmap_write(icst->map, icst->lockreg_off, 0);
336		if (ret)
337			return ret;
338		return 0;
339	}
340
341	if (parent_rate)
342		icst->params->ref = parent_rate;
343	vco = icst_hz_to_vco(icst->params, rate);
344	icst->rate = icst_hz(icst->params, vco);
345	return vco_set(icst, vco);
346}
347
348static const struct clk_ops icst_ops = {
349	.recalc_rate = icst_recalc_rate,
350	.determine_rate = icst_determine_rate,
351	.set_rate = icst_set_rate,
352};
353
354struct clk *icst_clk_setup(struct device *dev,
355			   const struct clk_icst_desc *desc,
356			   const char *name,
357			   const char *parent_name,
358			   struct regmap *map,
359			   enum icst_control_type ctype)
360{
361	struct clk *clk;
362	struct clk_icst *icst;
363	struct clk_init_data init;
364	struct icst_params *pclone;
365
366	icst = kzalloc(sizeof(*icst), GFP_KERNEL);
367	if (!icst)
368		return ERR_PTR(-ENOMEM);
369
370	pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL);
371	if (!pclone) {
372		kfree(icst);
373		return ERR_PTR(-ENOMEM);
374	}
375
376	init.name = name;
377	init.ops = &icst_ops;
378	init.flags = 0;
379	init.parent_names = (parent_name ? &parent_name : NULL);
380	init.num_parents = (parent_name ? 1 : 0);
381	icst->map = map;
382	icst->hw.init = &init;
383	icst->params = pclone;
384	icst->vcoreg_off = desc->vco_offset;
385	icst->lockreg_off = desc->lock_offset;
386	icst->ctype = ctype;
387
388	clk = clk_register(dev, &icst->hw);
389	if (IS_ERR(clk)) {
390		kfree(pclone);
391		kfree(icst);
392	}
393
394	return clk;
395}
396EXPORT_SYMBOL_GPL(icst_clk_setup);
397
398struct clk *icst_clk_register(struct device *dev,
399			const struct clk_icst_desc *desc,
400			const char *name,
401			const char *parent_name,
402			void __iomem *base)
403{
404	struct regmap_config icst_regmap_conf = {
405		.reg_bits = 32,
406		.val_bits = 32,
407		.reg_stride = 4,
408	};
409	struct regmap *map;
410
411	map = regmap_init_mmio(dev, base, &icst_regmap_conf);
412	if (IS_ERR(map)) {
413		pr_err("could not initialize ICST regmap\n");
414		return ERR_CAST(map);
415	}
416	return icst_clk_setup(dev, desc, name, parent_name, map,
417			      ICST_VERSATILE);
418}
419EXPORT_SYMBOL_GPL(icst_clk_register);
420
421#ifdef CONFIG_OF
422/*
423 * In a device tree, an memory-mapped ICST clock appear as a child
424 * of a syscon node. Assume this and probe it only as a child of a
425 * syscon.
426 */
427
428static const struct icst_params icst525_params = {
429	.vco_max	= ICST525_VCO_MAX_5V,
430	.vco_min	= ICST525_VCO_MIN,
431	.vd_min		= 8,
432	.vd_max		= 263,
433	.rd_min		= 3,
434	.rd_max		= 65,
435	.s2div		= icst525_s2div,
436	.idx2s		= icst525_idx2s,
437};
438
439static const struct icst_params icst307_params = {
440	.vco_max	= ICST307_VCO_MAX,
441	.vco_min	= ICST307_VCO_MIN,
442	.vd_min		= 4 + 8,
443	.vd_max		= 511 + 8,
444	.rd_min		= 1 + 2,
445	.rd_max		= 127 + 2,
446	.s2div		= icst307_s2div,
447	.idx2s		= icst307_idx2s,
448};
449
450/*
451 * The core modules on the Integrator/AP and Integrator/CP have
452 * especially crippled ICST525 control.
453 */
454static const struct icst_params icst525_apcp_cm_params = {
455	.vco_max	= ICST525_VCO_MAX_5V,
456	.vco_min	= ICST525_VCO_MIN,
457	/* Minimum 12 MHz, VDW = 4 */
458	.vd_min		= 12,
459	/*
460	 * Maximum 160 MHz, VDW = 152 for all core modules, but
461	 * CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually
462	 * go to 200 MHz (max VDW = 192).
463	 */
464	.vd_max		= 192,
465	/* r is hardcoded to 22 and this is the actual divisor, +2 */
466	.rd_min		= 24,
467	.rd_max		= 24,
468	.s2div		= icst525_s2div,
469	.idx2s		= icst525_idx2s,
470};
471
472static const struct icst_params icst525_ap_sys_params = {
473	.vco_max	= ICST525_VCO_MAX_5V,
474	.vco_min	= ICST525_VCO_MIN,
475	/* Minimum 3 MHz, VDW = 4 */
476	.vd_min		= 3,
477	/* Maximum 50 MHz, VDW = 192 */
478	.vd_max		= 50,
479	/* r is hardcoded to 46 and this is the actual divisor, +2 */
480	.rd_min		= 48,
481	.rd_max		= 48,
482	.s2div		= icst525_s2div,
483	.idx2s		= icst525_idx2s,
484};
485
486static const struct icst_params icst525_ap_pci_params = {
487	.vco_max	= ICST525_VCO_MAX_5V,
488	.vco_min	= ICST525_VCO_MIN,
489	/* Minimum 25 MHz */
490	.vd_min		= 25,
491	/* Maximum 33 MHz */
492	.vd_max		= 33,
493	/* r is hardcoded to 14 or 22 and this is the actual divisors +2 */
494	.rd_min		= 16,
495	.rd_max		= 24,
496	.s2div		= icst525_s2div,
497	.idx2s		= icst525_idx2s,
498};
499
500static void __init of_syscon_icst_setup(struct device_node *np)
501{
502	struct device_node *parent;
503	struct regmap *map;
504	struct clk_icst_desc icst_desc;
505	const char *name;
506	const char *parent_name;
507	struct clk *regclk;
508	enum icst_control_type ctype;
509
510	/* We do not release this reference, we are using it perpetually */
511	parent = of_get_parent(np);
512	if (!parent) {
513		pr_err("no parent node for syscon ICST clock\n");
514		return;
515	}
516	map = syscon_node_to_regmap(parent);
517	if (IS_ERR(map)) {
518		pr_err("no regmap for syscon ICST clock parent\n");
519		return;
520	}
521
522	if (of_property_read_u32(np, "reg", &icst_desc.vco_offset) &&
523	    of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) {
524		pr_err("no VCO register offset for ICST clock\n");
525		return;
526	}
527	if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) {
528		pr_err("no lock register offset for ICST clock\n");
529		return;
530	}
531
532	if (of_device_is_compatible(np, "arm,syscon-icst525")) {
533		icst_desc.params = &icst525_params;
534		ctype = ICST_VERSATILE;
535	} else if (of_device_is_compatible(np, "arm,syscon-icst307")) {
536		icst_desc.params = &icst307_params;
537		ctype = ICST_VERSATILE;
538	} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) {
539		icst_desc.params = &icst525_apcp_cm_params;
540		ctype = ICST_INTEGRATOR_AP_CM;
541	} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) {
542		icst_desc.params = &icst525_ap_sys_params;
543		ctype = ICST_INTEGRATOR_AP_SYS;
544	} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) {
545		icst_desc.params = &icst525_ap_pci_params;
546		ctype = ICST_INTEGRATOR_AP_PCI;
547	} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) {
548		icst_desc.params = &icst525_apcp_cm_params;
549		ctype = ICST_INTEGRATOR_CP_CM_CORE;
550	} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) {
551		icst_desc.params = &icst525_apcp_cm_params;
552		ctype = ICST_INTEGRATOR_CP_CM_MEM;
553	} else {
554		pr_err("unknown ICST clock %pOF\n", np);
555		return;
556	}
557
558	/* Parent clock name is not the same as node parent */
559	parent_name = of_clk_get_parent_name(np, 0);
560	name = kasprintf(GFP_KERNEL, "%pOFP", np);
561
562	regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype);
563	if (IS_ERR(regclk)) {
564		pr_err("error setting up syscon ICST clock %s\n", name);
565		kfree(name);
566		return;
567	}
568	of_clk_add_provider(np, of_clk_src_simple_get, regclk);
569	pr_debug("registered syscon ICST clock %s\n", name);
570}
571
572CLK_OF_DECLARE(arm_syscon_icst525_clk,
573	       "arm,syscon-icst525", of_syscon_icst_setup);
574CLK_OF_DECLARE(arm_syscon_icst307_clk,
575	       "arm,syscon-icst307", of_syscon_icst_setup);
576CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk,
577	       "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup);
578CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk,
579	       "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup);
580CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk,
581	       "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup);
582CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk,
583	       "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup);
584CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk,
585	       "arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup);
586#endif