divider.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * TI Divider Clock
  4 *
  5 * Copyright (C) 2013 Texas Instruments, Inc.
  6 *
  7 * Tero Kristo <t-kristo@ti.com>
  8 */
  9
 10#include <linux/clk-provider.h>
 11#include <linux/slab.h>
 12#include <linux/err.h>
 13#include <linux/of.h>
 14#include <linux/of_address.h>
 15#include <linux/clk/ti.h>
 16#include "clock.h"
 17
 18#undef pr_fmt
 19#define pr_fmt(fmt) "%s: " fmt, __func__
 20
 21static unsigned int _get_table_div(const struct clk_div_table *table,
 22				   unsigned int val)
 23{
 24	const struct clk_div_table *clkt;
 25
 26	for (clkt = table; clkt->div; clkt++)
 27		if (clkt->val == val)
 28			return clkt->div;
 29	return 0;
 30}
 31
 32static void _setup_mask(struct clk_omap_divider *divider)
 33{
 34	u16 mask;
 35	u32 max_val;
 36	const struct clk_div_table *clkt;
 37
 38	if (divider->table) {
 39		max_val = 0;
 40
 41		for (clkt = divider->table; clkt->div; clkt++)
 42			if (clkt->val > max_val)
 43				max_val = clkt->val;
 44	} else {
 45		max_val = divider->max;
 46
 47		if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
 48		    !(divider->flags & CLK_DIVIDER_POWER_OF_TWO))
 49			max_val--;
 50	}
 51
 52	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
 53		mask = fls(max_val) - 1;
 54	else
 55		mask = max_val;
 56
 57	divider->mask = (1 << fls(mask)) - 1;
 58}
 59
 60static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
 61{
 62	if (divider->flags & CLK_DIVIDER_ONE_BASED)
 63		return val;
 64	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
 65		return 1 << val;
 66	if (divider->table)
 67		return _get_table_div(divider->table, val);
 68	return val + 1;
 69}
 70
 71static unsigned int _get_table_val(const struct clk_div_table *table,
 72				   unsigned int div)
 73{
 74	const struct clk_div_table *clkt;
 75
 76	for (clkt = table; clkt->div; clkt++)
 77		if (clkt->div == div)
 78			return clkt->val;
 79	return 0;
 80}
 81
 82static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
 83{
 84	if (divider->flags & CLK_DIVIDER_ONE_BASED)
 85		return div;
 86	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
 87		return __ffs(div);
 88	if (divider->table)
 89		return  _get_table_val(divider->table, div);
 90	return div - 1;
 91}
 92
 93static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
 94						unsigned long parent_rate)
 95{
 96	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
 97	unsigned int div, val;
 98
 99	val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
100	val &= divider->mask;
101
102	div = _get_div(divider, val);
103	if (!div) {
104		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
105		     "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
106		     clk_hw_get_name(hw));
107		return parent_rate;
108	}
109
110	return DIV_ROUND_UP(parent_rate, div);
111}
112
113/*
114 * The reverse of DIV_ROUND_UP: The maximum number which
115 * divided by m is r
116 */
117#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
118
119static bool _is_valid_table_div(const struct clk_div_table *table,
120				unsigned int div)
121{
122	const struct clk_div_table *clkt;
123
124	for (clkt = table; clkt->div; clkt++)
125		if (clkt->div == div)
126			return true;
127	return false;
128}
129
130static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
131{
132	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
133		return is_power_of_2(div);
134	if (divider->table)
135		return _is_valid_table_div(divider->table, div);
136	return true;
137}
138
139static int _div_round_up(const struct clk_div_table *table,
140			 unsigned long parent_rate, unsigned long rate)
141{
142	const struct clk_div_table *clkt;
143	int up = INT_MAX;
144	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
145
146	for (clkt = table; clkt->div; clkt++) {
147		if (clkt->div == div)
148			return clkt->div;
149		else if (clkt->div < div)
150			continue;
151
152		if ((clkt->div - div) < (up - div))
153			up = clkt->div;
154	}
155
156	return up;
157}
158
159static int _div_round(const struct clk_div_table *table,
160		      unsigned long parent_rate, unsigned long rate)
161{
162	if (!table)
163		return DIV_ROUND_UP(parent_rate, rate);
164
165	return _div_round_up(table, parent_rate, rate);
166}
167
168static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
169				  unsigned long *best_parent_rate)
170{
171	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
172	int i, bestdiv = 0;
173	unsigned long parent_rate, best = 0, now, maxdiv;
174	unsigned long parent_rate_saved = *best_parent_rate;
175
176	if (!rate)
177		rate = 1;
178
179	maxdiv = divider->max;
180
181	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
182		parent_rate = *best_parent_rate;
183		bestdiv = _div_round(divider->table, parent_rate, rate);
184		bestdiv = bestdiv == 0 ? 1 : bestdiv;
185		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
186		return bestdiv;
187	}
188
189	/*
190	 * The maximum divider we can use without overflowing
191	 * unsigned long in rate * i below
192	 */
193	maxdiv = min(ULONG_MAX / rate, maxdiv);
194
195	for (i = 1; i <= maxdiv; i++) {
196		if (!_is_valid_div(divider, i))
197			continue;
198		if (rate * i == parent_rate_saved) {
199			/*
200			 * It's the most ideal case if the requested rate can be
201			 * divided from parent clock without needing to change
202			 * parent rate, so return the divider immediately.
203			 */
204			*best_parent_rate = parent_rate_saved;
205			return i;
206		}
207		parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
208				MULT_ROUND_UP(rate, i));
209		now = DIV_ROUND_UP(parent_rate, i);
210		if (now <= rate && now > best) {
211			bestdiv = i;
212			best = now;
213			*best_parent_rate = parent_rate;
214		}
215	}
216
217	if (!bestdiv) {
218		bestdiv = divider->max;
219		*best_parent_rate =
220			clk_hw_round_rate(clk_hw_get_parent(hw), 1);
221	}
222
223	return bestdiv;
224}
225
226static int ti_clk_divider_determine_rate(struct clk_hw *hw,
227					 struct clk_rate_request *req)
228{
229	int div;
230	div = ti_clk_divider_bestdiv(hw, req->rate, &req->best_parent_rate);
231
232	req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
233
234	return 0;
235}
236
237static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
238				   unsigned long parent_rate)
239{
240	struct clk_omap_divider *divider;
241	unsigned int div, value;
242	u32 val;
243
244	if (!hw || !rate)
245		return -EINVAL;
246
247	divider = to_clk_omap_divider(hw);
248
249	div = DIV_ROUND_UP(parent_rate, rate);
250
251	if (div > divider->max)
252		div = divider->max;
253	if (div < divider->min)
254		div = divider->min;
255
256	value = _get_val(divider, div);
257
258	val = ti_clk_ll_ops->clk_readl(&divider->reg);
259	val &= ~(divider->mask << divider->shift);
260	val |= value << divider->shift;
261	ti_clk_ll_ops->clk_writel(val, &divider->reg);
262
263	ti_clk_latch(&divider->reg, divider->latch);
264
265	return 0;
266}
267
268/**
269 * clk_divider_save_context - Save the divider value
270 * @hw: pointer  struct clk_hw
271 *
272 * Save the divider value
273 */
274static int clk_divider_save_context(struct clk_hw *hw)
275{
276	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
277	u32 val;
278
279	val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
280	divider->context = val & divider->mask;
281
282	return 0;
283}
284
285/**
286 * clk_divider_restore_context - restore the saved the divider value
287 * @hw: pointer  struct clk_hw
288 *
289 * Restore the saved the divider value
290 */
291static void clk_divider_restore_context(struct clk_hw *hw)
292{
293	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
294	u32 val;
295
296	val = ti_clk_ll_ops->clk_readl(&divider->reg);
297	val &= ~(divider->mask << divider->shift);
298	val |= divider->context << divider->shift;
299	ti_clk_ll_ops->clk_writel(val, &divider->reg);
300}
301
302const struct clk_ops ti_clk_divider_ops = {
303	.recalc_rate = ti_clk_divider_recalc_rate,
304	.determine_rate = ti_clk_divider_determine_rate,
305	.set_rate = ti_clk_divider_set_rate,
306	.save_context = clk_divider_save_context,
307	.restore_context = clk_divider_restore_context,
308};
309
310static struct clk *_register_divider(struct device_node *node,
311				     u32 flags,
312				     struct clk_omap_divider *div)
313{
314	struct clk_init_data init;
315	const char *parent_name;
316	const char *name;
317
318	parent_name = of_clk_get_parent_name(node, 0);
319
320	name = ti_dt_clk_name(node);
321	init.name = name;
322	init.ops = &ti_clk_divider_ops;
323	init.flags = flags;
324	init.parent_names = (parent_name ? &parent_name : NULL);
325	init.num_parents = (parent_name ? 1 : 0);
326
327	div->hw.init = &init;
328
329	/* register the clock */
330	return of_ti_clk_register(node, &div->hw, name);
331}
332
333int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
334			      u8 flags, struct clk_omap_divider *divider)
335{
336	int valid_div = 0;
337	int i;
338	struct clk_div_table *tmp;
339	u16 min_div = 0;
340
341	if (!div_table) {
342		divider->min = 1;
343		divider->max = max_div;
344		_setup_mask(divider);
345		return 0;
346	}
347
348	i = 0;
349
350	while (!num_dividers || i < num_dividers) {
351		if (div_table[i] == -1)
352			break;
353		if (div_table[i])
354			valid_div++;
355		i++;
356	}
357
358	num_dividers = i;
359
360	tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
361	if (!tmp)
362		return -ENOMEM;
363
364	valid_div = 0;
365
366	for (i = 0; i < num_dividers; i++)
367		if (div_table[i] > 0) {
368			tmp[valid_div].div = div_table[i];
369			tmp[valid_div].val = i;
370			valid_div++;
371			if (div_table[i] > max_div)
372				max_div = div_table[i];
373			if (!min_div || div_table[i] < min_div)
374				min_div = div_table[i];
375		}
376
377	divider->min = min_div;
378	divider->max = max_div;
379	divider->table = tmp;
380	_setup_mask(divider);
381
382	return 0;
383}
384
385static int __init ti_clk_get_div_table(struct device_node *node,
386				       struct clk_omap_divider *div)
387{
388	struct clk_div_table *table;
389	const __be32 *divspec;
390	u32 val;
391	u32 num_div;
392	u32 valid_div;
393	int i;
394
395	divspec = of_get_property(node, "ti,dividers", &num_div);
396
397	if (!divspec)
398		return 0;
399
400	num_div /= 4;
401
402	valid_div = 0;
403
404	/* Determine required size for divider table */
405	for (i = 0; i < num_div; i++) {
406		of_property_read_u32_index(node, "ti,dividers", i, &val);
407		if (val)
408			valid_div++;
409	}
410
411	if (!valid_div) {
412		pr_err("no valid dividers for %pOFn table\n", node);
413		return -EINVAL;
414	}
415
416	table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);
417	if (!table)
418		return -ENOMEM;
419
420	valid_div = 0;
421
422	for (i = 0; i < num_div; i++) {
423		of_property_read_u32_index(node, "ti,dividers", i, &val);
424		if (val) {
425			table[valid_div].div = val;
426			table[valid_div].val = i;
427			valid_div++;
428		}
429	}
430
431	div->table = table;
432
433	return 0;
434}
435
436static int _populate_divider_min_max(struct device_node *node,
437				     struct clk_omap_divider *divider)
438{
439	u32 min_div = 0;
440	u32 max_div = 0;
441	u32 val;
442	const struct clk_div_table *clkt;
443
444	if (!divider->table) {
445		/* Clk divider table not provided, determine min/max divs */
446		if (of_property_read_u32(node, "ti,min-div", &min_div))
447			min_div = 1;
448
449		if (of_property_read_u32(node, "ti,max-div", &max_div)) {
450			pr_err("no max-div for %pOFn!\n", node);
451			return -EINVAL;
452		}
453	} else {
454
455		for (clkt = divider->table; clkt->div; clkt++) {
456			val = clkt->div;
457			if (val > max_div)
458				max_div = val;
459			if (!min_div || val < min_div)
460				min_div = val;
461		}
462	}
463
464	divider->min = min_div;
465	divider->max = max_div;
466	_setup_mask(divider);
467
468	return 0;
469}
470
471static int __init ti_clk_divider_populate(struct device_node *node,
472					  struct clk_omap_divider *div,
473					  u32 *flags)
474{
475	u32 val;
476	int ret;
477
478	ret = ti_clk_get_reg_addr(node, 0, &div->reg);
479	if (ret)
480		return ret;
481
482	div->shift = div->reg.bit;
483
484	if (!of_property_read_u32(node, "ti,latch-bit", &val))
485		div->latch = val;
486	else
487		div->latch = -EINVAL;
488
489	*flags = 0;
490	div->flags = 0;
491
492	if (of_property_read_bool(node, "ti,index-starts-at-one"))
493		div->flags |= CLK_DIVIDER_ONE_BASED;
494
495	if (of_property_read_bool(node, "ti,index-power-of-two"))
496		div->flags |= CLK_DIVIDER_POWER_OF_TWO;
497
498	if (of_property_read_bool(node, "ti,set-rate-parent"))
499		*flags |= CLK_SET_RATE_PARENT;
500
501	ret = ti_clk_get_div_table(node, div);
502	if (ret)
503		return ret;
504
505	return _populate_divider_min_max(node, div);
506}
507
508/**
509 * of_ti_divider_clk_setup - Setup function for simple div rate clock
510 * @node: device node for this clock
511 *
512 * Sets up a basic divider clock.
513 */
514static void __init of_ti_divider_clk_setup(struct device_node *node)
515{
516	struct clk *clk;
517	u32 flags = 0;
518	struct clk_omap_divider *div;
519
520	div = kzalloc(sizeof(*div), GFP_KERNEL);
521	if (!div)
522		return;
523
524	if (ti_clk_divider_populate(node, div, &flags))
525		goto cleanup;
526
527	clk = _register_divider(node, flags, div);
528	if (!IS_ERR(clk)) {
529		of_clk_add_provider(node, of_clk_src_simple_get, clk);
530		of_ti_clk_autoidle_setup(node);
531		return;
532	}
533
534cleanup:
535	kfree(div->table);
536	kfree(div);
537}
538CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
539
540static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
541{
542	struct clk_omap_divider *div;
543	u32 tmp;
544
545	div = kzalloc(sizeof(*div), GFP_KERNEL);
546	if (!div)
547		return;
548
549	if (ti_clk_divider_populate(node, div, &tmp))
550		goto cleanup;
551
552	if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
553		return;
554
555cleanup:
556	kfree(div->table);
557	kfree(div);
558}
559CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
560	       of_ti_composite_divider_clk_setup);