clk-814x.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2
  3#include <linux/kernel.h>
  4#include <linux/clk.h>
  5#include <linux/clk-provider.h>
  6#include <linux/clk/ti.h>
  7#include <linux/of_platform.h>
  8#include <dt-bindings/clock/dm814.h>
  9
 10#include "clock.h"
 11
 12static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
 13	{ DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
 14	{ 0 },
 15};
 16
 17static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
 18	{ DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
 19	{ DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
 20	{ DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
 21	{ DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
 22	{ DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
 23	{ DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
 24	{ DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
 25	{ DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
 26	{ DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
 27	{ DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
 28	{ DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
 29	{ DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
 30	{ DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
 31	{ DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
 32	{ DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
 33	{ DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
 34	{ DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
 35	{ DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
 36	{ DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
 37	{ DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
 38	{ 0 },
 39};
 40
 41static const struct
 42omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
 43	{ 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
 44};
 45
 46const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
 47	{ 0x48180500, dm814_default_clkctrl_regs },
 48	{ 0x48181400, dm814_alwon_clkctrl_regs },
 49	{ 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
 50	{ 0 },
 51};
 52
 53static struct ti_dt_clk dm814_clks[] = {
 54	DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
 55	{ .node_name = NULL },
 56};
 57
 58static bool timer_clocks_initialized;
 59
 60static int __init dm814x_adpll_early_init(void)
 61{
 62	struct device_node *np;
 63
 64	if (!timer_clocks_initialized)
 65		return -ENODEV;
 66
 67	np = of_find_node_by_name(NULL, "pllss");
 68	if (!np) {
 69		pr_err("Could not find node for plls\n");
 70		return -ENODEV;
 71	}
 72
 73	of_platform_populate(np, NULL, NULL, NULL);
 74	of_node_put(np);
 75
 76	return 0;
 77}
 78core_initcall(dm814x_adpll_early_init);
 79
 80static const char * const init_clocks[] = {
 81	"pll040clkout",		/* MPU 481c5040.adpll.clkout */
 82	"pll290clkout",		/* DDR 481c5290.adpll.clkout */
 83};
 84
 85static int __init dm814x_adpll_enable_init_clocks(void)
 86{
 87	int i, err;
 88
 89	if (!timer_clocks_initialized)
 90		return -ENODEV;
 91
 92	for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
 93		struct clk *clock;
 94
 95		clock = clk_get(NULL, init_clocks[i]);
 96		if (WARN(IS_ERR(clock), "could not find init clock %s\n",
 97			 init_clocks[i]))
 98			continue;
 99		err = clk_prepare_enable(clock);
100		if (WARN(err, "could not enable init clock %s\n",
101			 init_clocks[i]))
102			continue;
103	}
104
105	return 0;
106}
107postcore_initcall(dm814x_adpll_enable_init_clocks);
108
109int __init dm814x_dt_clk_init(void)
110{
111	ti_dt_clocks_register(dm814_clks);
112	omap2_clk_disable_autoidle_all();
113	ti_clk_add_aliases();
114	omap2_clk_enable_init_clocks(NULL, 0);
115	timer_clocks_initialized = true;
116
117	return 0;
118}