clk-tegra114.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#include <linux/io.h>
   7#include <linux/clk-provider.h>
   8#include <linux/of.h>
   9#include <linux/of_address.h>
  10#include <linux/delay.h>
  11#include <linux/export.h>
  12#include <linux/clk/tegra.h>
  13#include <dt-bindings/clock/tegra114-car.h>
  14#include <dt-bindings/reset/nvidia,tegra114-car.h>
  15
  16#include "clk.h"
  17#include "clk-id.h"
  18
  19#define RST_DFLL_DVCO			0x2F4
  20#define CPU_FINETRIM_SELECT		0x4d4	/* override default prop dlys */
  21#define CPU_FINETRIM_DR			0x4d8	/* rise->rise prop dly A */
  22#define CPU_FINETRIM_R			0x4e4	/* rise->rise prop dly inc A */
  23
  24/* RST_DFLL_DVCO bitfields */
  25#define DVFS_DFLL_RESET_SHIFT		0
  26
  27/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
  28#define CPU_FINETRIM_1_FCPU_1		BIT(0)	/* fcpu0 */
  29#define CPU_FINETRIM_1_FCPU_2		BIT(1)	/* fcpu1 */
  30#define CPU_FINETRIM_1_FCPU_3		BIT(2)	/* fcpu2 */
  31#define CPU_FINETRIM_1_FCPU_4		BIT(3)	/* fcpu3 */
  32#define CPU_FINETRIM_1_FCPU_5		BIT(4)	/* fl2 */
  33#define CPU_FINETRIM_1_FCPU_6		BIT(5)	/* ftop */
  34
  35/* CPU_FINETRIM_R bitfields */
  36#define CPU_FINETRIM_R_FCPU_1_SHIFT	0		/* fcpu0 */
  37#define CPU_FINETRIM_R_FCPU_1_MASK	(0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
  38#define CPU_FINETRIM_R_FCPU_2_SHIFT	2		/* fcpu1 */
  39#define CPU_FINETRIM_R_FCPU_2_MASK	(0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
  40#define CPU_FINETRIM_R_FCPU_3_SHIFT	4		/* fcpu2 */
  41#define CPU_FINETRIM_R_FCPU_3_MASK	(0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
  42#define CPU_FINETRIM_R_FCPU_4_SHIFT	6		/* fcpu3 */
  43#define CPU_FINETRIM_R_FCPU_4_MASK	(0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
  44#define CPU_FINETRIM_R_FCPU_5_SHIFT	8		/* fl2 */
  45#define CPU_FINETRIM_R_FCPU_5_MASK	(0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
  46#define CPU_FINETRIM_R_FCPU_6_SHIFT	10		/* ftop */
  47#define CPU_FINETRIM_R_FCPU_6_MASK	(0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
  48
  49#define TEGRA114_CLK_PERIPH_BANKS	5
  50
  51#define PLLC_BASE 0x80
  52#define PLLC_MISC2 0x88
  53#define PLLC_MISC 0x8c
  54#define PLLC2_BASE 0x4e8
  55#define PLLC2_MISC 0x4ec
  56#define PLLC3_BASE 0x4fc
  57#define PLLC3_MISC 0x500
  58#define PLLM_BASE 0x90
  59#define PLLM_MISC 0x9c
  60#define PLLP_BASE 0xa0
  61#define PLLP_MISC 0xac
  62#define PLLX_BASE 0xe0
  63#define PLLX_MISC 0xe4
  64#define PLLX_MISC2 0x514
  65#define PLLX_MISC3 0x518
  66#define PLLD_BASE 0xd0
  67#define PLLD_MISC 0xdc
  68#define PLLD2_BASE 0x4b8
  69#define PLLD2_MISC 0x4bc
  70#define PLLE_BASE 0xe8
  71#define PLLE_MISC 0xec
  72#define PLLA_BASE 0xb0
  73#define PLLA_MISC 0xbc
  74#define PLLU_BASE 0xc0
  75#define PLLU_MISC 0xcc
  76#define PLLRE_BASE 0x4c4
  77#define PLLRE_MISC 0x4c8
  78
  79#define PLL_MISC_LOCK_ENABLE 18
  80#define PLLC_MISC_LOCK_ENABLE 24
  81#define PLLDU_MISC_LOCK_ENABLE 22
  82#define PLLE_MISC_LOCK_ENABLE 9
  83#define PLLRE_MISC_LOCK_ENABLE 30
  84
  85#define PLLC_IDDQ_BIT 26
  86#define PLLX_IDDQ_BIT 3
  87#define PLLRE_IDDQ_BIT 16
  88
  89#define PLL_BASE_LOCK BIT(27)
  90#define PLLE_MISC_LOCK BIT(11)
  91#define PLLRE_MISC_LOCK BIT(24)
  92#define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
  93
  94#define PLLE_AUX 0x48c
  95#define PLLC_OUT 0x84
  96#define PLLM_OUT 0x94
  97
  98#define OSC_CTRL			0x50
  99#define OSC_CTRL_OSC_FREQ_SHIFT		28
 100#define OSC_CTRL_PLL_REF_DIV_SHIFT	26
 101
 102#define PLLXC_SW_MAX_P			6
 103
 104#define CCLKG_BURST_POLICY 0x368
 105
 106#define CLK_SOURCE_CSITE 0x1d4
 107#define CLK_SOURCE_EMC 0x19c
 108
 109/* PLLM override registers */
 110#define PMC_PLLM_WB0_OVERRIDE 0x1dc
 111#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 112
 113/* Tegra CPU clock and reset control regs */
 114#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
 115
 116#define MUX8(_name, _parents, _offset, \
 117			     _clk_num, _gate_flags, _clk_id)	\
 118	TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 119			29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
 120			_clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
 121			NULL)
 122
 123#ifdef CONFIG_PM_SLEEP
 124static struct cpu_clk_suspend_context {
 125	u32 clk_csite_src;
 126	u32 cclkg_burst;
 127	u32 cclkg_divider;
 128} tegra114_cpu_clk_sctx;
 129#endif
 130
 131static void __iomem *clk_base;
 132static void __iomem *pmc_base;
 133
 134static DEFINE_SPINLOCK(pll_d_lock);
 135static DEFINE_SPINLOCK(pll_d2_lock);
 136static DEFINE_SPINLOCK(pll_u_lock);
 137static DEFINE_SPINLOCK(pll_re_lock);
 138static DEFINE_SPINLOCK(emc_lock);
 139
 140static struct div_nmp pllxc_nmp = {
 141	.divm_shift = 0,
 142	.divm_width = 8,
 143	.divn_shift = 8,
 144	.divn_width = 8,
 145	.divp_shift = 20,
 146	.divp_width = 4,
 147};
 148
 149static const struct pdiv_map pllxc_p[] = {
 150	{ .pdiv =  1, .hw_val =  0 },
 151	{ .pdiv =  2, .hw_val =  1 },
 152	{ .pdiv =  3, .hw_val =  2 },
 153	{ .pdiv =  4, .hw_val =  3 },
 154	{ .pdiv =  5, .hw_val =  4 },
 155	{ .pdiv =  6, .hw_val =  5 },
 156	{ .pdiv =  8, .hw_val =  6 },
 157	{ .pdiv = 10, .hw_val =  7 },
 158	{ .pdiv = 12, .hw_val =  8 },
 159	{ .pdiv = 16, .hw_val =  9 },
 160	{ .pdiv = 12, .hw_val = 10 },
 161	{ .pdiv = 16, .hw_val = 11 },
 162	{ .pdiv = 20, .hw_val = 12 },
 163	{ .pdiv = 24, .hw_val = 13 },
 164	{ .pdiv = 32, .hw_val = 14 },
 165	{ .pdiv =  0, .hw_val =  0 },
 166};
 167
 168static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
 169	{ 12000000, 624000000, 104, 1, 2, 0 },
 170	{ 12000000, 600000000, 100, 1, 2, 0 },
 171	{ 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
 172	{ 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
 173	{ 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
 174	{ 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
 175	{        0,         0,   0, 0, 0, 0 },
 176};
 177
 178static struct tegra_clk_pll_params pll_c_params = {
 179	.input_min = 12000000,
 180	.input_max = 800000000,
 181	.cf_min = 12000000,
 182	.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
 183	.vco_min = 600000000,
 184	.vco_max = 1400000000,
 185	.base_reg = PLLC_BASE,
 186	.misc_reg = PLLC_MISC,
 187	.lock_mask = PLL_BASE_LOCK,
 188	.lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
 189	.lock_delay = 300,
 190	.iddq_reg = PLLC_MISC,
 191	.iddq_bit_idx = PLLC_IDDQ_BIT,
 192	.max_p = PLLXC_SW_MAX_P,
 193	.dyn_ramp_reg = PLLC_MISC2,
 194	.stepa_shift = 17,
 195	.stepb_shift = 9,
 196	.pdiv_tohw = pllxc_p,
 197	.div_nmp = &pllxc_nmp,
 198	.freq_table = pll_c_freq_table,
 199	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 200};
 201
 202static struct div_nmp pllcx_nmp = {
 203	.divm_shift = 0,
 204	.divm_width = 2,
 205	.divn_shift = 8,
 206	.divn_width = 8,
 207	.divp_shift = 20,
 208	.divp_width = 3,
 209};
 210
 211static const struct pdiv_map pllc_p[] = {
 212	{ .pdiv =  1, .hw_val = 0 },
 213	{ .pdiv =  2, .hw_val = 1 },
 214	{ .pdiv =  4, .hw_val = 3 },
 215	{ .pdiv =  8, .hw_val = 5 },
 216	{ .pdiv = 16, .hw_val = 7 },
 217	{ .pdiv =  0, .hw_val = 0 },
 218};
 219
 220static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
 221	{ 12000000, 600000000, 100, 1, 2, 0 },
 222	{ 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
 223	{ 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
 224	{ 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
 225	{ 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
 226	{        0,         0,   0, 0, 0, 0 },
 227};
 228
 229static struct tegra_clk_pll_params pll_c2_params = {
 230	.input_min = 12000000,
 231	.input_max = 48000000,
 232	.cf_min = 12000000,
 233	.cf_max = 19200000,
 234	.vco_min = 600000000,
 235	.vco_max = 1200000000,
 236	.base_reg = PLLC2_BASE,
 237	.misc_reg = PLLC2_MISC,
 238	.lock_mask = PLL_BASE_LOCK,
 239	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 240	.lock_delay = 300,
 241	.pdiv_tohw = pllc_p,
 242	.div_nmp = &pllcx_nmp,
 243	.max_p = 7,
 244	.ext_misc_reg[0] = 0x4f0,
 245	.ext_misc_reg[1] = 0x4f4,
 246	.ext_misc_reg[2] = 0x4f8,
 247	.freq_table = pll_cx_freq_table,
 248	.flags = TEGRA_PLL_USE_LOCK,
 249};
 250
 251static struct tegra_clk_pll_params pll_c3_params = {
 252	.input_min = 12000000,
 253	.input_max = 48000000,
 254	.cf_min = 12000000,
 255	.cf_max = 19200000,
 256	.vco_min = 600000000,
 257	.vco_max = 1200000000,
 258	.base_reg = PLLC3_BASE,
 259	.misc_reg = PLLC3_MISC,
 260	.lock_mask = PLL_BASE_LOCK,
 261	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 262	.lock_delay = 300,
 263	.pdiv_tohw = pllc_p,
 264	.div_nmp = &pllcx_nmp,
 265	.max_p = 7,
 266	.ext_misc_reg[0] = 0x504,
 267	.ext_misc_reg[1] = 0x508,
 268	.ext_misc_reg[2] = 0x50c,
 269	.freq_table = pll_cx_freq_table,
 270	.flags = TEGRA_PLL_USE_LOCK,
 271};
 272
 273static struct div_nmp pllm_nmp = {
 274	.divm_shift = 0,
 275	.divm_width = 8,
 276	.override_divm_shift = 0,
 277	.divn_shift = 8,
 278	.divn_width = 8,
 279	.override_divn_shift = 8,
 280	.divp_shift = 20,
 281	.divp_width = 1,
 282	.override_divp_shift = 27,
 283};
 284
 285static const struct pdiv_map pllm_p[] = {
 286	{ .pdiv = 1, .hw_val = 0 },
 287	{ .pdiv = 2, .hw_val = 1 },
 288	{ .pdiv = 0, .hw_val = 0 },
 289};
 290
 291static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
 292	{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
 293	{ 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
 294	{ 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
 295	{ 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
 296	{ 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
 297	{        0,         0,  0, 0, 0, 0 },
 298};
 299
 300static struct tegra_clk_pll_params pll_m_params = {
 301	.input_min = 12000000,
 302	.input_max = 500000000,
 303	.cf_min = 12000000,
 304	.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
 305	.vco_min = 400000000,
 306	.vco_max = 1066000000,
 307	.base_reg = PLLM_BASE,
 308	.misc_reg = PLLM_MISC,
 309	.lock_mask = PLL_BASE_LOCK,
 310	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 311	.lock_delay = 300,
 312	.max_p = 2,
 313	.pdiv_tohw = pllm_p,
 314	.div_nmp = &pllm_nmp,
 315	.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
 316	.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
 317	.freq_table = pll_m_freq_table,
 318	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
 319		 TEGRA_PLL_FIXED,
 320};
 321
 322static struct div_nmp pllp_nmp = {
 323	.divm_shift = 0,
 324	.divm_width = 5,
 325	.divn_shift = 8,
 326	.divn_width = 10,
 327	.divp_shift = 20,
 328	.divp_width = 3,
 329};
 330
 331static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
 332	{ 12000000, 216000000, 432, 12, 2, 8 },
 333	{ 13000000, 216000000, 432, 13, 2, 8 },
 334	{ 16800000, 216000000, 360, 14, 2, 8 },
 335	{ 19200000, 216000000, 360, 16, 2, 8 },
 336	{ 26000000, 216000000, 432, 26, 2, 8 },
 337	{        0,         0,   0,  0, 0, 0 },
 338};
 339
 340static struct tegra_clk_pll_params pll_p_params = {
 341	.input_min = 2000000,
 342	.input_max = 31000000,
 343	.cf_min = 1000000,
 344	.cf_max = 6000000,
 345	.vco_min = 200000000,
 346	.vco_max = 700000000,
 347	.base_reg = PLLP_BASE,
 348	.misc_reg = PLLP_MISC,
 349	.lock_mask = PLL_BASE_LOCK,
 350	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 351	.lock_delay = 300,
 352	.div_nmp = &pllp_nmp,
 353	.freq_table = pll_p_freq_table,
 354	.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
 355		 TEGRA_PLL_HAS_LOCK_ENABLE,
 356	.fixed_rate = 408000000,
 357};
 358
 359static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
 360	{  9600000, 282240000, 147,  5, 1, 4 },
 361	{  9600000, 368640000, 192,  5, 1, 4 },
 362	{  9600000, 240000000, 200,  8, 1, 8 },
 363	{ 28800000, 282240000, 245, 25, 1, 8 },
 364	{ 28800000, 368640000, 320, 25, 1, 8 },
 365	{ 28800000, 240000000, 200, 24, 1, 8 },
 366	{        0,         0,   0,  0, 0, 0 },
 367};
 368
 369
 370static struct tegra_clk_pll_params pll_a_params = {
 371	.input_min = 2000000,
 372	.input_max = 31000000,
 373	.cf_min = 1000000,
 374	.cf_max = 6000000,
 375	.vco_min = 200000000,
 376	.vco_max = 700000000,
 377	.base_reg = PLLA_BASE,
 378	.misc_reg = PLLA_MISC,
 379	.lock_mask = PLL_BASE_LOCK,
 380	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 381	.lock_delay = 300,
 382	.div_nmp = &pllp_nmp,
 383	.freq_table = pll_a_freq_table,
 384	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
 385		 TEGRA_PLL_HAS_LOCK_ENABLE,
 386};
 387
 388static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
 389	{ 12000000,  216000000,  864, 12, 4, 12 },
 390	{ 13000000,  216000000,  864, 13, 4, 12 },
 391	{ 16800000,  216000000,  720, 14, 4, 12 },
 392	{ 19200000,  216000000,  720, 16, 4, 12 },
 393	{ 26000000,  216000000,  864, 26, 4, 12 },
 394	{ 12000000,  594000000,  594, 12, 1, 12 },
 395	{ 13000000,  594000000,  594, 13, 1, 12 },
 396	{ 16800000,  594000000,  495, 14, 1, 12 },
 397	{ 19200000,  594000000,  495, 16, 1, 12 },
 398	{ 26000000,  594000000,  594, 26, 1, 12 },
 399	{ 12000000, 1000000000, 1000, 12, 1, 12 },
 400	{ 13000000, 1000000000, 1000, 13, 1, 12 },
 401	{ 19200000, 1000000000,  625, 12, 1, 12 },
 402	{ 26000000, 1000000000, 1000, 26, 1, 12 },
 403	{        0,          0,    0,  0, 0,  0 },
 404};
 405
 406static struct tegra_clk_pll_params pll_d_params = {
 407	.input_min = 2000000,
 408	.input_max = 40000000,
 409	.cf_min = 1000000,
 410	.cf_max = 6000000,
 411	.vco_min = 500000000,
 412	.vco_max = 1000000000,
 413	.base_reg = PLLD_BASE,
 414	.misc_reg = PLLD_MISC,
 415	.lock_mask = PLL_BASE_LOCK,
 416	.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 417	.lock_delay = 1000,
 418	.div_nmp = &pllp_nmp,
 419	.freq_table = pll_d_freq_table,
 420	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
 421		 TEGRA_PLL_HAS_LOCK_ENABLE,
 422};
 423
 424static struct tegra_clk_pll_params pll_d2_params = {
 425	.input_min = 2000000,
 426	.input_max = 40000000,
 427	.cf_min = 1000000,
 428	.cf_max = 6000000,
 429	.vco_min = 500000000,
 430	.vco_max = 1000000000,
 431	.base_reg = PLLD2_BASE,
 432	.misc_reg = PLLD2_MISC,
 433	.lock_mask = PLL_BASE_LOCK,
 434	.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 435	.lock_delay = 1000,
 436	.div_nmp = &pllp_nmp,
 437	.freq_table = pll_d_freq_table,
 438	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
 439		 TEGRA_PLL_HAS_LOCK_ENABLE,
 440};
 441
 442static const struct pdiv_map pllu_p[] = {
 443	{ .pdiv = 1, .hw_val = 1 },
 444	{ .pdiv = 2, .hw_val = 0 },
 445	{ .pdiv = 0, .hw_val = 0 },
 446};
 447
 448static struct div_nmp pllu_nmp = {
 449	.divm_shift = 0,
 450	.divm_width = 5,
 451	.divn_shift = 8,
 452	.divn_width = 10,
 453	.divp_shift = 20,
 454	.divp_width = 1,
 455};
 456
 457static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
 458	{ 12000000, 480000000, 960, 12, 2, 12 },
 459	{ 13000000, 480000000, 960, 13, 2, 12 },
 460	{ 16800000, 480000000, 400,  7, 2,  5 },
 461	{ 19200000, 480000000, 200,  4, 2,  3 },
 462	{ 26000000, 480000000, 960, 26, 2, 12 },
 463	{        0,         0,   0,  0, 0,  0 },
 464};
 465
 466static struct tegra_clk_pll_params pll_u_params = {
 467	.input_min = 2000000,
 468	.input_max = 40000000,
 469	.cf_min = 1000000,
 470	.cf_max = 6000000,
 471	.vco_min = 480000000,
 472	.vco_max = 960000000,
 473	.base_reg = PLLU_BASE,
 474	.misc_reg = PLLU_MISC,
 475	.lock_mask = PLL_BASE_LOCK,
 476	.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 477	.lock_delay = 1000,
 478	.pdiv_tohw = pllu_p,
 479	.div_nmp = &pllu_nmp,
 480	.freq_table = pll_u_freq_table,
 481	.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
 482		 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 483};
 484
 485static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 486	/* 1 GHz */
 487	{ 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
 488	{ 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
 489	{ 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
 490	{ 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
 491	{ 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
 492	{        0,          0,  0, 0, 0, 0 },
 493};
 494
 495static struct tegra_clk_pll_params pll_x_params = {
 496	.input_min = 12000000,
 497	.input_max = 800000000,
 498	.cf_min = 12000000,
 499	.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
 500	.vco_min = 700000000,
 501	.vco_max = 2400000000U,
 502	.base_reg = PLLX_BASE,
 503	.misc_reg = PLLX_MISC,
 504	.lock_mask = PLL_BASE_LOCK,
 505	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 506	.lock_delay = 300,
 507	.iddq_reg = PLLX_MISC3,
 508	.iddq_bit_idx = PLLX_IDDQ_BIT,
 509	.max_p = PLLXC_SW_MAX_P,
 510	.dyn_ramp_reg = PLLX_MISC2,
 511	.stepa_shift = 16,
 512	.stepb_shift = 24,
 513	.pdiv_tohw = pllxc_p,
 514	.div_nmp = &pllxc_nmp,
 515	.freq_table = pll_x_freq_table,
 516	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
 517};
 518
 519static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 520	/* PLLE special case: use cpcon field to store cml divider value */
 521	{ 336000000, 100000000, 100, 21, 16, 11 },
 522	{ 312000000, 100000000, 200, 26, 24, 13 },
 523	{  12000000, 100000000, 200,  1, 24, 13 },
 524	{         0,         0,   0,  0,  0,  0 },
 525};
 526
 527static const struct pdiv_map plle_p[] = {
 528	{ .pdiv =  1, .hw_val =  0 },
 529	{ .pdiv =  2, .hw_val =  1 },
 530	{ .pdiv =  3, .hw_val =  2 },
 531	{ .pdiv =  4, .hw_val =  3 },
 532	{ .pdiv =  5, .hw_val =  4 },
 533	{ .pdiv =  6, .hw_val =  5 },
 534	{ .pdiv =  8, .hw_val =  6 },
 535	{ .pdiv = 10, .hw_val =  7 },
 536	{ .pdiv = 12, .hw_val =  8 },
 537	{ .pdiv = 16, .hw_val =  9 },
 538	{ .pdiv = 12, .hw_val = 10 },
 539	{ .pdiv = 16, .hw_val = 11 },
 540	{ .pdiv = 20, .hw_val = 12 },
 541	{ .pdiv = 24, .hw_val = 13 },
 542	{ .pdiv = 32, .hw_val = 14 },
 543	{ .pdiv =  0, .hw_val =  0 }
 544};
 545
 546static struct div_nmp plle_nmp = {
 547	.divm_shift = 0,
 548	.divm_width = 8,
 549	.divn_shift = 8,
 550	.divn_width = 8,
 551	.divp_shift = 24,
 552	.divp_width = 4,
 553};
 554
 555static struct tegra_clk_pll_params pll_e_params = {
 556	.input_min = 12000000,
 557	.input_max = 1000000000,
 558	.cf_min = 12000000,
 559	.cf_max = 75000000,
 560	.vco_min = 1600000000,
 561	.vco_max = 2400000000U,
 562	.base_reg = PLLE_BASE,
 563	.misc_reg = PLLE_MISC,
 564	.aux_reg = PLLE_AUX,
 565	.lock_mask = PLLE_MISC_LOCK,
 566	.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 567	.lock_delay = 300,
 568	.pdiv_tohw = plle_p,
 569	.div_nmp = &plle_nmp,
 570	.freq_table = pll_e_freq_table,
 571	.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
 572	.fixed_rate = 100000000,
 573};
 574
 575static struct div_nmp pllre_nmp = {
 576	.divm_shift = 0,
 577	.divm_width = 8,
 578	.divn_shift = 8,
 579	.divn_width = 8,
 580	.divp_shift = 16,
 581	.divp_width = 4,
 582};
 583
 584static struct tegra_clk_pll_params pll_re_vco_params = {
 585	.input_min = 12000000,
 586	.input_max = 1000000000,
 587	.cf_min = 12000000,
 588	.cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
 589	.vco_min = 300000000,
 590	.vco_max = 600000000,
 591	.base_reg = PLLRE_BASE,
 592	.misc_reg = PLLRE_MISC,
 593	.lock_mask = PLLRE_MISC_LOCK,
 594	.lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
 595	.lock_delay = 300,
 596	.iddq_reg = PLLRE_MISC,
 597	.iddq_bit_idx = PLLRE_IDDQ_BIT,
 598	.div_nmp = &pllre_nmp,
 599	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
 600		 TEGRA_PLL_LOCK_MISC,
 601};
 602
 603/* possible OSC frequencies in Hz */
 604static unsigned long tegra114_input_freq[] = {
 605	[ 0] = 13000000,
 606	[ 1] = 16800000,
 607	[ 4] = 19200000,
 608	[ 5] = 38400000,
 609	[ 8] = 12000000,
 610	[ 9] = 48000000,
 611	[12] = 26000000,
 612};
 613
 614#define MASK(x) (BIT(x) - 1)
 615
 616/* peripheral mux definitions */
 617
 618static const char *mux_plld_out0_plld2_out0[] = {
 619	"pll_d_out0", "pll_d2_out0",
 620};
 621#define mux_plld_out0_plld2_out0_idx NULL
 622
 623static const char *mux_pllmcp_clkm[] = {
 624	"pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
 625};
 626
 627static const struct clk_div_table pll_re_div_table[] = {
 628	{ .val = 0, .div = 1 },
 629	{ .val = 1, .div = 2 },
 630	{ .val = 2, .div = 3 },
 631	{ .val = 3, .div = 4 },
 632	{ .val = 4, .div = 5 },
 633	{ .val = 5, .div = 6 },
 634	{ .val = 0, .div = 0 },
 635};
 636
 637static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
 638	[tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
 639	[tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
 640	[tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
 641	[tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
 642	[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
 643	[tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
 644	[tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
 645	[tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
 646	[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
 647	[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
 648	[tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
 649	[tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
 650	[tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
 651	[tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
 652	[tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
 653	[tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
 654	[tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
 655	[tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
 656	[tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
 657	[tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
 658	[tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
 659	[tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
 660	[tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
 661	[tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
 662	[tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
 663	[tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
 664	[tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
 665	[tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
 666	[tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
 667	[tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
 668	[tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
 669	[tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
 670	[tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
 671	[tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
 672	[tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
 673	[tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
 674	[tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
 675	[tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
 676	[tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
 677	[tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
 678	[tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
 679	[tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
 680	[tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
 681	[tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
 682	[tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
 683	[tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
 684	[tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
 685	[tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
 686	[tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
 687	[tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
 688	[tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
 689	[tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
 690	[tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
 691	[tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
 692	[tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
 693	[tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
 694	[tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
 695	[tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
 696	[tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
 697	[tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
 698	[tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
 699	[tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
 700	[tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
 701	[tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
 702	[tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
 703	[tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
 704	[tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
 705	[tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
 706	[tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
 707	[tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
 708	[tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
 709	[tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
 710	[tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
 711	[tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
 712	[tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
 713	[tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
 714	[tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
 715	[tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
 716	[tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
 717	[tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
 718	[tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
 719	[tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
 720	[tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
 721	[tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
 722	[tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
 723	[tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
 724	[tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
 725	[tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
 726	[tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
 727	[tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
 728	[tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
 729	[tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
 730	[tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
 731	[tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
 732	[tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
 733	[tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
 734	[tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
 735	[tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
 736	[tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
 737	[tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
 738	[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
 739	[tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
 740	[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
 741	[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
 742	[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
 743	[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
 744	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
 745	[tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
 746	[tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
 747	[tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
 748	[tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
 749	[tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
 750	[tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
 751	[tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
 752	[tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
 753	[tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
 754	[tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
 755	[tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
 756	[tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
 757	[tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
 758	[tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
 759	[tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
 760	[tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
 761	[tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
 762	[tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
 763	[tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
 764	[tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
 765	[tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
 766	[tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
 767	[tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
 768	[tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
 769	[tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
 770	[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
 771	[tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
 772	[tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
 773	[tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
 774	[tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
 775	[tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
 776	[tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
 777	[tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
 778	[tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
 779	[tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
 780	[tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
 781	[tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
 782	[tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
 783	[tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
 784	[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
 785	[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
 786	[tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
 787	[tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
 788	[tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
 789	[tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
 790	[tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
 791	[tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
 792	[tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
 793	[tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
 794	[tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
 795	[tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
 796	[tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
 797	[tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
 798	[tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
 799	[tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
 800	[tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
 801	[tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
 802	[tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
 803	[tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
 804	[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
 805	[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
 806	[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
 807};
 808
 809static struct tegra_devclk devclks[] __initdata = {
 810	{ .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
 811	{ .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
 812	{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
 813	{ .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
 814	{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
 815	{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
 816	{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
 817	{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
 818	{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
 819	{ .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
 820	{ .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
 821	{ .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
 822	{ .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
 823	{ .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
 824	{ .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
 825	{ .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
 826	{ .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
 827	{ .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
 828	{ .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
 829	{ .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
 830	{ .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
 831	{ .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
 832	{ .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
 833	{ .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
 834	{ .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
 835	{ .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
 836	{ .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
 837	{ .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
 838	{ .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
 839	{ .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
 840	{ .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
 841	{ .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
 842	{ .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
 843	{ .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
 844	{ .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
 845	{ .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
 846	{ .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
 847	{ .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
 848	{ .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
 849	{ .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
 850	{ .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
 851	{ .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
 852	{ .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
 853	{ .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
 854	{ .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
 855	{ .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
 856	{ .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
 857	{ .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
 858	{ .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
 859	{ .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
 860	{ .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
 861	{ .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
 862	{ .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
 863	{ .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
 864	{ .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
 865	{ .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
 866	{ .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
 867	{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
 868	{ .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
 869	{ .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
 870	{ .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
 871	{ .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
 872	{ .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
 873};
 874
 875static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
 876	"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
 877};
 878static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
 879	[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
 880};
 881
 882static struct tegra_audio_clk_info tegra114_audio_plls[] = {
 883	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
 884};
 885
 886static struct clk **clks;
 887
 888static unsigned long osc_freq;
 889static unsigned long pll_ref_freq;
 890
 891static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
 892{
 893	struct clk *clk;
 894
 895	/* clk_32k */
 896	clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
 897	clks[TEGRA114_CLK_CLK_32K] = clk;
 898}
 899
 900static void __init tegra114_pll_init(void __iomem *clk_base,
 901				     void __iomem *pmc)
 902{
 903	struct clk *clk;
 904
 905	/* PLLC */
 906	clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
 907			pmc, 0, &pll_c_params, NULL);
 908	clks[TEGRA114_CLK_PLL_C] = clk;
 909
 910	/* PLLC_OUT1 */
 911	clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
 912			clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 913			8, 8, 1, NULL);
 914	clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
 915				clk_base + PLLC_OUT, 1, 0,
 916				CLK_SET_RATE_PARENT, 0, NULL);
 917	clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
 918
 919	/* PLLC2 */
 920	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
 921			     &pll_c2_params, NULL);
 922	clks[TEGRA114_CLK_PLL_C2] = clk;
 923
 924	/* PLLC3 */
 925	clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
 926			     &pll_c3_params, NULL);
 927	clks[TEGRA114_CLK_PLL_C3] = clk;
 928
 929	/* PLLM */
 930	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
 931			     CLK_SET_RATE_GATE, &pll_m_params, NULL);
 932	clks[TEGRA114_CLK_PLL_M] = clk;
 933
 934	/* PLLM_OUT1 */
 935	clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
 936				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 937				8, 8, 1, NULL);
 938	clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
 939				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
 940				CLK_SET_RATE_PARENT, 0, NULL);
 941	clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
 942
 943	/* PLLM_UD */
 944	clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
 945					CLK_SET_RATE_PARENT, 1, 1);
 946
 947	/* PLLU */
 948	clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
 949					       &pll_u_params, &pll_u_lock);
 950	clks[TEGRA114_CLK_PLL_U] = clk;
 951
 952	/* PLLU_480M */
 953	clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
 954				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
 955				22, 0, &pll_u_lock);
 956	clks[TEGRA114_CLK_PLL_U_480M] = clk;
 957
 958	/* PLLU_60M */
 959	clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
 960					CLK_SET_RATE_PARENT, 1, 8);
 961	clks[TEGRA114_CLK_PLL_U_60M] = clk;
 962
 963	/* PLLU_48M */
 964	clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
 965					CLK_SET_RATE_PARENT, 1, 10);
 966	clks[TEGRA114_CLK_PLL_U_48M] = clk;
 967
 968	/* PLLU_12M */
 969	clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
 970					CLK_SET_RATE_PARENT, 1, 40);
 971	clks[TEGRA114_CLK_PLL_U_12M] = clk;
 972
 973	/* PLLD */
 974	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
 975			    &pll_d_params, &pll_d_lock);
 976	clks[TEGRA114_CLK_PLL_D] = clk;
 977
 978	/* PLLD_OUT0 */
 979	clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
 980					CLK_SET_RATE_PARENT, 1, 2);
 981	clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
 982
 983	/* PLLD2 */
 984	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
 985			    &pll_d2_params, &pll_d2_lock);
 986	clks[TEGRA114_CLK_PLL_D2] = clk;
 987
 988	/* PLLD2_OUT0 */
 989	clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
 990					CLK_SET_RATE_PARENT, 1, 2);
 991	clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
 992
 993	/* PLLRE */
 994	clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
 995			     0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
 996	clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
 997
 998	clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
 999					 clk_base + PLLRE_BASE, 16, 4, 0,
1000					 pll_re_div_table, &pll_re_lock);
1001	clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
1002
1003	/* PLLE */
1004	clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
1005				      clk_base, 0, &pll_e_params, NULL);
1006	clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1007}
1008
1009#define CLK_SOURCE_VI_SENSOR 0x1a8
1010
1011static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1012	MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1013};
1014
1015static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1016					    void __iomem *pmc_base)
1017{
1018	struct clk *clk;
1019	struct tegra_periph_init_data *data;
1020	unsigned int i;
1021
1022	/* xusb_ss_div2 */
1023	clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1024					1, 2);
1025	clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
1026
1027	/* dsia mux */
1028	clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1029			       ARRAY_SIZE(mux_plld_out0_plld2_out0),
1030			       CLK_SET_RATE_NO_REPARENT,
1031			       clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1032	clks[TEGRA114_CLK_DSIA_MUX] = clk;
1033
1034	/* dsib mux */
1035	clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1036			       ARRAY_SIZE(mux_plld_out0_plld2_out0),
1037			       CLK_SET_RATE_NO_REPARENT,
1038			       clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1039	clks[TEGRA114_CLK_DSIB_MUX] = clk;
1040
1041	clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1042					     0, 48, periph_clk_enb_refcnt);
1043	clks[TEGRA114_CLK_DSIA] = clk;
1044
1045	clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1046					     0, 82, periph_clk_enb_refcnt);
1047	clks[TEGRA114_CLK_DSIB] = clk;
1048
1049	/* emc mux */
1050	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1051			       ARRAY_SIZE(mux_pllmcp_clkm),
1052			       CLK_SET_RATE_NO_REPARENT,
1053			       clk_base + CLK_SOURCE_EMC,
1054			       29, 3, 0, &emc_lock);
1055
1056	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1057				    &emc_lock);
1058	clks[TEGRA114_CLK_MC] = clk;
1059
1060	clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1061					     CLK_SET_RATE_PARENT, 56,
1062					     periph_clk_enb_refcnt);
1063	clks[TEGRA114_CLK_MIPI_CAL] = clk;
1064
1065	for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1066		data = &tegra_periph_clk_list[i];
1067		clk = tegra_clk_register_periph_data(clk_base, data);
1068		clks[data->clk_id] = clk;
1069	}
1070
1071	tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1072				&pll_p_params);
1073}
1074
1075/* Tegra114 CPU clock and reset control functions */
1076static void tegra114_wait_cpu_in_reset(u32 cpu)
1077{
1078	unsigned int reg;
1079
1080	do {
1081		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1082		cpu_relax();
1083	} while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1084}
1085
1086static void tegra114_disable_cpu_clock(u32 cpu)
1087{
1088	/* flow controller would take care in the power sequence. */
1089}
1090
1091#ifdef CONFIG_PM_SLEEP
1092static void tegra114_cpu_clock_suspend(void)
1093{
1094	/* switch coresite to clk_m, save off original source */
1095	tegra114_cpu_clk_sctx.clk_csite_src =
1096				readl(clk_base + CLK_SOURCE_CSITE);
1097	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1098
1099	tegra114_cpu_clk_sctx.cclkg_burst =
1100				readl(clk_base + CCLKG_BURST_POLICY);
1101	tegra114_cpu_clk_sctx.cclkg_divider =
1102				readl(clk_base + CCLKG_BURST_POLICY + 4);
1103}
1104
1105static void tegra114_cpu_clock_resume(void)
1106{
1107	writel(tegra114_cpu_clk_sctx.clk_csite_src,
1108					clk_base + CLK_SOURCE_CSITE);
1109
1110	writel(tegra114_cpu_clk_sctx.cclkg_burst,
1111					clk_base + CCLKG_BURST_POLICY);
1112	writel(tegra114_cpu_clk_sctx.cclkg_divider,
1113					clk_base + CCLKG_BURST_POLICY + 4);
1114}
1115#endif
1116
1117static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1118	.wait_for_reset	= tegra114_wait_cpu_in_reset,
1119	.disable_clock	= tegra114_disable_cpu_clock,
1120#ifdef CONFIG_PM_SLEEP
1121	.suspend	= tegra114_cpu_clock_suspend,
1122	.resume		= tegra114_cpu_clock_resume,
1123#endif
1124};
1125
1126static const struct of_device_id pmc_match[] __initconst = {
1127	{ .compatible = "nvidia,tegra114-pmc" },
1128	{ },
1129};
1130
1131/*
1132 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
1133 * breaks
1134 */
1135static struct tegra_clk_init_table init_table[] __initdata = {
1136	{ TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
1137	{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
1138	{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
1139	{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
1140	{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
1141	{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
1142	{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1143	{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1144	{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1145	{ TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1146	{ TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1147	{ TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
1148	{ TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
1149	{ TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
1150	{ TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
1151	{ TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
1152	{ TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1153	{ TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1154	{ TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1155	{ TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1156	{ TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
1157	{ TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
1158	{ TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
1159	{ TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
1160	{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1161	{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1162	{ TEGRA114_CLK_VDE, TEGRA114_CLK_PLL_P, 408000000, 0 },
1163	{ TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1164	{ TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1165	{ TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1166	{ TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1167	{ TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1168	{ TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1169	{ TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1170	{ TEGRA114_CLK_PWM, TEGRA114_CLK_PLL_P, 408000000, 0 },
1171	/* must be the last entry */
1172	{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1173};
1174
1175static void __init tegra114_clock_apply_init_table(void)
1176{
1177	tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1178}
1179
1180/**
1181 * tegra114_car_barrier - wait for pending writes to the CAR to complete
1182 *
1183 * Wait for any outstanding writes to the CAR MMIO space from this CPU
1184 * to complete before continuing execution.  No return value.
1185 */
1186static void tegra114_car_barrier(void)
1187{
1188	wmb();		/* probably unnecessary */
1189	readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1190}
1191
1192/**
1193 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1194 *
1195 * When the CPU rail voltage is in the high-voltage range, use the
1196 * built-in hardwired clock propagation delays in the CPU clock
1197 * shaper.  No return value.
1198 */
1199void tegra114_clock_tune_cpu_trimmers_high(void)
1200{
1201	u32 select = 0;
1202
1203	/* Use hardwired rise->rise & fall->fall clock propagation delays */
1204	select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1205		    CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1206		    CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1207	writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1208
1209	tegra114_car_barrier();
1210}
1211EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
1212
1213/**
1214 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1215 *
1216 * When the CPU rail voltage is in the low-voltage range, use the
1217 * extended clock propagation delays set by
1218 * tegra114_clock_tune_cpu_trimmers_init().  The intention is to
1219 * maintain the input clock duty cycle that the FCPU subsystem
1220 * expects.  No return value.
1221 */
1222void tegra114_clock_tune_cpu_trimmers_low(void)
1223{
1224	u32 select = 0;
1225
1226	/*
1227	 * Use software-specified rise->rise & fall->fall clock
1228	 * propagation delays (from
1229	 * tegra114_clock_tune_cpu_trimmers_init()
1230	 */
1231	select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1232		   CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1233		   CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1234	writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1235
1236	tegra114_car_barrier();
1237}
1238EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
1239
1240/**
1241 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1242 *
1243 * Program extended clock propagation delays into the FCPU clock
1244 * shaper and enable them.  XXX Define the purpose - peak current
1245 * reduction?  No return value.
1246 */
1247/* XXX Initial voltage rail state assumption issues? */
1248void tegra114_clock_tune_cpu_trimmers_init(void)
1249{
1250	u32 dr = 0, r = 0;
1251
1252	/* Increment the rise->rise clock delay by four steps */
1253	r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
1254	      CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
1255	      CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
1256	writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1257
1258	/*
1259	 * Use the rise->rise clock propagation delay specified in the
1260	 * r field
1261	 */
1262	dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1263	       CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1264	       CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1265	writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1266
1267	tegra114_clock_tune_cpu_trimmers_low();
1268}
1269EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
1270
1271/**
1272 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1273 *
1274 * Assert the reset line of the DFLL's DVCO.  No return value.
1275 */
1276static void tegra114_clock_assert_dfll_dvco_reset(void)
1277{
1278	u32 v;
1279
1280	v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1281	v |= (1 << DVFS_DFLL_RESET_SHIFT);
1282	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1283	tegra114_car_barrier();
1284}
1285
1286/**
1287 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1288 *
1289 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1290 * operate.  No return value.
1291 */
1292static void tegra114_clock_deassert_dfll_dvco_reset(void)
1293{
1294	u32 v;
1295
1296	v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1297	v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1298	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1299	tegra114_car_barrier();
1300}
1301
1302static int tegra114_reset_assert(unsigned long id)
1303{
1304	if (id == TEGRA114_RST_DFLL_DVCO)
1305		tegra114_clock_assert_dfll_dvco_reset();
1306	else
1307		return -EINVAL;
1308
1309	return 0;
1310}
1311
1312static int tegra114_reset_deassert(unsigned long id)
1313{
1314	if (id == TEGRA114_RST_DFLL_DVCO)
1315		tegra114_clock_deassert_dfll_dvco_reset();
1316	else
1317		return -EINVAL;
1318
1319	return 0;
1320}
1321
1322static void __init tegra114_clock_init(struct device_node *np)
1323{
1324	struct device_node *node;
1325
1326	clk_base = of_iomap(np, 0);
1327	if (!clk_base) {
1328		pr_err("ioremap tegra114 CAR failed\n");
1329		return;
1330	}
1331
1332	node = of_find_matching_node(NULL, pmc_match);
1333	if (!node) {
1334		pr_err("Failed to find pmc node\n");
1335		WARN_ON(1);
1336		return;
1337	}
1338
1339	pmc_base = of_iomap(node, 0);
1340	of_node_put(node);
1341	if (!pmc_base) {
1342		pr_err("Can't map pmc registers\n");
1343		WARN_ON(1);
1344		return;
1345	}
1346
1347	clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1348				TEGRA114_CLK_PERIPH_BANKS);
1349	if (!clks)
1350		return;
1351
1352	if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
1353			       ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
1354			       &pll_ref_freq) < 0)
1355		return;
1356
1357	tegra114_fixed_clk_init(clk_base);
1358	tegra114_pll_init(clk_base, pmc_base);
1359	tegra114_periph_clk_init(clk_base, pmc_base);
1360	tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
1361			     tegra114_audio_plls,
1362			     ARRAY_SIZE(tegra114_audio_plls), 24000000);
1363	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1364					&pll_x_params);
1365
1366	tegra_init_special_resets(1, tegra114_reset_assert,
1367				  tegra114_reset_deassert);
1368
1369	tegra_add_of_provider(np, of_clk_src_onecell_get);
1370	tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1371
1372	tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1373
1374	tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1375}
1376CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);