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clk-pll.c
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linux-6.19.14/drivers/clk/tegra/clk-pll.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#include <linux/slab.h> 7#include <linux/io.h> 8#include <linux/delay.h> 9#include <linux/err.h> 10#include <linux/clk.h> 11#include <linux/clk-provider.h> 12 13#include "clk.h" 14 15#define PLL_BASE_BYPASS BIT(31) 16#define PLL_BASE_ENABLE BIT(30) 17#define PLL_BASE_REF_ENABLE BIT(29) 18#define PLL_BASE_OVERRIDE BIT(28) 19 20#define PLL_BASE_DIVP_SHIFT 20 21#define PLL_BASE_DIVP_WIDTH 3 22#define PLL_BASE_DIVN_SHIFT 8 23#define PLL_BASE_DIVN_WIDTH 10 24#define PLL_BASE_DIVM_SHIFT 0 25#define PLL_BASE_DIVM_WIDTH 5 26#define PLLU_POST_DIVP_MASK 0x1 27 28#define PLL_MISC_DCCON_SHIFT 20 29#define PLL_MISC_CPCON_SHIFT 8 30#define PLL_MISC_CPCON_WIDTH 4 31#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 32#define PLL_MISC_LFCON_SHIFT 4 33#define PLL_MISC_LFCON_WIDTH 4 34#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 35#define PLL_MISC_VCOCON_SHIFT 0 36#define PLL_MISC_VCOCON_WIDTH 4 37#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 38 39#define OUT_OF_TABLE_CPCON 8 40 41#define PMC_PLLP_WB0_OVERRIDE 0xf8 42#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 43#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 44 45#define PLL_POST_LOCK_DELAY 50 46 47#define PLLDU_LFCON_SET_DIVN 600 48 49#define PLLE_BASE_DIVCML_SHIFT 24 50#define PLLE_BASE_DIVCML_MASK 0xf 51#define PLLE_BASE_DIVP_SHIFT 16 52#define PLLE_BASE_DIVP_WIDTH 6 53#define PLLE_BASE_DIVN_SHIFT 8 54#define PLLE_BASE_DIVN_WIDTH 8 55#define PLLE_BASE_DIVM_SHIFT 0 56#define PLLE_BASE_DIVM_WIDTH 8 57#define PLLE_BASE_ENABLE BIT(31) 58 59#define PLLE_MISC_SETUP_BASE_SHIFT 16 60#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 61#define PLLE_MISC_LOCK_ENABLE BIT(9) 62#define PLLE_MISC_READY BIT(15) 63#define PLLE_MISC_SETUP_EX_SHIFT 2 64#define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 65#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 66 PLLE_MISC_SETUP_EX_MASK) 67#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 68 69#define PLLE_SS_CTRL 0x68 70#define PLLE_SS_CNTL_BYPASS_SS BIT(10) 71#define PLLE_SS_CNTL_INTERP_RESET BIT(11) 72#define PLLE_SS_CNTL_SSC_BYP BIT(12) 73#define PLLE_SS_CNTL_CENTER BIT(14) 74#define PLLE_SS_CNTL_INVERT BIT(15) 75#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ 76 PLLE_SS_CNTL_SSC_BYP) 77#define PLLE_SS_MAX_MASK 0x1ff 78#define PLLE_SS_MAX_VAL_TEGRA114 0x25 79#define PLLE_SS_MAX_VAL_TEGRA210 0x21 80#define PLLE_SS_INC_MASK (0xff << 16) 81#define PLLE_SS_INC_VAL (0x1 << 16) 82#define PLLE_SS_INCINTRV_MASK (0x3f << 24) 83#define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24) 84#define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24) 85#define PLLE_SS_COEFFICIENTS_MASK \ 86 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) 87#define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \ 88 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\ 89 PLLE_SS_INCINTRV_VAL_TEGRA114) 90#define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \ 91 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\ 92 PLLE_SS_INCINTRV_VAL_TEGRA210) 93 94#define PLLE_AUX_PLLP_SEL BIT(2) 95#define PLLE_AUX_USE_LOCKDET BIT(3) 96#define PLLE_AUX_ENABLE_SWCTL BIT(4) 97#define PLLE_AUX_SS_SWCTL BIT(6) 98#define PLLE_AUX_SEQ_ENABLE BIT(24) 99#define PLLE_AUX_SEQ_START_STATE BIT(25) 100#define PLLE_AUX_PLLRE_SEL BIT(28) 101#define PLLE_AUX_SS_SEQ_INCLUDE BIT(31) 102 103#define XUSBIO_PLL_CFG0 0x51c 104#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 105#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 106#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 107#define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 108#define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 109 110#define SATA_PLL_CFG0 0x490 111#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 112#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 113#define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 114#define SATA_PLL_CFG0_SEQ_START_STATE BIT(25) 115 116#define PLLE_MISC_PLLE_PTS BIT(8) 117#define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 118#define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 119#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 120#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 121#define PLLE_MISC_VREG_CTRL_SHIFT 2 122#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 123 124#define PLLCX_MISC_STROBE BIT(31) 125#define PLLCX_MISC_RESET BIT(30) 126#define PLLCX_MISC_SDM_DIV_SHIFT 28 127#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 128#define PLLCX_MISC_FILT_DIV_SHIFT 26 129#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 130#define PLLCX_MISC_ALPHA_SHIFT 18 131#define PLLCX_MISC_DIV_LOW_RANGE \ 132 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 133 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 134#define PLLCX_MISC_DIV_HIGH_RANGE \ 135 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 136 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 137#define PLLCX_MISC_COEF_LOW_RANGE \ 138 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 139#define PLLCX_MISC_KA_SHIFT 2 140#define PLLCX_MISC_KB_SHIFT 9 141#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 142 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 143 PLLCX_MISC_DIV_LOW_RANGE | \ 144 PLLCX_MISC_RESET) 145#define PLLCX_MISC1_DEFAULT 0x000d2308 146#define PLLCX_MISC2_DEFAULT 0x30211200 147#define PLLCX_MISC3_DEFAULT 0x200 148 149#define PMC_SATA_PWRGT 0x1ac 150#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 151#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 152 153#define PLLSS_MISC_KCP 0 154#define PLLSS_MISC_KVCO 0 155#define PLLSS_MISC_SETUP 0 156#define PLLSS_EN_SDM 0 157#define PLLSS_EN_SSC 0 158#define PLLSS_EN_DITHER2 0 159#define PLLSS_EN_DITHER 1 160#define PLLSS_SDM_RESET 0 161#define PLLSS_CLAMP 0 162#define PLLSS_SDM_SSC_MAX 0 163#define PLLSS_SDM_SSC_MIN 0 164#define PLLSS_SDM_SSC_STEP 0 165#define PLLSS_SDM_DIN 0 166#define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \ 167 (PLLSS_MISC_KVCO << 24) | \ 168 PLLSS_MISC_SETUP) 169#define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \ 170 (PLLSS_EN_SSC << 30) | \ 171 (PLLSS_EN_DITHER2 << 29) | \ 172 (PLLSS_EN_DITHER << 28) | \ 173 (PLLSS_SDM_RESET) << 27 | \ 174 (PLLSS_CLAMP << 22)) 175#define PLLSS_CTRL1_DEFAULT \ 176 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN) 177#define PLLSS_CTRL2_DEFAULT \ 178 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN) 179#define PLLSS_LOCK_OVERRIDE BIT(24) 180#define PLLSS_REF_SRC_SEL_SHIFT 25 181#define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 182 183#define UTMIP_PLL_CFG1 0x484 184#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 185#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) 186#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 187#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 188#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 189#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 190#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 191 192#define UTMIP_PLL_CFG2 0x488 193#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) 194#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 195#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 196#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) 197#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 198#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) 199#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 200#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) 201#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) 202#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) 203#define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30) 204 205#define UTMIPLL_HW_PWRDN_CFG0 0x52c 206#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 207#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 208#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 209#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 210#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 211#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 212#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 213#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 214 215#define PLLU_HW_PWRDN_CFG0 0x530 216#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) 217#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 218#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 219#define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) 220#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 221#define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) 222 223#define XUSB_PLL_CFG0 0x534 224#define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff 225#define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14) 226 227#define PLLU_BASE_CLKENABLE_USB BIT(21) 228#define PLLU_BASE_OVERRIDE BIT(24) 229 230#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 231#define pll_readl_base(p) pll_readl(p->params->base_reg, p) 232#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 233#define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 234#define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p) 235#define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p) 236 237#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 238#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 239#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 240#define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 241#define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p) 242#define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p) 243 244#define mask(w) ((1 << (w)) - 1) 245#define divm_mask(p) mask(p->params->div_nmp->divm_width) 246#define divn_mask(p) mask(p->params->div_nmp->divn_width) 247#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 248 mask(p->params->div_nmp->divp_width)) 249#define sdm_din_mask(p) p->params->sdm_din_mask 250#define sdm_en_mask(p) p->params->sdm_ctrl_en_mask 251 252#define divm_shift(p) (p)->params->div_nmp->divm_shift 253#define divn_shift(p) (p)->params->div_nmp->divn_shift 254#define divp_shift(p) (p)->params->div_nmp->divp_shift 255 256#define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 257#define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 258#define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 259 260#define divm_max(p) (divm_mask(p)) 261#define divn_max(p) (divn_mask(p)) 262#define divp_max(p) (1 << (divp_mask(p))) 263 264#define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 265#define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 266 267static struct div_nmp default_nmp = { 268 .divn_shift = PLL_BASE_DIVN_SHIFT, 269 .divn_width = PLL_BASE_DIVN_WIDTH, 270 .divm_shift = PLL_BASE_DIVM_SHIFT, 271 .divm_width = PLL_BASE_DIVM_WIDTH, 272 .divp_shift = PLL_BASE_DIVP_SHIFT, 273 .divp_width = PLL_BASE_DIVP_WIDTH, 274}; 275 276static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 277{ 278 u32 val; 279 280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) 281 return; 282 283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 284 return; 285 286 val = pll_readl_misc(pll); 287 val |= BIT(pll->params->lock_enable_bit_idx); 288 pll_writel_misc(val, pll); 289} 290 291static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 292{ 293 int i; 294 u32 val, lock_mask; 295 void __iomem *lock_addr; 296 297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { 298 udelay(pll->params->lock_delay); 299 return 0; 300 } 301 302 lock_addr = pll->clk_base; 303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) 304 lock_addr += pll->params->misc_reg; 305 else 306 lock_addr += pll->params->base_reg; 307 308 lock_mask = pll->params->lock_mask; 309 310 for (i = 0; i < pll->params->lock_delay; i++) { 311 val = readl_relaxed(lock_addr); 312 if ((val & lock_mask) == lock_mask) { 313 udelay(PLL_POST_LOCK_DELAY); 314 return 0; 315 } 316 udelay(2); /* timeout = 2 * lock time */ 317 } 318 319 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 320 clk_hw_get_name(&pll->hw)); 321 322 return -1; 323} 324 325int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) 326{ 327 return clk_pll_wait_for_lock(pll); 328} 329 330static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll) 331{ 332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 333 334 return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) && 335 !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE); 336} 337 338static int clk_pll_is_enabled(struct clk_hw *hw) 339{ 340 struct tegra_clk_pll *pll = to_clk_pll(hw); 341 u32 val; 342 343 /* 344 * Power Management Controller (PMC) can override the PLLM clock 345 * settings, including the enable-state. The PLLM is enabled when 346 * PLLM's CaR state is ON and when PLLM isn't gated by PMC. 347 */ 348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll)) 349 return 0; 350 351 val = pll_readl_base(pll); 352 353 return val & PLL_BASE_ENABLE ? 1 : 0; 354} 355 356static void _clk_pll_enable(struct clk_hw *hw) 357{ 358 struct tegra_clk_pll *pll = to_clk_pll(hw); 359 u32 val; 360 361 if (pll->params->iddq_reg) { 362 val = pll_readl(pll->params->iddq_reg, pll); 363 val &= ~BIT(pll->params->iddq_bit_idx); 364 pll_writel(val, pll->params->iddq_reg, pll); 365 udelay(5); 366 } 367 368 if (pll->params->reset_reg) { 369 val = pll_readl(pll->params->reset_reg, pll); 370 val &= ~BIT(pll->params->reset_bit_idx); 371 pll_writel(val, pll->params->reset_reg, pll); 372 } 373 374 clk_pll_enable_lock(pll); 375 376 val = pll_readl_base(pll); 377 if (pll->params->flags & TEGRA_PLL_BYPASS) 378 val &= ~PLL_BASE_BYPASS; 379 val |= PLL_BASE_ENABLE; 380 pll_writel_base(val, pll); 381 382 if (pll->params->flags & TEGRA_PLLM) { 383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 384 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 386 } 387} 388 389static void _clk_pll_disable(struct clk_hw *hw) 390{ 391 struct tegra_clk_pll *pll = to_clk_pll(hw); 392 u32 val; 393 394 val = pll_readl_base(pll); 395 if (pll->params->flags & TEGRA_PLL_BYPASS) 396 val &= ~PLL_BASE_BYPASS; 397 val &= ~PLL_BASE_ENABLE; 398 pll_writel_base(val, pll); 399 400 if (pll->params->flags & TEGRA_PLLM) { 401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 402 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 404 } 405 406 if (pll->params->reset_reg) { 407 val = pll_readl(pll->params->reset_reg, pll); 408 val |= BIT(pll->params->reset_bit_idx); 409 pll_writel(val, pll->params->reset_reg, pll); 410 } 411 412 if (pll->params->iddq_reg) { 413 val = pll_readl(pll->params->iddq_reg, pll); 414 val |= BIT(pll->params->iddq_bit_idx); 415 pll_writel(val, pll->params->iddq_reg, pll); 416 udelay(2); 417 } 418} 419 420static void pll_clk_start_ss(struct tegra_clk_pll *pll) 421{ 422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { 423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); 424 425 val |= pll->params->ssc_ctrl_en_mask; 426 pll_writel(val, pll->params->ssc_ctrl_reg, pll); 427 } 428} 429 430static void pll_clk_stop_ss(struct tegra_clk_pll *pll) 431{ 432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { 433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); 434 435 val &= ~pll->params->ssc_ctrl_en_mask; 436 pll_writel(val, pll->params->ssc_ctrl_reg, pll); 437 } 438} 439 440static int clk_pll_enable(struct clk_hw *hw) 441{ 442 struct tegra_clk_pll *pll = to_clk_pll(hw); 443 unsigned long flags = 0; 444 int ret; 445 446 if (clk_pll_is_enabled(hw)) 447 return 0; 448 449 if (pll->lock) 450 spin_lock_irqsave(pll->lock, flags); 451 452 _clk_pll_enable(hw); 453 454 ret = clk_pll_wait_for_lock(pll); 455 456 pll_clk_start_ss(pll); 457 458 if (pll->lock) 459 spin_unlock_irqrestore(pll->lock, flags); 460 461 return ret; 462} 463 464static void clk_pll_disable(struct clk_hw *hw) 465{ 466 struct tegra_clk_pll *pll = to_clk_pll(hw); 467 unsigned long flags = 0; 468 469 if (pll->lock) 470 spin_lock_irqsave(pll->lock, flags); 471 472 pll_clk_stop_ss(pll); 473 474 _clk_pll_disable(hw); 475 476 if (pll->lock) 477 spin_unlock_irqrestore(pll->lock, flags); 478} 479 480static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 481{ 482 struct tegra_clk_pll *pll = to_clk_pll(hw); 483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 484 485 if (p_tohw) { 486 while (p_tohw->pdiv) { 487 if (p_div <= p_tohw->pdiv) 488 return p_tohw->hw_val; 489 p_tohw++; 490 } 491 return -EINVAL; 492 } 493 return -EINVAL; 494} 495 496int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div) 497{ 498 return _p_div_to_hw(&pll->hw, p_div); 499} 500 501static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 502{ 503 struct tegra_clk_pll *pll = to_clk_pll(hw); 504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 505 506 if (p_tohw) { 507 while (p_tohw->pdiv) { 508 if (p_div_hw == p_tohw->hw_val) 509 return p_tohw->pdiv; 510 p_tohw++; 511 } 512 return -EINVAL; 513 } 514 515 return 1 << p_div_hw; 516} 517 518static int _get_table_rate(struct clk_hw *hw, 519 struct tegra_clk_pll_freq_table *cfg, 520 unsigned long rate, unsigned long parent_rate) 521{ 522 struct tegra_clk_pll *pll = to_clk_pll(hw); 523 struct tegra_clk_pll_freq_table *sel; 524 int p; 525 526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 527 if (sel->input_rate == parent_rate && 528 sel->output_rate == rate) 529 break; 530 531 if (sel->input_rate == 0) 532 return -EINVAL; 533 534 if (pll->params->pdiv_tohw) { 535 p = _p_div_to_hw(hw, sel->p); 536 if (p < 0) 537 return p; 538 } else { 539 p = ilog2(sel->p); 540 } 541 542 cfg->input_rate = sel->input_rate; 543 cfg->output_rate = sel->output_rate; 544 cfg->m = sel->m; 545 cfg->n = sel->n; 546 cfg->p = p; 547 cfg->cpcon = sel->cpcon; 548 cfg->sdm_data = sel->sdm_data; 549 550 return 0; 551} 552 553static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 554 unsigned long rate, unsigned long parent_rate) 555{ 556 struct tegra_clk_pll *pll = to_clk_pll(hw); 557 unsigned long cfreq; 558 u32 p_div = 0; 559 int ret; 560 561 if (!rate) 562 return -EINVAL; 563 564 switch (parent_rate) { 565 case 12000000: 566 case 26000000: 567 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 568 break; 569 case 13000000: 570 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 571 break; 572 case 16800000: 573 case 19200000: 574 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 575 break; 576 case 9600000: 577 case 28800000: 578 /* 579 * PLL_P_OUT1 rate is not listed in PLLA table 580 */ 581 cfreq = parent_rate / (parent_rate / 1000000); 582 break; 583 default: 584 pr_err("%s Unexpected reference rate %lu\n", 585 __func__, parent_rate); 586 BUG(); 587 } 588 589 /* Raise VCO to guarantee 0.5% accuracy */ 590 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 591 cfg->output_rate <<= 1) 592 p_div++; 593 594 cfg->m = parent_rate / cfreq; 595 cfg->n = cfg->output_rate / cfreq; 596 cfg->cpcon = OUT_OF_TABLE_CPCON; 597 598 if (cfg->m == 0 || cfg->m > divm_max(pll) || 599 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || 600 cfg->output_rate > pll->params->vco_max) { 601 return -EINVAL; 602 } 603 604 cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m); 605 cfg->output_rate >>= p_div; 606 607 if (pll->params->pdiv_tohw) { 608 ret = _p_div_to_hw(hw, 1 << p_div); 609 if (ret < 0) 610 return ret; 611 else 612 cfg->p = ret; 613 } else 614 cfg->p = p_div; 615 616 return 0; 617} 618 619/* 620 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number 621 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as 622 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used 623 * to indicate that SDM is disabled. 624 * 625 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 626 */ 627static void clk_pll_set_sdm_data(struct clk_hw *hw, 628 struct tegra_clk_pll_freq_table *cfg) 629{ 630 struct tegra_clk_pll *pll = to_clk_pll(hw); 631 u32 val; 632 bool enabled; 633 634 if (!pll->params->sdm_din_reg) 635 return; 636 637 if (cfg->sdm_data) { 638 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); 639 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); 640 pll_writel_sdm_din(val, pll); 641 } 642 643 val = pll_readl_sdm_ctrl(pll); 644 enabled = (val & sdm_en_mask(pll)); 645 646 if (cfg->sdm_data == 0 && enabled) 647 val &= ~pll->params->sdm_ctrl_en_mask; 648 649 if (cfg->sdm_data != 0 && !enabled) 650 val |= pll->params->sdm_ctrl_en_mask; 651 652 pll_writel_sdm_ctrl(val, pll); 653} 654 655static void _update_pll_mnp(struct tegra_clk_pll *pll, 656 struct tegra_clk_pll_freq_table *cfg) 657{ 658 u32 val; 659 struct tegra_clk_pll_params *params = pll->params; 660 struct div_nmp *div_nmp = params->div_nmp; 661 662 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 663 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 664 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 665 val = pll_override_readl(params->pmc_divp_reg, pll); 666 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); 667 val |= cfg->p << div_nmp->override_divp_shift; 668 pll_override_writel(val, params->pmc_divp_reg, pll); 669 670 val = pll_override_readl(params->pmc_divnm_reg, pll); 671 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | 672 (divn_mask(pll) << div_nmp->override_divn_shift)); 673 val |= (cfg->m << div_nmp->override_divm_shift) | 674 (cfg->n << div_nmp->override_divn_shift); 675 pll_override_writel(val, params->pmc_divnm_reg, pll); 676 } else { 677 val = pll_readl_base(pll); 678 679 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | 680 divp_mask_shifted(pll)); 681 682 val |= (cfg->m << divm_shift(pll)) | 683 (cfg->n << divn_shift(pll)) | 684 (cfg->p << divp_shift(pll)); 685 686 pll_writel_base(val, pll); 687 688 clk_pll_set_sdm_data(&pll->hw, cfg); 689 } 690} 691 692static void _get_pll_mnp(struct tegra_clk_pll *pll, 693 struct tegra_clk_pll_freq_table *cfg) 694{ 695 u32 val; 696 struct tegra_clk_pll_params *params = pll->params; 697 struct div_nmp *div_nmp = params->div_nmp; 698 699 *cfg = (struct tegra_clk_pll_freq_table) { }; 700 701 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 702 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 703 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 704 val = pll_override_readl(params->pmc_divp_reg, pll); 705 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); 706 707 val = pll_override_readl(params->pmc_divnm_reg, pll); 708 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); 709 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); 710 } else { 711 val = pll_readl_base(pll); 712 713 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 714 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 715 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 716 717 if (pll->params->sdm_din_reg) { 718 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { 719 val = pll_readl_sdm_din(pll); 720 val &= sdm_din_mask(pll); 721 cfg->sdm_data = sdin_din_to_data(val); 722 } 723 } 724 } 725} 726 727static void _update_pll_cpcon(struct tegra_clk_pll *pll, 728 struct tegra_clk_pll_freq_table *cfg, 729 unsigned long rate) 730{ 731 u32 val; 732 733 val = pll_readl_misc(pll); 734 735 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 736 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 737 738 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { 739 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 740 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 741 val |= 1 << PLL_MISC_LFCON_SHIFT; 742 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { 743 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 744 if (rate >= (pll->params->vco_max >> 1)) 745 val |= 1 << PLL_MISC_DCCON_SHIFT; 746 } 747 748 pll_writel_misc(val, pll); 749} 750 751static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 752 unsigned long rate) 753{ 754 struct tegra_clk_pll *pll = to_clk_pll(hw); 755 struct tegra_clk_pll_freq_table old_cfg; 756 int state, ret = 0; 757 758 state = clk_pll_is_enabled(hw); 759 760 if (state && pll->params->pre_rate_change) { 761 ret = pll->params->pre_rate_change(); 762 if (WARN_ON(ret)) 763 return ret; 764 } 765 766 _get_pll_mnp(pll, &old_cfg); 767 768 if (state && pll->params->defaults_set && pll->params->dyn_ramp && 769 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { 770 ret = pll->params->dyn_ramp(pll, cfg); 771 if (!ret) 772 goto done; 773 } 774 775 if (state) { 776 pll_clk_stop_ss(pll); 777 _clk_pll_disable(hw); 778 } 779 780 if (!pll->params->defaults_set && pll->params->set_defaults) 781 pll->params->set_defaults(pll); 782 783 _update_pll_mnp(pll, cfg); 784 785 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) 786 _update_pll_cpcon(pll, cfg, rate); 787 788 if (state) { 789 _clk_pll_enable(hw); 790 ret = clk_pll_wait_for_lock(pll); 791 pll_clk_start_ss(pll); 792 } 793 794done: 795 if (state && pll->params->post_rate_change) 796 pll->params->post_rate_change(); 797 798 return ret; 799} 800 801static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 802 unsigned long parent_rate) 803{ 804 struct tegra_clk_pll *pll = to_clk_pll(hw); 805 struct tegra_clk_pll_freq_table cfg, old_cfg; 806 unsigned long flags = 0; 807 int ret = 0; 808 809 if (pll->params->flags & TEGRA_PLL_FIXED) { 810 if (rate != pll->params->fixed_rate) { 811 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 812 __func__, clk_hw_get_name(hw), 813 pll->params->fixed_rate, rate); 814 return -EINVAL; 815 } 816 return 0; 817 } 818 819 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 820 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { 821 pr_err("%s: Failed to set %s rate %lu\n", __func__, 822 clk_hw_get_name(hw), rate); 823 WARN_ON(1); 824 return -EINVAL; 825 } 826 if (pll->lock) 827 spin_lock_irqsave(pll->lock, flags); 828 829 _get_pll_mnp(pll, &old_cfg); 830 if (pll->params->flags & TEGRA_PLL_VCO_OUT) 831 cfg.p = old_cfg.p; 832 833 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p || 834 old_cfg.sdm_data != cfg.sdm_data) 835 ret = _program_pll(hw, &cfg, rate); 836 837 if (pll->lock) 838 spin_unlock_irqrestore(pll->lock, flags); 839 840 return ret; 841} 842 843static int clk_pll_determine_rate(struct clk_hw *hw, 844 struct clk_rate_request *req) 845{ 846 struct tegra_clk_pll *pll = to_clk_pll(hw); 847 struct tegra_clk_pll_freq_table cfg; 848 849 if (pll->params->flags & TEGRA_PLL_FIXED) { 850 /* PLLM/MB are used for memory; we do not change rate */ 851 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) 852 req->rate = clk_hw_get_rate(hw); 853 else 854 req->rate = pll->params->fixed_rate; 855 856 return 0; 857 } 858 859 if (_get_table_rate(hw, &cfg, req->rate, req->best_parent_rate) && 860 pll->params->calc_rate(hw, &cfg, req->rate, req->best_parent_rate)) 861 return -EINVAL; 862 863 req->rate = cfg.output_rate; 864 865 return 0; 866} 867 868static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 869 unsigned long parent_rate) 870{ 871 struct tegra_clk_pll *pll = to_clk_pll(hw); 872 struct tegra_clk_pll_freq_table cfg; 873 u32 val; 874 u64 rate = parent_rate; 875 int pdiv; 876 877 val = pll_readl_base(pll); 878 879 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 880 return parent_rate; 881 882 if ((pll->params->flags & TEGRA_PLL_FIXED) && 883 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && 884 !(val & PLL_BASE_OVERRIDE)) { 885 struct tegra_clk_pll_freq_table sel; 886 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 887 parent_rate)) { 888 pr_err("Clock %s has unknown fixed frequency\n", 889 clk_hw_get_name(hw)); 890 BUG(); 891 } 892 return pll->params->fixed_rate; 893 } 894 895 _get_pll_mnp(pll, &cfg); 896 897 if (pll->params->flags & TEGRA_PLL_VCO_OUT) { 898 pdiv = 1; 899 } else { 900 pdiv = _hw_to_p_div(hw, cfg.p); 901 if (pdiv < 0) { 902 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n", 903 clk_hw_get_name(hw), cfg.p); 904 pdiv = 1; 905 } 906 } 907 908 if (pll->params->set_gain) 909 pll->params->set_gain(&cfg); 910 911 cfg.m *= pdiv; 912 913 rate *= cfg.n; 914 do_div(rate, cfg.m); 915 916 return rate; 917} 918 919static int clk_plle_training(struct tegra_clk_pll *pll) 920{ 921 u32 val; 922 unsigned long timeout; 923 924 if (!pll->pmc) 925 return -ENOSYS; 926 927 /* 928 * PLLE is already disabled, and setup cleared; 929 * create falling edge on PLLE IDDQ input. 930 */ 931 val = readl(pll->pmc + PMC_SATA_PWRGT); 932 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 933 writel(val, pll->pmc + PMC_SATA_PWRGT); 934 935 val = readl(pll->pmc + PMC_SATA_PWRGT); 936 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 937 writel(val, pll->pmc + PMC_SATA_PWRGT); 938 939 val = readl(pll->pmc + PMC_SATA_PWRGT); 940 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 941 writel(val, pll->pmc + PMC_SATA_PWRGT); 942 943 val = pll_readl_misc(pll); 944 945 timeout = jiffies + msecs_to_jiffies(100); 946 while (1) { 947 val = pll_readl_misc(pll); 948 if (val & PLLE_MISC_READY) 949 break; 950 if (time_after(jiffies, timeout)) { 951 pr_err("%s: timeout waiting for PLLE\n", __func__); 952 return -EBUSY; 953 } 954 udelay(300); 955 } 956 957 return 0; 958} 959 960static int clk_plle_enable(struct clk_hw *hw) 961{ 962 struct tegra_clk_pll *pll = to_clk_pll(hw); 963 struct tegra_clk_pll_freq_table sel; 964 unsigned long input_rate; 965 u32 val; 966 int err; 967 968 if (clk_pll_is_enabled(hw)) 969 return 0; 970 971 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 972 973 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 974 return -EINVAL; 975 976 clk_pll_disable(hw); 977 978 val = pll_readl_misc(pll); 979 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 980 pll_writel_misc(val, pll); 981 982 val = pll_readl_misc(pll); 983 if (!(val & PLLE_MISC_READY)) { 984 err = clk_plle_training(pll); 985 if (err) 986 return err; 987 } 988 989 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { 990 /* configure dividers */ 991 val = pll_readl_base(pll); 992 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 993 divm_mask_shifted(pll)); 994 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 995 val |= sel.m << divm_shift(pll); 996 val |= sel.n << divn_shift(pll); 997 val |= sel.p << divp_shift(pll); 998 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 999 pll_writel_base(val, pll); 1000 } 1001 1002 val = pll_readl_misc(pll); 1003 val |= PLLE_MISC_SETUP_VALUE; 1004 val |= PLLE_MISC_LOCK_ENABLE; 1005 pll_writel_misc(val, pll); 1006 1007 val = readl(pll->clk_base + PLLE_SS_CTRL); 1008 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1009 val |= PLLE_SS_DISABLE; 1010 writel(val, pll->clk_base + PLLE_SS_CTRL); 1011 1012 val = pll_readl_base(pll); 1013 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1014 pll_writel_base(val, pll); 1015 1016 clk_pll_wait_for_lock(pll); 1017 1018 return 0; 1019} 1020 1021static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 1022 unsigned long parent_rate) 1023{ 1024 struct tegra_clk_pll *pll = to_clk_pll(hw); 1025 u32 val = pll_readl_base(pll); 1026 u32 divn = 0, divm = 0, divp = 0; 1027 u64 rate = parent_rate; 1028 1029 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 1030 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 1031 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 1032 divm *= divp; 1033 1034 rate *= divn; 1035 do_div(rate, divm); 1036 return rate; 1037} 1038 1039static void tegra_clk_pll_restore_context(struct clk_hw *hw) 1040{ 1041 struct tegra_clk_pll *pll = to_clk_pll(hw); 1042 struct clk_hw *parent = clk_hw_get_parent(hw); 1043 unsigned long parent_rate = clk_hw_get_rate(parent); 1044 unsigned long rate = clk_hw_get_rate(hw); 1045 1046 if (clk_pll_is_enabled(hw)) 1047 return; 1048 1049 if (pll->params->set_defaults) 1050 pll->params->set_defaults(pll); 1051 1052 clk_pll_set_rate(hw, rate, parent_rate); 1053 1054 if (!__clk_get_enable_count(hw->clk)) 1055 clk_pll_disable(hw); 1056 else 1057 clk_pll_enable(hw); 1058} 1059 1060const struct clk_ops tegra_clk_pll_ops = { 1061 .is_enabled = clk_pll_is_enabled, 1062 .enable = clk_pll_enable, 1063 .disable = clk_pll_disable, 1064 .recalc_rate = clk_pll_recalc_rate, 1065 .determine_rate = clk_pll_determine_rate, 1066 .set_rate = clk_pll_set_rate, 1067 .restore_context = tegra_clk_pll_restore_context, 1068}; 1069 1070const struct clk_ops tegra_clk_plle_ops = { 1071 .recalc_rate = clk_plle_recalc_rate, 1072 .is_enabled = clk_pll_is_enabled, 1073 .disable = clk_pll_disable, 1074 .enable = clk_plle_enable, 1075}; 1076 1077/* 1078 * Structure defining the fields for USB UTMI clocks Parameters. 1079 */ 1080struct utmi_clk_param { 1081 /* Oscillator Frequency in Hz */ 1082 u32 osc_frequency; 1083 /* UTMIP PLL Enable Delay Count */ 1084 u8 enable_delay_count; 1085 /* UTMIP PLL Stable count */ 1086 u8 stable_count; 1087 /* UTMIP PLL Active delay count */ 1088 u8 active_delay_count; 1089 /* UTMIP PLL Xtal frequency count */ 1090 u8 xtal_freq_count; 1091}; 1092 1093static const struct utmi_clk_param utmi_parameters[] = { 1094 { 1095 .osc_frequency = 13000000, .enable_delay_count = 0x02, 1096 .stable_count = 0x33, .active_delay_count = 0x05, 1097 .xtal_freq_count = 0x7f 1098 }, { 1099 .osc_frequency = 19200000, .enable_delay_count = 0x03, 1100 .stable_count = 0x4b, .active_delay_count = 0x06, 1101 .xtal_freq_count = 0xbb 1102 }, { 1103 .osc_frequency = 12000000, .enable_delay_count = 0x02, 1104 .stable_count = 0x2f, .active_delay_count = 0x04, 1105 .xtal_freq_count = 0x76 1106 }, { 1107 .osc_frequency = 26000000, .enable_delay_count = 0x04, 1108 .stable_count = 0x66, .active_delay_count = 0x09, 1109 .xtal_freq_count = 0xfe 1110 }, { 1111 .osc_frequency = 16800000, .enable_delay_count = 0x03, 1112 .stable_count = 0x41, .active_delay_count = 0x0a, 1113 .xtal_freq_count = 0xa4 1114 }, { 1115 .osc_frequency = 38400000, .enable_delay_count = 0x0, 1116 .stable_count = 0x0, .active_delay_count = 0x6, 1117 .xtal_freq_count = 0x80 1118 }, 1119}; 1120 1121static int clk_pllu_enable(struct clk_hw *hw) 1122{ 1123 struct tegra_clk_pll *pll = to_clk_pll(hw); 1124 struct clk_hw *pll_ref = clk_hw_get_parent(hw); 1125 struct clk_hw *osc = clk_hw_get_parent(pll_ref); 1126 const struct utmi_clk_param *params = NULL; 1127 unsigned long flags = 0, input_rate; 1128 unsigned int i; 1129 int ret = 0; 1130 u32 value; 1131 1132 if (!osc) { 1133 pr_err("%s: failed to get OSC clock\n", __func__); 1134 return -EINVAL; 1135 } 1136 1137 input_rate = clk_hw_get_rate(osc); 1138 1139 if (pll->lock) 1140 spin_lock_irqsave(pll->lock, flags); 1141 1142 if (!clk_pll_is_enabled(hw)) 1143 _clk_pll_enable(hw); 1144 1145 ret = clk_pll_wait_for_lock(pll); 1146 if (ret < 0) 1147 goto out; 1148 1149 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1150 if (input_rate == utmi_parameters[i].osc_frequency) { 1151 params = &utmi_parameters[i]; 1152 break; 1153 } 1154 } 1155 1156 if (!params) { 1157 pr_err("%s: unexpected input rate %lu Hz\n", __func__, 1158 input_rate); 1159 ret = -EINVAL; 1160 goto out; 1161 } 1162 1163 value = pll_readl_base(pll); 1164 value &= ~PLLU_BASE_OVERRIDE; 1165 pll_writel_base(value, pll); 1166 1167 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); 1168 /* Program UTMIP PLL stable and active counts */ 1169 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1170 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); 1171 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1172 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); 1173 /* Remove power downs from UTMIP PLL control bits */ 1174 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1175 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1176 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1177 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); 1178 1179 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); 1180 /* Program UTMIP PLL delay and oscillator frequency counts */ 1181 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1182 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); 1183 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1184 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); 1185 /* Remove power downs from UTMIP PLL control bits */ 1186 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1187 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1188 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1189 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); 1190 1191out: 1192 if (pll->lock) 1193 spin_unlock_irqrestore(pll->lock, flags); 1194 1195 return ret; 1196} 1197 1198static const struct clk_ops tegra_clk_pllu_ops = { 1199 .is_enabled = clk_pll_is_enabled, 1200 .enable = clk_pllu_enable, 1201 .disable = clk_pll_disable, 1202 .recalc_rate = clk_pll_recalc_rate, 1203 .determine_rate = clk_pll_determine_rate, 1204 .set_rate = clk_pll_set_rate, 1205}; 1206 1207static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 1208 unsigned long parent_rate) 1209{ 1210 u16 mdiv = parent_rate / pll_params->cf_min; 1211 1212 if (pll_params->flags & TEGRA_MDIV_NEW) 1213 return (!pll_params->mdiv_default ? mdiv : 1214 min(mdiv, pll_params->mdiv_default)); 1215 1216 if (pll_params->mdiv_default) 1217 return pll_params->mdiv_default; 1218 1219 if (parent_rate > pll_params->cf_max) 1220 return 2; 1221 else 1222 return 1; 1223} 1224 1225static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 1226 struct tegra_clk_pll_freq_table *cfg, 1227 unsigned long rate, unsigned long parent_rate) 1228{ 1229 struct tegra_clk_pll *pll = to_clk_pll(hw); 1230 unsigned int p; 1231 int p_div; 1232 1233 if (!rate) 1234 return -EINVAL; 1235 1236 p = DIV_ROUND_UP(pll->params->vco_min, rate); 1237 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 1238 cfg->output_rate = rate * p; 1239 cfg->n = cfg->output_rate * cfg->m / parent_rate; 1240 cfg->input_rate = parent_rate; 1241 1242 p_div = _p_div_to_hw(hw, p); 1243 if (p_div < 0) 1244 return p_div; 1245 1246 cfg->p = p_div; 1247 1248 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 1249 return -EINVAL; 1250 1251 return 0; 1252} 1253 1254#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1255 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1256 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 1257 defined(CONFIG_ARCH_TEGRA_210_SOC) 1258 1259u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) 1260{ 1261 struct tegra_clk_pll *pll = to_clk_pll(hw); 1262 1263 return (u16)_pll_fixed_mdiv(pll->params, input_rate); 1264} 1265 1266static unsigned long _clip_vco_min(unsigned long vco_min, 1267 unsigned long parent_rate) 1268{ 1269 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate; 1270} 1271 1272static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1273 void __iomem *clk_base, 1274 unsigned long parent_rate) 1275{ 1276 u32 val; 1277 u32 step_a, step_b; 1278 1279 switch (parent_rate) { 1280 case 12000000: 1281 case 13000000: 1282 case 26000000: 1283 step_a = 0x2B; 1284 step_b = 0x0B; 1285 break; 1286 case 16800000: 1287 step_a = 0x1A; 1288 step_b = 0x09; 1289 break; 1290 case 19200000: 1291 step_a = 0x12; 1292 step_b = 0x08; 1293 break; 1294 default: 1295 pr_err("%s: Unexpected reference rate %lu\n", 1296 __func__, parent_rate); 1297 WARN_ON(1); 1298 return -EINVAL; 1299 } 1300 1301 val = step_a << pll_params->stepa_shift; 1302 val |= step_b << pll_params->stepb_shift; 1303 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1304 1305 return 0; 1306} 1307 1308static int _pll_ramp_calc_pll(struct clk_hw *hw, 1309 struct tegra_clk_pll_freq_table *cfg, 1310 unsigned long rate, unsigned long parent_rate) 1311{ 1312 struct tegra_clk_pll *pll = to_clk_pll(hw); 1313 int err = 0; 1314 1315 err = _get_table_rate(hw, cfg, rate, parent_rate); 1316 if (err < 0) 1317 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 1318 else { 1319 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 1320 WARN_ON(1); 1321 err = -EINVAL; 1322 goto out; 1323 } 1324 } 1325 1326 if (cfg->p > pll->params->max_p) 1327 err = -EINVAL; 1328 1329out: 1330 return err; 1331} 1332 1333static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 1334 unsigned long parent_rate) 1335{ 1336 struct tegra_clk_pll *pll = to_clk_pll(hw); 1337 struct tegra_clk_pll_freq_table cfg, old_cfg; 1338 unsigned long flags = 0; 1339 int ret; 1340 1341 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1342 if (ret < 0) 1343 return ret; 1344 1345 if (pll->lock) 1346 spin_lock_irqsave(pll->lock, flags); 1347 1348 _get_pll_mnp(pll, &old_cfg); 1349 if (pll->params->flags & TEGRA_PLL_VCO_OUT) 1350 cfg.p = old_cfg.p; 1351 1352 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 1353 ret = _program_pll(hw, &cfg, rate); 1354 1355 if (pll->lock) 1356 spin_unlock_irqrestore(pll->lock, flags); 1357 1358 return ret; 1359} 1360 1361static int clk_pll_ramp_determine_rate(struct clk_hw *hw, 1362 struct clk_rate_request *req) 1363{ 1364 struct tegra_clk_pll *pll = to_clk_pll(hw); 1365 struct tegra_clk_pll_freq_table cfg; 1366 int ret, p_div; 1367 u64 output_rate = req->best_parent_rate; 1368 1369 ret = _pll_ramp_calc_pll(hw, &cfg, req->rate, req->best_parent_rate); 1370 if (ret < 0) 1371 return ret; 1372 1373 p_div = _hw_to_p_div(hw, cfg.p); 1374 if (p_div < 0) 1375 return p_div; 1376 1377 if (pll->params->set_gain) 1378 pll->params->set_gain(&cfg); 1379 1380 output_rate *= cfg.n; 1381 do_div(output_rate, cfg.m * p_div); 1382 1383 req->rate = output_rate; 1384 1385 return 0; 1386} 1387 1388static void _pllcx_strobe(struct tegra_clk_pll *pll) 1389{ 1390 u32 val; 1391 1392 val = pll_readl_misc(pll); 1393 val |= PLLCX_MISC_STROBE; 1394 pll_writel_misc(val, pll); 1395 udelay(2); 1396 1397 val &= ~PLLCX_MISC_STROBE; 1398 pll_writel_misc(val, pll); 1399} 1400 1401static int clk_pllc_enable(struct clk_hw *hw) 1402{ 1403 struct tegra_clk_pll *pll = to_clk_pll(hw); 1404 u32 val; 1405 int ret; 1406 unsigned long flags = 0; 1407 1408 if (clk_pll_is_enabled(hw)) 1409 return 0; 1410 1411 if (pll->lock) 1412 spin_lock_irqsave(pll->lock, flags); 1413 1414 _clk_pll_enable(hw); 1415 udelay(2); 1416 1417 val = pll_readl_misc(pll); 1418 val &= ~PLLCX_MISC_RESET; 1419 pll_writel_misc(val, pll); 1420 udelay(2); 1421 1422 _pllcx_strobe(pll); 1423 1424 ret = clk_pll_wait_for_lock(pll); 1425 1426 if (pll->lock) 1427 spin_unlock_irqrestore(pll->lock, flags); 1428 1429 return ret; 1430} 1431 1432static void _clk_pllc_disable(struct clk_hw *hw) 1433{ 1434 struct tegra_clk_pll *pll = to_clk_pll(hw); 1435 u32 val; 1436 1437 _clk_pll_disable(hw); 1438 1439 val = pll_readl_misc(pll); 1440 val |= PLLCX_MISC_RESET; 1441 pll_writel_misc(val, pll); 1442 udelay(2); 1443} 1444 1445static void clk_pllc_disable(struct clk_hw *hw) 1446{ 1447 struct tegra_clk_pll *pll = to_clk_pll(hw); 1448 unsigned long flags = 0; 1449 1450 if (pll->lock) 1451 spin_lock_irqsave(pll->lock, flags); 1452 1453 _clk_pllc_disable(hw); 1454 1455 if (pll->lock) 1456 spin_unlock_irqrestore(pll->lock, flags); 1457} 1458 1459static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 1460 unsigned long input_rate, u32 n) 1461{ 1462 u32 val, n_threshold; 1463 1464 switch (input_rate) { 1465 case 12000000: 1466 n_threshold = 70; 1467 break; 1468 case 13000000: 1469 case 26000000: 1470 n_threshold = 71; 1471 break; 1472 case 16800000: 1473 n_threshold = 55; 1474 break; 1475 case 19200000: 1476 n_threshold = 48; 1477 break; 1478 default: 1479 pr_err("%s: Unexpected reference rate %lu\n", 1480 __func__, input_rate); 1481 return -EINVAL; 1482 } 1483 1484 val = pll_readl_misc(pll); 1485 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1486 val |= n <= n_threshold ? 1487 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1488 pll_writel_misc(val, pll); 1489 1490 return 0; 1491} 1492 1493static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1494 unsigned long parent_rate) 1495{ 1496 struct tegra_clk_pll_freq_table cfg, old_cfg; 1497 struct tegra_clk_pll *pll = to_clk_pll(hw); 1498 unsigned long flags = 0; 1499 int state, ret = 0; 1500 1501 if (pll->lock) 1502 spin_lock_irqsave(pll->lock, flags); 1503 1504 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1505 if (ret < 0) 1506 goto out; 1507 1508 _get_pll_mnp(pll, &old_cfg); 1509 1510 if (cfg.m != old_cfg.m) { 1511 WARN_ON(1); 1512 goto out; 1513 } 1514 1515 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1516 goto out; 1517 1518 state = clk_pll_is_enabled(hw); 1519 if (state) 1520 _clk_pllc_disable(hw); 1521 1522 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1523 if (ret < 0) 1524 goto out; 1525 1526 _update_pll_mnp(pll, &cfg); 1527 1528 if (state) 1529 ret = clk_pllc_enable(hw); 1530 1531out: 1532 if (pll->lock) 1533 spin_unlock_irqrestore(pll->lock, flags); 1534 1535 return ret; 1536} 1537 1538static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1539 struct tegra_clk_pll_freq_table *cfg, 1540 unsigned long rate, unsigned long parent_rate) 1541{ 1542 u16 m, n; 1543 u64 output_rate = parent_rate; 1544 1545 m = _pll_fixed_mdiv(pll->params, parent_rate); 1546 n = rate * m / parent_rate; 1547 1548 output_rate *= n; 1549 do_div(output_rate, m); 1550 1551 if (cfg) { 1552 cfg->m = m; 1553 cfg->n = n; 1554 } 1555 1556 return output_rate; 1557} 1558 1559static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1560 unsigned long parent_rate) 1561{ 1562 struct tegra_clk_pll_freq_table cfg, old_cfg; 1563 struct tegra_clk_pll *pll = to_clk_pll(hw); 1564 unsigned long flags = 0; 1565 int state, ret = 0; 1566 1567 if (pll->lock) 1568 spin_lock_irqsave(pll->lock, flags); 1569 1570 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1571 _get_pll_mnp(pll, &old_cfg); 1572 cfg.p = old_cfg.p; 1573 1574 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1575 state = clk_pll_is_enabled(hw); 1576 if (state) 1577 _clk_pll_disable(hw); 1578 1579 _update_pll_mnp(pll, &cfg); 1580 1581 if (state) { 1582 _clk_pll_enable(hw); 1583 ret = clk_pll_wait_for_lock(pll); 1584 } 1585 } 1586 1587 if (pll->lock) 1588 spin_unlock_irqrestore(pll->lock, flags); 1589 1590 return ret; 1591} 1592 1593static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1594 unsigned long parent_rate) 1595{ 1596 struct tegra_clk_pll_freq_table cfg; 1597 struct tegra_clk_pll *pll = to_clk_pll(hw); 1598 u64 rate = parent_rate; 1599 1600 _get_pll_mnp(pll, &cfg); 1601 1602 rate *= cfg.n; 1603 do_div(rate, cfg.m); 1604 1605 return rate; 1606} 1607 1608static int clk_pllre_determine_rate(struct clk_hw *hw, 1609 struct clk_rate_request *req) 1610{ 1611 struct tegra_clk_pll *pll = to_clk_pll(hw); 1612 1613 req->rate = _pllre_calc_rate(pll, NULL, req->rate, 1614 req->best_parent_rate); 1615 1616 return 0; 1617} 1618 1619static int clk_plle_tegra114_enable(struct clk_hw *hw) 1620{ 1621 struct tegra_clk_pll *pll = to_clk_pll(hw); 1622 struct tegra_clk_pll_freq_table sel; 1623 u32 val; 1624 int ret; 1625 unsigned long flags = 0; 1626 unsigned long input_rate; 1627 1628 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 1629 1630 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 1631 return -EINVAL; 1632 1633 if (pll->lock) 1634 spin_lock_irqsave(pll->lock, flags); 1635 1636 val = pll_readl_base(pll); 1637 val &= ~BIT(29); /* Disable lock override */ 1638 pll_writel_base(val, pll); 1639 1640 val = pll_readl(pll->params->aux_reg, pll); 1641 val |= PLLE_AUX_ENABLE_SWCTL; 1642 val &= ~PLLE_AUX_SEQ_ENABLE; 1643 pll_writel(val, pll->params->aux_reg, pll); 1644 udelay(1); 1645 1646 val = pll_readl_misc(pll); 1647 val |= PLLE_MISC_LOCK_ENABLE; 1648 val |= PLLE_MISC_IDDQ_SW_CTRL; 1649 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1650 val |= PLLE_MISC_PLLE_PTS; 1651 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); 1652 pll_writel_misc(val, pll); 1653 udelay(5); 1654 1655 val = pll_readl(PLLE_SS_CTRL, pll); 1656 val |= PLLE_SS_DISABLE; 1657 pll_writel(val, PLLE_SS_CTRL, pll); 1658 1659 val = pll_readl_base(pll); 1660 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 1661 divm_mask_shifted(pll)); 1662 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 1663 val |= sel.m << divm_shift(pll); 1664 val |= sel.n << divn_shift(pll); 1665 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1666 pll_writel_base(val, pll); 1667 udelay(1); 1668 1669 _clk_pll_enable(hw); 1670 ret = clk_pll_wait_for_lock(pll); 1671 1672 if (ret < 0) 1673 goto out; 1674 1675 val = pll_readl(PLLE_SS_CTRL, pll); 1676 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 1677 val &= ~PLLE_SS_COEFFICIENTS_MASK; 1678 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114; 1679 pll_writel(val, PLLE_SS_CTRL, pll); 1680 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 1681 pll_writel(val, PLLE_SS_CTRL, pll); 1682 udelay(1); 1683 val &= ~PLLE_SS_CNTL_INTERP_RESET; 1684 pll_writel(val, PLLE_SS_CTRL, pll); 1685 udelay(1); 1686 1687 /* Enable HW control of XUSB brick PLL */ 1688 val = pll_readl_misc(pll); 1689 val &= ~PLLE_MISC_IDDQ_SW_CTRL; 1690 pll_writel_misc(val, pll); 1691 1692 val = pll_readl(pll->params->aux_reg, pll); 1693 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); 1694 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); 1695 pll_writel(val, pll->params->aux_reg, pll); 1696 udelay(1); 1697 val |= PLLE_AUX_SEQ_ENABLE; 1698 pll_writel(val, pll->params->aux_reg, pll); 1699 1700 val = pll_readl(XUSBIO_PLL_CFG0, pll); 1701 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 1702 XUSBIO_PLL_CFG0_SEQ_START_STATE); 1703 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 1704 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 1705 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1706 udelay(1); 1707 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1708 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1709 1710 /* Enable HW control of SATA PLL */ 1711 val = pll_readl(SATA_PLL_CFG0, pll); 1712 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 1713 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 1714 val |= SATA_PLL_CFG0_SEQ_START_STATE; 1715 pll_writel(val, SATA_PLL_CFG0, pll); 1716 1717 udelay(1); 1718 1719 val = pll_readl(SATA_PLL_CFG0, pll); 1720 val |= SATA_PLL_CFG0_SEQ_ENABLE; 1721 pll_writel(val, SATA_PLL_CFG0, pll); 1722 1723out: 1724 if (pll->lock) 1725 spin_unlock_irqrestore(pll->lock, flags); 1726 1727 return ret; 1728} 1729 1730static void clk_plle_tegra114_disable(struct clk_hw *hw) 1731{ 1732 struct tegra_clk_pll *pll = to_clk_pll(hw); 1733 unsigned long flags = 0; 1734 u32 val; 1735 1736 if (pll->lock) 1737 spin_lock_irqsave(pll->lock, flags); 1738 1739 _clk_pll_disable(hw); 1740 1741 val = pll_readl_misc(pll); 1742 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1743 pll_writel_misc(val, pll); 1744 udelay(1); 1745 1746 if (pll->lock) 1747 spin_unlock_irqrestore(pll->lock, flags); 1748} 1749 1750static int clk_pllu_tegra114_enable(struct clk_hw *hw) 1751{ 1752 struct tegra_clk_pll *pll = to_clk_pll(hw); 1753 const struct utmi_clk_param *params = NULL; 1754 struct clk *osc = __clk_lookup("osc"); 1755 unsigned long flags = 0, input_rate; 1756 unsigned int i; 1757 int ret = 0; 1758 u32 value; 1759 1760 if (!osc) { 1761 pr_err("%s: failed to get OSC clock\n", __func__); 1762 return -EINVAL; 1763 } 1764 1765 input_rate = clk_hw_get_rate(__clk_get_hw(osc)); 1766 1767 if (pll->lock) 1768 spin_lock_irqsave(pll->lock, flags); 1769 1770 if (!clk_pll_is_enabled(hw)) 1771 _clk_pll_enable(hw); 1772 1773 ret = clk_pll_wait_for_lock(pll); 1774 if (ret < 0) 1775 goto out; 1776 1777 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1778 if (input_rate == utmi_parameters[i].osc_frequency) { 1779 params = &utmi_parameters[i]; 1780 break; 1781 } 1782 } 1783 1784 if (!params) { 1785 pr_err("%s: unexpected input rate %lu Hz\n", __func__, 1786 input_rate); 1787 ret = -EINVAL; 1788 goto out; 1789 } 1790 1791 value = pll_readl_base(pll); 1792 value &= ~PLLU_BASE_OVERRIDE; 1793 pll_writel_base(value, pll); 1794 1795 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); 1796 /* Program UTMIP PLL stable and active counts */ 1797 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1798 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); 1799 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1800 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); 1801 /* Remove power downs from UTMIP PLL control bits */ 1802 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1803 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1804 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1805 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); 1806 1807 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); 1808 /* Program UTMIP PLL delay and oscillator frequency counts */ 1809 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1810 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); 1811 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1812 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); 1813 /* Remove power downs from UTMIP PLL control bits */ 1814 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1815 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1816 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1817 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1818 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); 1819 1820 /* Setup HW control of UTMIPLL */ 1821 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1822 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1823 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1824 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1825 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1826 1827 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); 1828 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1829 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1830 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); 1831 1832 udelay(1); 1833 1834 /* 1835 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned 1836 * to USB2 1837 */ 1838 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1839 value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1840 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1841 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1842 1843 udelay(1); 1844 1845 /* Enable HW control of UTMIPLL */ 1846 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1847 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1848 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); 1849 1850out: 1851 if (pll->lock) 1852 spin_unlock_irqrestore(pll->lock, flags); 1853 1854 return ret; 1855} 1856 1857static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll) 1858{ 1859 u32 val, val_aux; 1860 1861 /* ensure parent is set to pll_ref */ 1862 val = pll_readl_base(pll); 1863 val_aux = pll_readl(pll->params->aux_reg, pll); 1864 1865 if (val & PLL_BASE_ENABLE) { 1866 if ((val_aux & PLLE_AUX_PLLRE_SEL) || 1867 (val_aux & PLLE_AUX_PLLP_SEL)) 1868 WARN(1, "pll_e enabled with unsupported parent %s\n", 1869 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : 1870 "pll_re_vco"); 1871 } else { 1872 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); 1873 pll_writel(val_aux, pll->params->aux_reg, pll); 1874 fence_udelay(1, pll->clk_base); 1875 } 1876} 1877#endif 1878 1879static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1880 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, 1881 spinlock_t *lock) 1882{ 1883 struct tegra_clk_pll *pll; 1884 1885 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1886 if (!pll) 1887 return ERR_PTR(-ENOMEM); 1888 1889 pll->clk_base = clk_base; 1890 pll->pmc = pmc; 1891 1892 pll->params = pll_params; 1893 pll->lock = lock; 1894 1895 if (!pll_params->div_nmp) 1896 pll_params->div_nmp = &default_nmp; 1897 1898 return pll; 1899} 1900 1901static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1902 const char *name, const char *parent_name, unsigned long flags, 1903 const struct clk_ops *ops) 1904{ 1905 struct clk_init_data init; 1906 1907 init.name = name; 1908 init.ops = ops; 1909 init.flags = flags; 1910 init.parent_names = (parent_name ? &parent_name : NULL); 1911 init.num_parents = (parent_name ? 1 : 0); 1912 1913 /* Default to _calc_rate if unspecified */ 1914 if (!pll->params->calc_rate) { 1915 if (pll->params->flags & TEGRA_PLLM) 1916 pll->params->calc_rate = _calc_dynamic_ramp_rate; 1917 else 1918 pll->params->calc_rate = _calc_rate; 1919 } 1920 1921 if (pll->params->set_defaults) 1922 pll->params->set_defaults(pll); 1923 1924 /* Data in .init is copied by clk_register(), so stack variable OK */ 1925 pll->hw.init = &init; 1926 1927 return tegra_clk_dev_register(&pll->hw); 1928} 1929 1930struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1931 void __iomem *clk_base, void __iomem *pmc, 1932 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1933 spinlock_t *lock) 1934{ 1935 struct tegra_clk_pll *pll; 1936 struct clk *clk; 1937 1938 pll_params->flags |= TEGRA_PLL_BYPASS; 1939 1940 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1941 if (IS_ERR(pll)) 1942 return ERR_CAST(pll); 1943 1944 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1945 &tegra_clk_pll_ops); 1946 if (IS_ERR(clk)) 1947 kfree(pll); 1948 1949 return clk; 1950} 1951 1952static struct div_nmp pll_e_nmp = { 1953 .divn_shift = PLLE_BASE_DIVN_SHIFT, 1954 .divn_width = PLLE_BASE_DIVN_WIDTH, 1955 .divm_shift = PLLE_BASE_DIVM_SHIFT, 1956 .divm_width = PLLE_BASE_DIVM_WIDTH, 1957 .divp_shift = PLLE_BASE_DIVP_SHIFT, 1958 .divp_width = PLLE_BASE_DIVP_WIDTH, 1959}; 1960 1961struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1962 void __iomem *clk_base, void __iomem *pmc, 1963 unsigned long flags, struct tegra_clk_pll_params *pll_params, 1964 spinlock_t *lock) 1965{ 1966 struct tegra_clk_pll *pll; 1967 struct clk *clk; 1968 1969 pll_params->flags |= TEGRA_PLL_BYPASS; 1970 1971 if (!pll_params->div_nmp) 1972 pll_params->div_nmp = &pll_e_nmp; 1973 1974 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1975 if (IS_ERR(pll)) 1976 return ERR_CAST(pll); 1977 1978 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1979 &tegra_clk_plle_ops); 1980 if (IS_ERR(clk)) 1981 kfree(pll); 1982 1983 return clk; 1984} 1985 1986struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name, 1987 void __iomem *clk_base, unsigned long flags, 1988 struct tegra_clk_pll_params *pll_params, spinlock_t *lock) 1989{ 1990 struct tegra_clk_pll *pll; 1991 struct clk *clk; 1992 1993 pll_params->flags |= TEGRA_PLLU; 1994 1995 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1996 if (IS_ERR(pll)) 1997 return ERR_CAST(pll); 1998 1999 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2000 &tegra_clk_pllu_ops); 2001 if (IS_ERR(clk)) 2002 kfree(pll); 2003 2004 return clk; 2005} 2006 2007#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 2008 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 2009 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 2010 defined(CONFIG_ARCH_TEGRA_210_SOC) 2011static const struct clk_ops tegra_clk_pllxc_ops = { 2012 .is_enabled = clk_pll_is_enabled, 2013 .enable = clk_pll_enable, 2014 .disable = clk_pll_disable, 2015 .recalc_rate = clk_pll_recalc_rate, 2016 .determine_rate = clk_pll_ramp_determine_rate, 2017 .set_rate = clk_pllxc_set_rate, 2018}; 2019 2020static const struct clk_ops tegra_clk_pllc_ops = { 2021 .is_enabled = clk_pll_is_enabled, 2022 .enable = clk_pllc_enable, 2023 .disable = clk_pllc_disable, 2024 .recalc_rate = clk_pll_recalc_rate, 2025 .determine_rate = clk_pll_ramp_determine_rate, 2026 .set_rate = clk_pllc_set_rate, 2027}; 2028 2029static const struct clk_ops tegra_clk_pllre_ops = { 2030 .is_enabled = clk_pll_is_enabled, 2031 .enable = clk_pll_enable, 2032 .disable = clk_pll_disable, 2033 .recalc_rate = clk_pllre_recalc_rate, 2034 .determine_rate = clk_pllre_determine_rate, 2035 .set_rate = clk_pllre_set_rate, 2036}; 2037 2038static const struct clk_ops tegra_clk_plle_tegra114_ops = { 2039 .is_enabled = clk_pll_is_enabled, 2040 .enable = clk_plle_tegra114_enable, 2041 .disable = clk_plle_tegra114_disable, 2042 .recalc_rate = clk_pll_recalc_rate, 2043}; 2044 2045static const struct clk_ops tegra_clk_pllu_tegra114_ops = { 2046 .is_enabled = clk_pll_is_enabled, 2047 .enable = clk_pllu_tegra114_enable, 2048 .disable = clk_pll_disable, 2049 .recalc_rate = clk_pll_recalc_rate, 2050}; 2051 2052struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 2053 void __iomem *clk_base, void __iomem *pmc, 2054 unsigned long flags, 2055 struct tegra_clk_pll_params *pll_params, 2056 spinlock_t *lock) 2057{ 2058 struct tegra_clk_pll *pll; 2059 struct clk *clk, *parent; 2060 unsigned long parent_rate; 2061 u32 val, val_iddq; 2062 2063 parent = __clk_lookup(parent_name); 2064 if (!parent) { 2065 WARN(1, "parent clk %s of %s must be registered first\n", 2066 parent_name, name); 2067 return ERR_PTR(-EINVAL); 2068 } 2069 2070 if (!pll_params->pdiv_tohw) 2071 return ERR_PTR(-EINVAL); 2072 2073 parent_rate = clk_get_rate(parent); 2074 2075 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2076 2077 if (pll_params->adjust_vco) 2078 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2079 parent_rate); 2080 2081 /* 2082 * If the pll has a set_defaults callback, it will take care of 2083 * configuring dynamic ramping and setting IDDQ in that path. 2084 */ 2085 if (!pll_params->set_defaults) { 2086 int err; 2087 2088 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 2089 if (err) 2090 return ERR_PTR(err); 2091 2092 val = readl_relaxed(clk_base + pll_params->base_reg); 2093 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 2094 2095 if (val & PLL_BASE_ENABLE) 2096 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 2097 else { 2098 val_iddq |= BIT(pll_params->iddq_bit_idx); 2099 writel_relaxed(val_iddq, 2100 clk_base + pll_params->iddq_reg); 2101 } 2102 } 2103 2104 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2105 if (IS_ERR(pll)) 2106 return ERR_CAST(pll); 2107 2108 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2109 &tegra_clk_pllxc_ops); 2110 if (IS_ERR(clk)) 2111 kfree(pll); 2112 2113 return clk; 2114} 2115 2116struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 2117 void __iomem *clk_base, void __iomem *pmc, 2118 unsigned long flags, 2119 struct tegra_clk_pll_params *pll_params, 2120 spinlock_t *lock, unsigned long parent_rate) 2121{ 2122 u32 val; 2123 struct tegra_clk_pll *pll; 2124 struct clk *clk; 2125 2126 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2127 2128 if (pll_params->adjust_vco) 2129 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2130 parent_rate); 2131 2132 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2133 if (IS_ERR(pll)) 2134 return ERR_CAST(pll); 2135 2136 /* program minimum rate by default */ 2137 2138 val = pll_readl_base(pll); 2139 if (val & PLL_BASE_ENABLE) 2140 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & 2141 BIT(pll_params->iddq_bit_idx)); 2142 else { 2143 int m; 2144 2145 m = _pll_fixed_mdiv(pll_params, parent_rate); 2146 val = m << divm_shift(pll); 2147 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); 2148 pll_writel_base(val, pll); 2149 } 2150 2151 /* disable lock override */ 2152 2153 val = pll_readl_misc(pll); 2154 val &= ~BIT(29); 2155 pll_writel_misc(val, pll); 2156 2157 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2158 &tegra_clk_pllre_ops); 2159 if (IS_ERR(clk)) 2160 kfree(pll); 2161 2162 return clk; 2163} 2164 2165struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 2166 void __iomem *clk_base, void __iomem *pmc, 2167 unsigned long flags, 2168 struct tegra_clk_pll_params *pll_params, 2169 spinlock_t *lock) 2170{ 2171 struct tegra_clk_pll *pll; 2172 struct clk *clk, *parent; 2173 unsigned long parent_rate; 2174 2175 if (!pll_params->pdiv_tohw) 2176 return ERR_PTR(-EINVAL); 2177 2178 parent = __clk_lookup(parent_name); 2179 if (!parent) { 2180 WARN(1, "parent clk %s of %s must be registered first\n", 2181 parent_name, name); 2182 return ERR_PTR(-EINVAL); 2183 } 2184 2185 parent_rate = clk_get_rate(parent); 2186 2187 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2188 2189 if (pll_params->adjust_vco) 2190 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2191 parent_rate); 2192 2193 pll_params->flags |= TEGRA_PLL_BYPASS; 2194 pll_params->flags |= TEGRA_PLLM; 2195 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2196 if (IS_ERR(pll)) 2197 return ERR_CAST(pll); 2198 2199 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2200 &tegra_clk_pll_ops); 2201 if (IS_ERR(clk)) 2202 kfree(pll); 2203 2204 return clk; 2205} 2206 2207struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 2208 void __iomem *clk_base, void __iomem *pmc, 2209 unsigned long flags, 2210 struct tegra_clk_pll_params *pll_params, 2211 spinlock_t *lock) 2212{ 2213 struct clk *parent, *clk; 2214 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 2215 struct tegra_clk_pll *pll; 2216 struct tegra_clk_pll_freq_table cfg; 2217 unsigned long parent_rate; 2218 2219 if (!p_tohw) 2220 return ERR_PTR(-EINVAL); 2221 2222 parent = __clk_lookup(parent_name); 2223 if (!parent) { 2224 WARN(1, "parent clk %s of %s must be registered first\n", 2225 parent_name, name); 2226 return ERR_PTR(-EINVAL); 2227 } 2228 2229 parent_rate = clk_get_rate(parent); 2230 2231 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2232 2233 pll_params->flags |= TEGRA_PLL_BYPASS; 2234 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2235 if (IS_ERR(pll)) 2236 return ERR_CAST(pll); 2237 2238 /* 2239 * Most of PLLC register fields are shadowed, and can not be read 2240 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 2241 * Initialize PLL to default state: disabled, reset; shadow registers 2242 * loaded with default parameters; dividers are preset for half of 2243 * minimum VCO rate (the latter assured that shadowed divider settings 2244 * are within supported range). 2245 */ 2246 2247 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 2248 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 2249 2250 while (p_tohw->pdiv) { 2251 if (p_tohw->pdiv == 2) { 2252 cfg.p = p_tohw->hw_val; 2253 break; 2254 } 2255 p_tohw++; 2256 } 2257 2258 if (!p_tohw->pdiv) { 2259 WARN_ON(1); 2260 return ERR_PTR(-EINVAL); 2261 } 2262 2263 pll_writel_base(0, pll); 2264 _update_pll_mnp(pll, &cfg); 2265 2266 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 2267 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 2268 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 2269 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 2270 2271 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 2272 2273 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2274 &tegra_clk_pllc_ops); 2275 if (IS_ERR(clk)) 2276 kfree(pll); 2277 2278 return clk; 2279} 2280 2281struct clk *tegra_clk_register_plle_tegra114(const char *name, 2282 const char *parent_name, 2283 void __iomem *clk_base, unsigned long flags, 2284 struct tegra_clk_pll_params *pll_params, 2285 spinlock_t *lock) 2286{ 2287 struct tegra_clk_pll *pll; 2288 struct clk *clk; 2289 2290 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2291 if (IS_ERR(pll)) 2292 return ERR_CAST(pll); 2293 2294 _clk_plle_tegra_init_parent(pll); 2295 2296 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2297 &tegra_clk_plle_tegra114_ops); 2298 if (IS_ERR(clk)) 2299 kfree(pll); 2300 2301 return clk; 2302} 2303 2304struct clk * 2305tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name, 2306 void __iomem *clk_base, unsigned long flags, 2307 struct tegra_clk_pll_params *pll_params, 2308 spinlock_t *lock) 2309{ 2310 struct tegra_clk_pll *pll; 2311 struct clk *clk; 2312 2313 pll_params->flags |= TEGRA_PLLU; 2314 2315 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2316 if (IS_ERR(pll)) 2317 return ERR_CAST(pll); 2318 2319 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2320 &tegra_clk_pllu_tegra114_ops); 2321 if (IS_ERR(clk)) 2322 kfree(pll); 2323 2324 return clk; 2325} 2326#endif 2327 2328#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC) 2329static const struct clk_ops tegra_clk_pllss_ops = { 2330 .is_enabled = clk_pll_is_enabled, 2331 .enable = clk_pll_enable, 2332 .disable = clk_pll_disable, 2333 .recalc_rate = clk_pll_recalc_rate, 2334 .determine_rate = clk_pll_ramp_determine_rate, 2335 .set_rate = clk_pllxc_set_rate, 2336 .restore_context = tegra_clk_pll_restore_context, 2337}; 2338 2339struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 2340 void __iomem *clk_base, unsigned long flags, 2341 struct tegra_clk_pll_params *pll_params, 2342 spinlock_t *lock) 2343{ 2344 struct tegra_clk_pll *pll; 2345 struct clk *clk, *parent; 2346 struct tegra_clk_pll_freq_table cfg; 2347 unsigned long parent_rate; 2348 u32 val, val_iddq; 2349 int i; 2350 2351 if (!pll_params->div_nmp) 2352 return ERR_PTR(-EINVAL); 2353 2354 parent = __clk_lookup(parent_name); 2355 if (!parent) { 2356 WARN(1, "parent clk %s of %s must be registered first\n", 2357 parent_name, name); 2358 return ERR_PTR(-EINVAL); 2359 } 2360 2361 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2362 if (IS_ERR(pll)) 2363 return ERR_CAST(pll); 2364 2365 val = pll_readl_base(pll); 2366 val &= ~PLLSS_REF_SRC_SEL_MASK; 2367 pll_writel_base(val, pll); 2368 2369 parent_rate = clk_get_rate(parent); 2370 2371 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2372 2373 /* initialize PLL to minimum rate */ 2374 2375 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 2376 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 2377 2378 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) 2379 ; 2380 if (!i) { 2381 kfree(pll); 2382 return ERR_PTR(-EINVAL); 2383 } 2384 2385 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; 2386 2387 _update_pll_mnp(pll, &cfg); 2388 2389 pll_writel_misc(PLLSS_MISC_DEFAULT, pll); 2390 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); 2391 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); 2392 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 2393 2394 val = pll_readl_base(pll); 2395 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 2396 if (val & PLL_BASE_ENABLE) { 2397 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { 2398 WARN(1, "%s is on but IDDQ set\n", name); 2399 kfree(pll); 2400 return ERR_PTR(-EINVAL); 2401 } 2402 } else { 2403 val_iddq |= BIT(pll_params->iddq_bit_idx); 2404 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 2405 } 2406 2407 val &= ~PLLSS_LOCK_OVERRIDE; 2408 pll_writel_base(val, pll); 2409 2410 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2411 &tegra_clk_pllss_ops); 2412 2413 if (IS_ERR(clk)) 2414 kfree(pll); 2415 2416 return clk; 2417} 2418#endif 2419 2420#if defined(CONFIG_ARCH_TEGRA_210_SOC) 2421struct clk *tegra_clk_register_pllre_tegra210(const char *name, 2422 const char *parent_name, void __iomem *clk_base, 2423 void __iomem *pmc, unsigned long flags, 2424 struct tegra_clk_pll_params *pll_params, 2425 spinlock_t *lock, unsigned long parent_rate) 2426{ 2427 struct tegra_clk_pll *pll; 2428 struct clk *clk; 2429 2430 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2431 2432 if (pll_params->adjust_vco) 2433 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2434 parent_rate); 2435 2436 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2437 if (IS_ERR(pll)) 2438 return ERR_CAST(pll); 2439 2440 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2441 &tegra_clk_pll_ops); 2442 if (IS_ERR(clk)) 2443 kfree(pll); 2444 2445 return clk; 2446} 2447 2448static int clk_plle_tegra210_is_enabled(struct clk_hw *hw) 2449{ 2450 struct tegra_clk_pll *pll = to_clk_pll(hw); 2451 u32 val; 2452 2453 val = pll_readl_base(pll); 2454 2455 return val & PLLE_BASE_ENABLE ? 1 : 0; 2456} 2457 2458static int clk_plle_tegra210_enable(struct clk_hw *hw) 2459{ 2460 struct tegra_clk_pll *pll = to_clk_pll(hw); 2461 struct tegra_clk_pll_freq_table sel; 2462 u32 val; 2463 int ret = 0; 2464 unsigned long flags = 0; 2465 unsigned long input_rate; 2466 2467 if (clk_plle_tegra210_is_enabled(hw)) 2468 return 0; 2469 2470 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 2471 2472 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) 2473 return -EINVAL; 2474 2475 if (pll->lock) 2476 spin_lock_irqsave(pll->lock, flags); 2477 2478 val = pll_readl(pll->params->aux_reg, pll); 2479 if (val & PLLE_AUX_SEQ_ENABLE) 2480 goto out; 2481 2482 val = pll_readl_base(pll); 2483 val &= ~BIT(30); /* Disable lock override */ 2484 pll_writel_base(val, pll); 2485 2486 val = pll_readl_misc(pll); 2487 val |= PLLE_MISC_LOCK_ENABLE; 2488 val |= PLLE_MISC_IDDQ_SW_CTRL; 2489 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 2490 val |= PLLE_MISC_PLLE_PTS; 2491 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); 2492 pll_writel_misc(val, pll); 2493 udelay(5); 2494 2495 val = pll_readl(PLLE_SS_CTRL, pll); 2496 val |= PLLE_SS_DISABLE; 2497 pll_writel(val, PLLE_SS_CTRL, pll); 2498 2499 val = pll_readl_base(pll); 2500 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | 2501 divm_mask_shifted(pll)); 2502 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 2503 val |= sel.m << divm_shift(pll); 2504 val |= sel.n << divn_shift(pll); 2505 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 2506 pll_writel_base(val, pll); 2507 udelay(1); 2508 2509 val = pll_readl_base(pll); 2510 val |= PLLE_BASE_ENABLE; 2511 pll_writel_base(val, pll); 2512 2513 ret = clk_pll_wait_for_lock(pll); 2514 2515 if (ret < 0) 2516 goto out; 2517 2518 val = pll_readl(PLLE_SS_CTRL, pll); 2519 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); 2520 val &= ~PLLE_SS_COEFFICIENTS_MASK; 2521 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210; 2522 pll_writel(val, PLLE_SS_CTRL, pll); 2523 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); 2524 pll_writel(val, PLLE_SS_CTRL, pll); 2525 udelay(1); 2526 val &= ~PLLE_SS_CNTL_INTERP_RESET; 2527 pll_writel(val, PLLE_SS_CTRL, pll); 2528 udelay(1); 2529 2530out: 2531 if (pll->lock) 2532 spin_unlock_irqrestore(pll->lock, flags); 2533 2534 return ret; 2535} 2536 2537static void clk_plle_tegra210_disable(struct clk_hw *hw) 2538{ 2539 struct tegra_clk_pll *pll = to_clk_pll(hw); 2540 unsigned long flags = 0; 2541 u32 val; 2542 2543 if (pll->lock) 2544 spin_lock_irqsave(pll->lock, flags); 2545 2546 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */ 2547 val = pll_readl(pll->params->aux_reg, pll); 2548 if (val & PLLE_AUX_SEQ_ENABLE) 2549 goto out; 2550 2551 val = pll_readl_base(pll); 2552 val &= ~PLLE_BASE_ENABLE; 2553 pll_writel_base(val, pll); 2554 2555 val = pll_readl(pll->params->aux_reg, pll); 2556 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL; 2557 pll_writel(val, pll->params->aux_reg, pll); 2558 2559 val = pll_readl_misc(pll); 2560 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 2561 pll_writel_misc(val, pll); 2562 udelay(1); 2563 2564out: 2565 if (pll->lock) 2566 spin_unlock_irqrestore(pll->lock, flags); 2567} 2568 2569static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw) 2570{ 2571 struct tegra_clk_pll *pll = to_clk_pll(hw); 2572 2573 _clk_plle_tegra_init_parent(pll); 2574} 2575 2576static const struct clk_ops tegra_clk_plle_tegra210_ops = { 2577 .is_enabled = clk_plle_tegra210_is_enabled, 2578 .enable = clk_plle_tegra210_enable, 2579 .disable = clk_plle_tegra210_disable, 2580 .recalc_rate = clk_pll_recalc_rate, 2581 .restore_context = tegra_clk_plle_t210_restore_context, 2582}; 2583 2584struct clk *tegra_clk_register_plle_tegra210(const char *name, 2585 const char *parent_name, 2586 void __iomem *clk_base, unsigned long flags, 2587 struct tegra_clk_pll_params *pll_params, 2588 spinlock_t *lock) 2589{ 2590 struct tegra_clk_pll *pll; 2591 struct clk *clk; 2592 2593 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2594 if (IS_ERR(pll)) 2595 return ERR_CAST(pll); 2596 2597 _clk_plle_tegra_init_parent(pll); 2598 2599 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2600 &tegra_clk_plle_tegra210_ops); 2601 if (IS_ERR(clk)) 2602 kfree(pll); 2603 2604 return clk; 2605} 2606 2607struct clk *tegra_clk_register_pllc_tegra210(const char *name, 2608 const char *parent_name, void __iomem *clk_base, 2609 void __iomem *pmc, unsigned long flags, 2610 struct tegra_clk_pll_params *pll_params, 2611 spinlock_t *lock) 2612{ 2613 struct clk *parent, *clk; 2614 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 2615 struct tegra_clk_pll *pll; 2616 unsigned long parent_rate; 2617 2618 if (!p_tohw) 2619 return ERR_PTR(-EINVAL); 2620 2621 parent = __clk_lookup(parent_name); 2622 if (!parent) { 2623 WARN(1, "parent clk %s of %s must be registered first\n", 2624 name, parent_name); 2625 return ERR_PTR(-EINVAL); 2626 } 2627 2628 parent_rate = clk_get_rate(parent); 2629 2630 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2631 2632 if (pll_params->adjust_vco) 2633 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2634 parent_rate); 2635 2636 pll_params->flags |= TEGRA_PLL_BYPASS; 2637 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2638 if (IS_ERR(pll)) 2639 return ERR_CAST(pll); 2640 2641 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2642 &tegra_clk_pll_ops); 2643 if (IS_ERR(clk)) 2644 kfree(pll); 2645 2646 return clk; 2647} 2648 2649struct clk *tegra_clk_register_pllss_tegra210(const char *name, 2650 const char *parent_name, void __iomem *clk_base, 2651 unsigned long flags, 2652 struct tegra_clk_pll_params *pll_params, 2653 spinlock_t *lock) 2654{ 2655 struct tegra_clk_pll *pll; 2656 struct clk *clk, *parent; 2657 unsigned long parent_rate; 2658 u32 val; 2659 2660 if (!pll_params->div_nmp) 2661 return ERR_PTR(-EINVAL); 2662 2663 parent = __clk_lookup(parent_name); 2664 if (!parent) { 2665 WARN(1, "parent clk %s of %s must be registered first\n", 2666 name, parent_name); 2667 return ERR_PTR(-EINVAL); 2668 } 2669 2670 val = readl_relaxed(clk_base + pll_params->base_reg); 2671 if (val & PLLSS_REF_SRC_SEL_MASK) { 2672 WARN(1, "not supported reference clock for %s\n", name); 2673 return ERR_PTR(-EINVAL); 2674 } 2675 2676 parent_rate = clk_get_rate(parent); 2677 2678 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2679 2680 if (pll_params->adjust_vco) 2681 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2682 parent_rate); 2683 2684 pll_params->flags |= TEGRA_PLL_BYPASS; 2685 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 2686 if (IS_ERR(pll)) 2687 return ERR_CAST(pll); 2688 2689 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2690 &tegra_clk_pll_ops); 2691 2692 if (IS_ERR(clk)) 2693 kfree(pll); 2694 2695 return clk; 2696} 2697 2698struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 2699 void __iomem *clk_base, void __iomem *pmc, 2700 unsigned long flags, 2701 struct tegra_clk_pll_params *pll_params, 2702 spinlock_t *lock) 2703{ 2704 struct tegra_clk_pll *pll; 2705 struct clk *clk, *parent; 2706 unsigned long parent_rate; 2707 2708 if (!pll_params->pdiv_tohw) 2709 return ERR_PTR(-EINVAL); 2710 2711 parent = __clk_lookup(parent_name); 2712 if (!parent) { 2713 WARN(1, "parent clk %s of %s must be registered first\n", 2714 parent_name, name); 2715 return ERR_PTR(-EINVAL); 2716 } 2717 2718 parent_rate = clk_get_rate(parent); 2719 2720 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 2721 2722 if (pll_params->adjust_vco) 2723 pll_params->vco_min = pll_params->adjust_vco(pll_params, 2724 parent_rate); 2725 2726 pll_params->flags |= TEGRA_PLL_BYPASS; 2727 pll_params->flags |= TEGRA_PLLMB; 2728 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 2729 if (IS_ERR(pll)) 2730 return ERR_CAST(pll); 2731 2732 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2733 &tegra_clk_pll_ops); 2734 if (IS_ERR(clk)) 2735 kfree(pll); 2736 2737 return clk; 2738} 2739 2740#endif
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