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ccu-sun50i-h616.c
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linux-6.19.14/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2020 Arm Ltd. 4 * Based on the H6 CCU driver, which is: 5 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/io.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12 13#include "ccu_common.h" 14#include "ccu_reset.h" 15 16#include "ccu_div.h" 17#include "ccu_gate.h" 18#include "ccu_mp.h" 19#include "ccu_mult.h" 20#include "ccu_nk.h" 21#include "ccu_nkm.h" 22#include "ccu_nkmp.h" 23#include "ccu_nm.h" 24 25#include "ccu-sun50i-h616.h" 26 27/* 28 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However 29 * P should only be used for output frequencies lower than 288 MHz. 30 * 31 * For now we can just model it as a multiplier clock, and force P to /1. 32 * 33 * The M factor is present in the register's description, but not in the 34 * frequency formula, and it's documented as "M is only used for backdoor 35 * testing", so it's not modelled and then force to 0. 36 */ 37#define SUN50I_H616_PLL_CPUX_REG 0x000 38static struct ccu_mult pll_cpux_clk = { 39 .enable = BIT(31), 40 .lock = BIT(28), 41 .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12), 42 .common = { 43 .reg = 0x000, 44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", 45 &ccu_mult_ops, 46 CLK_SET_RATE_UNGATE), 47 }, 48}; 49 50/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ 51#define SUN50I_H616_PLL_DDR0_REG 0x010 52static struct ccu_nkmp pll_ddr0_clk = { 53 .enable = BIT(31), 54 .lock = BIT(28), 55 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 56 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 57 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 58 .common = { 59 .reg = 0x010, 60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M", 61 &ccu_nkmp_ops, 62 CLK_SET_RATE_UNGATE), 63 }, 64}; 65 66#define SUN50I_H616_PLL_DDR1_REG 0x018 67static struct ccu_nkmp pll_ddr1_clk = { 68 .enable = BIT(31), 69 .lock = BIT(28), 70 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 71 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 72 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 73 .common = { 74 .reg = 0x018, 75 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M", 76 &ccu_nkmp_ops, 77 CLK_SET_RATE_UNGATE), 78 }, 79}; 80 81#define SUN50I_H616_PLL_PERIPH0_REG 0x020 82static struct ccu_nkmp pll_periph0_clk = { 83 .enable = BIT(31), 84 .lock = BIT(28), 85 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 86 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 87 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 88 .fixed_post_div = 2, 89 .common = { 90 .reg = 0x020, 91 .features = CCU_FEATURE_FIXED_POSTDIV, 92 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 93 &ccu_nkmp_ops, 94 CLK_SET_RATE_UNGATE), 95 }, 96}; 97 98#define SUN50I_H616_PLL_PERIPH1_REG 0x028 99static struct ccu_nkmp pll_periph1_clk = { 100 .enable = BIT(31), 101 .lock = BIT(28), 102 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 103 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 104 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 105 .fixed_post_div = 2, 106 .common = { 107 .reg = 0x028, 108 .features = CCU_FEATURE_FIXED_POSTDIV, 109 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 110 &ccu_nkmp_ops, 111 CLK_SET_RATE_UNGATE), 112 }, 113}; 114 115#define SUN50I_H616_PLL_GPU_REG 0x030 116static struct ccu_nkmp pll_gpu_clk = { 117 .enable = BIT(31), 118 .lock = BIT(28), 119 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 120 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 121 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 122 .common = { 123 .reg = 0x030, 124 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", 125 &ccu_nkmp_ops, 126 CLK_SET_RATE_UNGATE), 127 }, 128}; 129 130/* 131 * For Video PLLs, the output divider is described as "used for testing" 132 * in the user manual. So it's not modelled and forced to 0. 133 */ 134#define SUN50I_H616_PLL_VIDEO0_REG 0x040 135static struct ccu_nm pll_video0_clk = { 136 .enable = BIT(31), 137 .lock = BIT(28), 138 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 139 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 140 .fixed_post_div = 4, 141 .min_rate = 288000000, 142 .max_rate = 2400000000UL, 143 .common = { 144 .reg = 0x040, 145 .features = CCU_FEATURE_FIXED_POSTDIV, 146 .hw.init = CLK_HW_INIT("pll-video0", "osc24M", 147 &ccu_nm_ops, 148 CLK_SET_RATE_UNGATE), 149 }, 150}; 151 152#define SUN50I_H616_PLL_VIDEO1_REG 0x048 153static struct ccu_nm pll_video1_clk = { 154 .enable = BIT(31), 155 .lock = BIT(28), 156 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 157 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 158 .fixed_post_div = 4, 159 .min_rate = 288000000, 160 .max_rate = 2400000000UL, 161 .common = { 162 .reg = 0x048, 163 .features = CCU_FEATURE_FIXED_POSTDIV, 164 .hw.init = CLK_HW_INIT("pll-video1", "osc24M", 165 &ccu_nm_ops, 166 CLK_SET_RATE_UNGATE), 167 }, 168}; 169 170#define SUN50I_H616_PLL_VIDEO2_REG 0x050 171static struct ccu_nm pll_video2_clk = { 172 .enable = BIT(31), 173 .lock = BIT(28), 174 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 175 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 176 .fixed_post_div = 4, 177 .min_rate = 288000000, 178 .max_rate = 2400000000UL, 179 .common = { 180 .reg = 0x050, 181 .features = CCU_FEATURE_FIXED_POSTDIV, 182 .hw.init = CLK_HW_INIT("pll-video2", "osc24M", 183 &ccu_nm_ops, 184 CLK_SET_RATE_UNGATE), 185 }, 186}; 187 188#define SUN50I_H616_PLL_VE_REG 0x058 189static struct ccu_nkmp pll_ve_clk = { 190 .enable = BIT(31), 191 .lock = BIT(28), 192 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 193 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 194 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 195 .common = { 196 .reg = 0x058, 197 .hw.init = CLK_HW_INIT("pll-ve", "osc24M", 198 &ccu_nkmp_ops, 199 CLK_SET_RATE_UNGATE), 200 }, 201}; 202 203#define SUN50I_H616_PLL_DE_REG 0x060 204static struct ccu_nkmp pll_de_clk = { 205 .enable = BIT(31), 206 .lock = BIT(28), 207 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 208 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 209 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 210 .common = { 211 .reg = 0x060, 212 .hw.init = CLK_HW_INIT("pll-de", "osc24M", 213 &ccu_nkmp_ops, 214 CLK_SET_RATE_UNGATE), 215 }, 216}; 217 218/* 219 * Sigma-delta modulation settings table obtained from the vendor SDK driver. 220 * There are additional M0 and M1 divider bits not modelled here, so forced to 221 * fixed values in the probe routine. Sigma-delta modulation allows providing a 222 * fractional-N divider in the PLL, to help reaching those specific 223 * frequencies with less error. 224 */ 225static struct ccu_sdm_setting pll_audio_sdm_table[] = { 226 { .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 }, 227 { .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 }, 228}; 229 230#define SUN50I_H616_PLL_AUDIO_REG 0x078 231static struct ccu_nm pll_audio_hs_clk = { 232 .enable = BIT(31), 233 .lock = BIT(28), 234 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 235 .m = _SUNXI_CCU_DIV(16, 6), 236 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 237 BIT(24), 0x178, BIT(31)), 238 .fixed_post_div = 2, 239 .common = { 240 .features = CCU_FEATURE_FIXED_POSTDIV | 241 CCU_FEATURE_SIGMA_DELTA_MOD, 242 .reg = 0x078, 243 .hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M", 244 &ccu_nm_ops, 245 CLK_SET_RATE_UNGATE), 246 }, 247}; 248 249static const char * const cpux_parents[] = { "osc24M", "osc32k", 250 "iosc", "pll-cpux", "pll-periph0" }; 251static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 252 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 253static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0); 254static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0); 255 256static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k", 257 "iosc", "pll-periph0" }; 258static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2", 259 psi_ahb1_ahb2_parents, 260 0x510, 261 0, 2, /* M */ 262 8, 2, /* P */ 263 24, 2, /* mux */ 264 0); 265 266static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k", 267 "psi-ahb1-ahb2", 268 "pll-periph0" }; 269static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c, 270 0, 2, /* M */ 271 8, 2, /* P */ 272 24, 2, /* mux */ 273 0); 274 275static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520, 276 0, 2, /* M */ 277 8, 2, /* P */ 278 24, 2, /* mux */ 279 0); 280 281static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524, 282 0, 2, /* M */ 283 8, 2, /* P */ 284 24, 2, /* mux */ 285 0); 286 287static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 288 "pll-ddr0", "pll-ddr1" }; 289static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540, 290 0, 3, /* M */ 291 24, 2, /* mux */ 292 BIT(31), /* gate */ 293 CLK_IS_CRITICAL); 294 295static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" }; 296static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, 297 0, 4, /* M */ 298 24, 1, /* mux */ 299 BIT(31), /* gate */ 300 CLK_SET_RATE_PARENT); 301 302static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2", 303 0x60c, BIT(0), 0); 304 305static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", 306 de_parents, 307 0x620, 308 0, 4, /* M */ 309 24, 1, /* mux */ 310 BIT(31), /* gate */ 311 0); 312 313static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2", 314 0x62c, BIT(0), 0); 315 316static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d", de_parents, 0x630, 317 0, 4, /* M */ 318 24, 1, /* mux */ 319 BIT(31), /* gate */ 320 0); 321 322static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2", 323 0x63c, BIT(0), 0); 324 325static const char * const gpu0_parents[] = { "pll-gpu", "gpu1" }; 326static SUNXI_CCU_M_WITH_MUX_GATE(gpu0_clk, "gpu0", gpu0_parents, 0x670, 327 0, 2, /* M */ 328 24, 1, /* mux */ 329 BIT(31), /* gate */ 330 CLK_SET_RATE_PARENT); 331 332/* 333 * This clk is needed as a temporary fall back during GPU PLL freq changes. 334 * Set CLK_IS_CRITICAL flag to prevent from being disabled. 335 */ 336#define SUN50I_H616_GPU_CLK1_REG 0x674 337static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674, 338 0, 2, /* M */ 339 BIT(31),/* gate */ 340 CLK_IS_CRITICAL); 341 342static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", 343 0x67c, BIT(0), 0); 344 345static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" }; 346static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680, 347 0, 4, /* M */ 348 8, 2, /* N */ 349 24, 1, /* mux */ 350 BIT(31),/* gate */ 351 0); 352 353static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2", 354 0x68c, BIT(0), 0); 355 356static const char * const ve_parents[] = { "pll-ve" }; 357static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, 358 0, 3, /* M */ 359 24, 1, /* mux */ 360 BIT(31), /* gate */ 361 CLK_SET_RATE_PARENT); 362 363static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", 364 0x69c, BIT(0), 0); 365 366static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2", 367 0x70c, BIT(0), 0); 368 369static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2", 370 0x73c, BIT(0), 0); 371 372static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0); 373 374static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2", 375 0x78c, BIT(0), 0); 376 377static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2", 378 0x79c, BIT(0), 0); 379 380static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0); 381 382static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); 383 384static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; 385static struct ccu_div dram_clk = { 386 .div = _SUNXI_CCU_DIV(0, 2), 387 .mux = _SUNXI_CCU_MUX(24, 2), 388 .common = { 389 .reg = 0x800, 390 .hw.init = CLK_HW_INIT_PARENTS("dram", 391 dram_parents, 392 &ccu_div_ops, 393 CLK_IS_CRITICAL), 394 }, 395}; 396 397static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus", 398 0x804, BIT(0), 0); 399static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus", 400 0x804, BIT(1), 0); 401static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus", 402 0x804, BIT(2), 0); 403static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus", 404 0x804, BIT(3), 0); 405static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus", 406 0x804, BIT(5), 0); 407static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus", 408 0x804, BIT(10), 0); 409 410static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2", 411 0x80c, BIT(0), CLK_IS_CRITICAL); 412 413static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0", 414 "pll-periph1", "pll-periph0-2x", 415 "pll-periph1-2x" }; 416static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810, 417 0, 4, /* M */ 418 8, 2, /* N */ 419 24, 3, /* mux */ 420 BIT(31),/* gate */ 421 0); 422 423static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814, 424 0, 4, /* M */ 425 8, 2, /* N */ 426 24, 3, /* mux */ 427 BIT(31),/* gate */ 428 0); 429 430static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0); 431 432static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", 433 "pll-periph1-2x" }; 434static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 435 0, 4, /* M */ 436 8, 2, /* N */ 437 24, 2, /* mux */ 438 BIT(31), /* gate */ 439 2, /* post-div */ 440 0); 441 442static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 443 0, 4, /* M */ 444 8, 2, /* N */ 445 24, 2, /* mux */ 446 BIT(31), /* gate */ 447 2, /* post-div */ 448 0); 449 450static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 451 0, 4, /* M */ 452 8, 2, /* N */ 453 24, 2, /* mux */ 454 BIT(31), /* gate */ 455 2, /* post-div */ 456 0); 457 458static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); 459static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); 460static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0); 461 462static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0); 463static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0); 464static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0); 465static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0); 466static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0); 467static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0); 468 469static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0); 470static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0); 471static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0); 472static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0); 473static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x91c, BIT(4), 0); 474 475static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940, 476 0, 4, /* M */ 477 8, 2, /* N */ 478 24, 3, /* mux */ 479 BIT(31),/* gate */ 480 0); 481 482static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944, 483 0, 4, /* M */ 484 8, 2, /* N */ 485 24, 3, /* mux */ 486 BIT(31),/* gate */ 487 0); 488 489static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0); 490static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0); 491 492static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970, 493 BIT(31) | BIT(30), 0); 494 495static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0); 496static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0); 497 498static const char * const ts_parents[] = { "osc24M", "pll-periph0" }; 499static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0, 500 0, 4, /* M */ 501 8, 2, /* N */ 502 24, 1, /* mux */ 503 BIT(31),/* gate */ 504 0); 505 506static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0); 507 508static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0); 509 510static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0); 511 512static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x", 513 "pll-audio-4x", "pll-audio-hs" }; 514static struct ccu_div spdif_clk = { 515 .enable = BIT(31), 516 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 517 .mux = _SUNXI_CCU_MUX(24, 2), 518 .common = { 519 .reg = 0xa20, 520 .hw.init = CLK_HW_INIT_PARENTS("spdif", 521 audio_parents, 522 &ccu_div_ops, 523 0), 524 }, 525}; 526 527static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0); 528 529static struct ccu_div dmic_clk = { 530 .enable = BIT(31), 531 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 532 .mux = _SUNXI_CCU_MUX(24, 2), 533 .common = { 534 .reg = 0xa40, 535 .hw.init = CLK_HW_INIT_PARENTS("dmic", 536 audio_parents, 537 &ccu_div_ops, 538 0), 539 }, 540}; 541 542static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0); 543 544static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_1x_clk, "audio-codec-1x", 545 audio_parents, 0xa50, 546 0, 4, /* M */ 547 24, 2, /* mux */ 548 BIT(31), /* gate */ 549 CLK_SET_RATE_PARENT); 550static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x", 551 audio_parents, 0xa54, 552 0, 4, /* M */ 553 24, 2, /* mux */ 554 BIT(31), /* gate */ 555 CLK_SET_RATE_PARENT); 556 557static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c, 558 BIT(0), 0); 559 560static struct ccu_div audio_hub_clk = { 561 .enable = BIT(31), 562 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 563 .mux = _SUNXI_CCU_MUX(24, 2), 564 .common = { 565 .reg = 0xa60, 566 .hw.init = CLK_HW_INIT_PARENTS("audio-hub", 567 audio_parents, 568 &ccu_div_ops, 569 0), 570 }, 571}; 572 573static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0); 574 575/* 576 * There are OHCI 12M clock source selection bits for the four USB 2.0 ports. 577 * We will force them to 0 (12M divided from 48M). 578 */ 579#define SUN50I_H616_USB0_CLK_REG 0xa70 580#define SUN50I_H616_USB1_CLK_REG 0xa74 581#define SUN50I_H616_USB2_CLK_REG 0xa78 582#define SUN50I_H616_USB3_CLK_REG 0xa7c 583 584static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0); 585static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0); 586 587static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0); 588static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0); 589 590static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0xa78, BIT(31), 0); 591static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0xa78, BIT(29), 0); 592 593static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0); 594static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M", 0xa7c, BIT(29), 0); 595 596static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0); 597static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0); 598static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb3", 0xa8c, BIT(2), 0); 599static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0); 600static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0); 601static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0); 602static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb3", 0xa8c, BIT(6), 0); 603static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0); 604static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0); 605 606static SUNXI_CCU_GATE(bus_keyadc_clk, "bus-keyadc", "apb1", 0xa9c, BIT(0), 0); 607 608static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-4x", 609 "pll-video2", "pll-video2-4x" }; 610static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00, 611 0, 4, /* M */ 612 24, 2, /* mux */ 613 BIT(31), /* gate */ 614 0); 615 616static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0); 617 618static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; 619static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { 620 { .index = 1, .div = 36621 }, 621}; 622 623#define SUN50I_H616_HDMI_CEC_CLK_REG 0xb10 624static struct ccu_mux hdmi_cec_clk = { 625 .enable = BIT(31) | BIT(30), 626 627 .mux = { 628 .shift = 24, 629 .width = 2, 630 631 .fixed_predivs = hdmi_cec_predivs, 632 .n_predivs = ARRAY_SIZE(hdmi_cec_predivs), 633 }, 634 635 .common = { 636 .reg = 0xb10, 637 .features = CCU_FEATURE_FIXED_PREDIV, 638 .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec", 639 hdmi_cec_parents, 640 &ccu_mux_ops, 641 0), 642 }, 643}; 644 645static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0); 646 647static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3", 648 0xb5c, BIT(0), 0); 649 650static const char * const tcon_tv_parents[] = { "pll-video0", 651 "pll-video0-4x", 652 "pll-video1", 653 "pll-video1-4x" }; 654static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", 655 tcon_tv_parents, 0xb60, 656 24, 3, /* mux */ 657 BIT(31), /* gate */ 658 CLK_SET_RATE_PARENT); 659static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", 660 tcon_tv_parents, 0xb64, 661 24, 3, /* mux */ 662 BIT(31), /* gate */ 663 CLK_SET_RATE_PARENT); 664static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", 665 0xb7c, BIT(0), 0); 666static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb3", 667 0xb7c, BIT(1), 0); 668static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", 669 tcon_tv_parents, 0xb80, 670 0, 4, /* M */ 671 8, 2, /* P */ 672 24, 3, /* mux */ 673 BIT(31), /* gate */ 674 CLK_SET_RATE_PARENT); 675static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", 676 tcon_tv_parents, 0xb84, 677 0, 4, /* M */ 678 8, 2, /* P */ 679 24, 3, /* mux */ 680 BIT(31), /* gate */ 681 CLK_SET_RATE_PARENT); 682 683static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", 684 0xb9c, BIT(0), 0); 685static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb3", 686 0xb9c, BIT(1), 0); 687 688static SUNXI_CCU_MP_WITH_MUX_GATE(tve0_clk, "tve0", 689 tcon_tv_parents, 0xbb0, 690 0, 4, /* M */ 691 8, 2, /* P */ 692 24, 3, /* mux */ 693 BIT(31), /* gate */ 694 CLK_SET_RATE_PARENT); 695 696static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3", 697 0xbbc, BIT(0), 0); 698static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb3", 699 0xbbc, BIT(1), 0); 700 701static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" }; 702static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40, 703 0, 4, /* M */ 704 24, 2, /* mux */ 705 BIT(31), /* gate */ 706 0); 707 708static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0); 709 710/* Fixed factor clocks */ 711static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0); 712 713static const struct clk_hw *clk_parent_pll_audio[] = { 714 &pll_audio_hs_clk.common.hw 715}; 716 717/* 718 * The PLL_AUDIO_4X clock defaults to 24.5714 MHz according to the manual, with 719 * a final divider of 1. The 2X and 1X clocks use 2 and 4 respectively. The 1x 720 * clock is set to either 24576000 or 22579200 for 48Khz and 44.1Khz (and 721 * multiples). 722 */ 723static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x", 724 clk_parent_pll_audio, 725 4, 1, CLK_SET_RATE_PARENT); 726static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", 727 clk_parent_pll_audio, 728 2, 1, CLK_SET_RATE_PARENT); 729static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", 730 clk_parent_pll_audio, 731 1, 1, CLK_SET_RATE_PARENT); 732 733static const struct clk_hw *pll_periph0_parents[] = { 734 &pll_periph0_clk.common.hw 735}; 736 737static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x", 738 pll_periph0_parents, 739 1, 2, 0); 740 741static const struct clk_hw *pll_periph0_2x_hws[] = { 742 &pll_periph0_2x_clk.hw 743}; 744 745static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k", 746 pll_periph0_2x_hws, 36621, 1, 0); 747 748static const struct clk_hw *pll_periph1_parents[] = { 749 &pll_periph1_clk.common.hw 750}; 751 752static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x", 753 pll_periph1_parents, 754 1, 2, 0); 755 756static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x", 757 &pll_video0_clk.common.hw, 758 1, 4, CLK_SET_RATE_PARENT); 759static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x", 760 &pll_video1_clk.common.hw, 761 1, 4, CLK_SET_RATE_PARENT); 762static CLK_FIXED_FACTOR_HW(pll_video2_4x_clk, "pll-video2-4x", 763 &pll_video2_clk.common.hw, 764 1, 4, CLK_SET_RATE_PARENT); 765 766static struct ccu_common *sun50i_h616_ccu_clks[] = { 767 &pll_cpux_clk.common, 768 &pll_ddr0_clk.common, 769 &pll_ddr1_clk.common, 770 &pll_periph0_clk.common, 771 &pll_periph1_clk.common, 772 &pll_gpu_clk.common, 773 &pll_video0_clk.common, 774 &pll_video1_clk.common, 775 &pll_video2_clk.common, 776 &pll_ve_clk.common, 777 &pll_de_clk.common, 778 &pll_audio_hs_clk.common, 779 &cpux_clk.common, 780 &axi_clk.common, 781 &cpux_apb_clk.common, 782 &psi_ahb1_ahb2_clk.common, 783 &ahb3_clk.common, 784 &apb1_clk.common, 785 &apb2_clk.common, 786 &mbus_clk.common, 787 &de_clk.common, 788 &bus_de_clk.common, 789 &deinterlace_clk.common, 790 &bus_deinterlace_clk.common, 791 &g2d_clk.common, 792 &bus_g2d_clk.common, 793 &gpu0_clk.common, 794 &bus_gpu_clk.common, 795 &gpu1_clk.common, 796 &ce_clk.common, 797 &bus_ce_clk.common, 798 &ve_clk.common, 799 &bus_ve_clk.common, 800 &bus_dma_clk.common, 801 &bus_hstimer_clk.common, 802 &avs_clk.common, 803 &bus_dbg_clk.common, 804 &bus_psi_clk.common, 805 &bus_pwm_clk.common, 806 &bus_iommu_clk.common, 807 &dram_clk.common, 808 &mbus_dma_clk.common, 809 &mbus_ve_clk.common, 810 &mbus_ce_clk.common, 811 &mbus_ts_clk.common, 812 &mbus_nand_clk.common, 813 &mbus_g2d_clk.common, 814 &bus_dram_clk.common, 815 &nand0_clk.common, 816 &nand1_clk.common, 817 &bus_nand_clk.common, 818 &mmc0_clk.common, 819 &mmc1_clk.common, 820 &mmc2_clk.common, 821 &bus_mmc0_clk.common, 822 &bus_mmc1_clk.common, 823 &bus_mmc2_clk.common, 824 &bus_uart0_clk.common, 825 &bus_uart1_clk.common, 826 &bus_uart2_clk.common, 827 &bus_uart3_clk.common, 828 &bus_uart4_clk.common, 829 &bus_uart5_clk.common, 830 &bus_i2c0_clk.common, 831 &bus_i2c1_clk.common, 832 &bus_i2c2_clk.common, 833 &bus_i2c3_clk.common, 834 &bus_i2c4_clk.common, 835 &spi0_clk.common, 836 &spi1_clk.common, 837 &bus_spi0_clk.common, 838 &bus_spi1_clk.common, 839 &emac_25m_clk.common, 840 &bus_emac0_clk.common, 841 &bus_emac1_clk.common, 842 &ts_clk.common, 843 &bus_ts_clk.common, 844 &bus_gpadc_clk.common, 845 &bus_ths_clk.common, 846 &spdif_clk.common, 847 &bus_spdif_clk.common, 848 &dmic_clk.common, 849 &bus_dmic_clk.common, 850 &audio_codec_1x_clk.common, 851 &audio_codec_4x_clk.common, 852 &bus_audio_codec_clk.common, 853 &audio_hub_clk.common, 854 &bus_audio_hub_clk.common, 855 &usb_ohci0_clk.common, 856 &usb_phy0_clk.common, 857 &usb_ohci1_clk.common, 858 &usb_phy1_clk.common, 859 &usb_ohci2_clk.common, 860 &usb_phy2_clk.common, 861 &usb_ohci3_clk.common, 862 &usb_phy3_clk.common, 863 &bus_ohci0_clk.common, 864 &bus_ohci1_clk.common, 865 &bus_ohci2_clk.common, 866 &bus_ohci3_clk.common, 867 &bus_ehci0_clk.common, 868 &bus_ehci1_clk.common, 869 &bus_ehci2_clk.common, 870 &bus_ehci3_clk.common, 871 &bus_otg_clk.common, 872 &bus_keyadc_clk.common, 873 &hdmi_clk.common, 874 &hdmi_slow_clk.common, 875 &hdmi_cec_clk.common, 876 &bus_hdmi_clk.common, 877 &bus_tcon_top_clk.common, 878 &tcon_lcd0_clk.common, 879 &tcon_lcd1_clk.common, 880 &tcon_tv0_clk.common, 881 &tcon_tv1_clk.common, 882 &bus_tcon_lcd0_clk.common, 883 &bus_tcon_lcd1_clk.common, 884 &bus_tcon_tv0_clk.common, 885 &bus_tcon_tv1_clk.common, 886 &tve0_clk.common, 887 &bus_tve_top_clk.common, 888 &bus_tve0_clk.common, 889 &hdcp_clk.common, 890 &bus_hdcp_clk.common, 891}; 892 893static struct clk_hw_onecell_data sun50i_h616_hw_clks = { 894 .hws = { 895 [CLK_OSC12M] = &osc12M_clk.hw, 896 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 897 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 898 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 899 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 900 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 901 [CLK_PLL_SYSTEM_32K] = &pll_system_32k_clk.hw, 902 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 903 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 904 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 905 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 906 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw, 907 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 908 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw, 909 [CLK_PLL_VIDEO2] = &pll_video2_clk.common.hw, 910 [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.hw, 911 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 912 [CLK_PLL_DE] = &pll_de_clk.common.hw, 913 [CLK_PLL_AUDIO_HS] = &pll_audio_hs_clk.common.hw, 914 [CLK_PLL_AUDIO_1X] = &pll_audio_1x_clk.hw, 915 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 916 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 917 [CLK_CPUX] = &cpux_clk.common.hw, 918 [CLK_AXI] = &axi_clk.common.hw, 919 [CLK_CPUX_APB] = &cpux_apb_clk.common.hw, 920 [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw, 921 [CLK_AHB3] = &ahb3_clk.common.hw, 922 [CLK_APB1] = &apb1_clk.common.hw, 923 [CLK_APB2] = &apb2_clk.common.hw, 924 [CLK_MBUS] = &mbus_clk.common.hw, 925 [CLK_DE] = &de_clk.common.hw, 926 [CLK_BUS_DE] = &bus_de_clk.common.hw, 927 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 928 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 929 [CLK_G2D] = &g2d_clk.common.hw, 930 [CLK_BUS_G2D] = &bus_g2d_clk.common.hw, 931 [CLK_GPU0] = &gpu0_clk.common.hw, 932 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 933 [CLK_GPU1] = &gpu1_clk.common.hw, 934 [CLK_CE] = &ce_clk.common.hw, 935 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 936 [CLK_VE] = &ve_clk.common.hw, 937 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 938 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 939 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 940 [CLK_AVS] = &avs_clk.common.hw, 941 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 942 [CLK_BUS_PSI] = &bus_psi_clk.common.hw, 943 [CLK_BUS_PWM] = &bus_pwm_clk.common.hw, 944 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw, 945 [CLK_DRAM] = &dram_clk.common.hw, 946 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw, 947 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw, 948 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw, 949 [CLK_MBUS_TS] = &mbus_ts_clk.common.hw, 950 [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw, 951 [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw, 952 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 953 [CLK_NAND0] = &nand0_clk.common.hw, 954 [CLK_NAND1] = &nand1_clk.common.hw, 955 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 956 [CLK_MMC0] = &mmc0_clk.common.hw, 957 [CLK_MMC1] = &mmc1_clk.common.hw, 958 [CLK_MMC2] = &mmc2_clk.common.hw, 959 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 960 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 961 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 962 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 963 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 964 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 965 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 966 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 967 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, 968 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 969 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 970 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 971 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, 972 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, 973 [CLK_SPI0] = &spi0_clk.common.hw, 974 [CLK_SPI1] = &spi1_clk.common.hw, 975 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 976 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 977 [CLK_EMAC_25M] = &emac_25m_clk.common.hw, 978 [CLK_BUS_EMAC0] = &bus_emac0_clk.common.hw, 979 [CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw, 980 [CLK_TS] = &ts_clk.common.hw, 981 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 982 [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw, 983 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 984 [CLK_SPDIF] = &spdif_clk.common.hw, 985 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 986 [CLK_DMIC] = &dmic_clk.common.hw, 987 [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw, 988 [CLK_AUDIO_CODEC_1X] = &audio_codec_1x_clk.common.hw, 989 [CLK_AUDIO_CODEC_4X] = &audio_codec_4x_clk.common.hw, 990 [CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw, 991 [CLK_AUDIO_HUB] = &audio_hub_clk.common.hw, 992 [CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw, 993 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 994 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 995 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 996 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 997 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, 998 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw, 999 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw, 1000 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw, 1001 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 1002 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, 1003 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw, 1004 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw, 1005 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 1006 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 1007 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw, 1008 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw, 1009 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 1010 [CLK_BUS_KEYADC] = &bus_keyadc_clk.common.hw, 1011 [CLK_HDMI] = &hdmi_clk.common.hw, 1012 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, 1013 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, 1014 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 1015 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw, 1016 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, 1017 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw, 1018 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw, 1019 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw, 1020 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw, 1021 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw, 1022 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, 1023 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw, 1024 [CLK_TVE0] = &tve0_clk.common.hw, 1025 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw, 1026 [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw, 1027 [CLK_HDCP] = &hdcp_clk.common.hw, 1028 [CLK_BUS_HDCP] = &bus_hdcp_clk.common.hw, 1029 }, 1030 .num = CLK_NUMBER, 1031}; 1032 1033static const struct ccu_reset_map sun50i_h616_ccu_resets[] = { 1034 [RST_MBUS] = { 0x540, BIT(30) }, 1035 1036 [RST_BUS_DE] = { 0x60c, BIT(16) }, 1037 [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) }, 1038 [RST_BUS_GPU] = { 0x67c, BIT(16) }, 1039 [RST_BUS_CE] = { 0x68c, BIT(16) }, 1040 [RST_BUS_VE] = { 0x69c, BIT(16) }, 1041 [RST_BUS_DMA] = { 0x70c, BIT(16) }, 1042 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) }, 1043 [RST_BUS_DBG] = { 0x78c, BIT(16) }, 1044 [RST_BUS_PSI] = { 0x79c, BIT(16) }, 1045 [RST_BUS_PWM] = { 0x7ac, BIT(16) }, 1046 [RST_BUS_IOMMU] = { 0x7bc, BIT(16) }, 1047 [RST_BUS_DRAM] = { 0x80c, BIT(16) }, 1048 [RST_BUS_NAND] = { 0x82c, BIT(16) }, 1049 [RST_BUS_MMC0] = { 0x84c, BIT(16) }, 1050 [RST_BUS_MMC1] = { 0x84c, BIT(17) }, 1051 [RST_BUS_MMC2] = { 0x84c, BIT(18) }, 1052 [RST_BUS_UART0] = { 0x90c, BIT(16) }, 1053 [RST_BUS_UART1] = { 0x90c, BIT(17) }, 1054 [RST_BUS_UART2] = { 0x90c, BIT(18) }, 1055 [RST_BUS_UART3] = { 0x90c, BIT(19) }, 1056 [RST_BUS_UART4] = { 0x90c, BIT(20) }, 1057 [RST_BUS_UART5] = { 0x90c, BIT(21) }, 1058 [RST_BUS_I2C0] = { 0x91c, BIT(16) }, 1059 [RST_BUS_I2C1] = { 0x91c, BIT(17) }, 1060 [RST_BUS_I2C2] = { 0x91c, BIT(18) }, 1061 [RST_BUS_I2C3] = { 0x91c, BIT(19) }, 1062 [RST_BUS_I2C4] = { 0x91c, BIT(20) }, 1063 [RST_BUS_SPI0] = { 0x96c, BIT(16) }, 1064 [RST_BUS_SPI1] = { 0x96c, BIT(17) }, 1065 [RST_BUS_EMAC0] = { 0x97c, BIT(16) }, 1066 [RST_BUS_EMAC1] = { 0x97c, BIT(17) }, 1067 [RST_BUS_TS] = { 0x9bc, BIT(16) }, 1068 [RST_BUS_GPADC] = { 0x9ec, BIT(16) }, 1069 [RST_BUS_THS] = { 0x9fc, BIT(16) }, 1070 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) }, 1071 [RST_BUS_DMIC] = { 0xa4c, BIT(16) }, 1072 [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) }, 1073 [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) }, 1074 1075 [RST_USB_PHY0] = { 0xa70, BIT(30) }, 1076 [RST_USB_PHY1] = { 0xa74, BIT(30) }, 1077 [RST_USB_PHY2] = { 0xa78, BIT(30) }, 1078 [RST_USB_PHY3] = { 0xa7c, BIT(30) }, 1079 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) }, 1080 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) }, 1081 [RST_BUS_OHCI2] = { 0xa8c, BIT(18) }, 1082 [RST_BUS_OHCI3] = { 0xa8c, BIT(19) }, 1083 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) }, 1084 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) }, 1085 [RST_BUS_EHCI2] = { 0xa8c, BIT(22) }, 1086 [RST_BUS_EHCI3] = { 0xa8c, BIT(23) }, 1087 [RST_BUS_OTG] = { 0xa8c, BIT(24) }, 1088 [RST_BUS_KEYADC] = { 0xa9c, BIT(16) }, 1089 1090 [RST_BUS_HDMI] = { 0xb1c, BIT(16) }, 1091 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) }, 1092 [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) }, 1093 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) }, 1094 [RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) }, 1095 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) }, 1096 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) }, 1097 [RST_BUS_LVDS] = { 0xbac, BIT(16) }, 1098 [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) }, 1099 [RST_BUS_TVE0] = { 0xbbc, BIT(17) }, 1100 [RST_BUS_HDCP] = { 0xc4c, BIT(16) }, 1101}; 1102 1103static const struct sunxi_ccu_desc sun50i_h616_ccu_desc = { 1104 .ccu_clks = sun50i_h616_ccu_clks, 1105 .num_ccu_clks = ARRAY_SIZE(sun50i_h616_ccu_clks), 1106 1107 .hw_clks = &sun50i_h616_hw_clks, 1108 1109 .resets = sun50i_h616_ccu_resets, 1110 .num_resets = ARRAY_SIZE(sun50i_h616_ccu_resets), 1111}; 1112 1113static const u32 pll_regs[] = { 1114 SUN50I_H616_PLL_CPUX_REG, 1115 SUN50I_H616_PLL_DDR0_REG, 1116 SUN50I_H616_PLL_DDR1_REG, 1117 SUN50I_H616_PLL_PERIPH0_REG, 1118 SUN50I_H616_PLL_PERIPH1_REG, 1119 SUN50I_H616_PLL_GPU_REG, 1120 SUN50I_H616_PLL_VIDEO0_REG, 1121 SUN50I_H616_PLL_VIDEO1_REG, 1122 SUN50I_H616_PLL_VIDEO2_REG, 1123 SUN50I_H616_PLL_VE_REG, 1124 SUN50I_H616_PLL_DE_REG, 1125 SUN50I_H616_PLL_AUDIO_REG, 1126}; 1127 1128static const u32 pll_video_regs[] = { 1129 SUN50I_H616_PLL_VIDEO0_REG, 1130 SUN50I_H616_PLL_VIDEO1_REG, 1131 SUN50I_H616_PLL_VIDEO2_REG, 1132}; 1133 1134static const u32 usb2_clk_regs[] = { 1135 SUN50I_H616_USB0_CLK_REG, 1136 SUN50I_H616_USB1_CLK_REG, 1137 SUN50I_H616_USB2_CLK_REG, 1138 SUN50I_H616_USB3_CLK_REG, 1139}; 1140 1141static struct ccu_mux_nb sun50i_h616_cpu_nb = { 1142 .common = &cpux_clk.common, 1143 .cm = &cpux_clk.mux, 1144 .delay_us = 1, /* manual doesn't really say */ 1145 .bypass_index = 4, /* PLL_PERI0@600MHz, as recommended by manual */ 1146}; 1147 1148static struct ccu_pll_nb sun50i_h616_pll_cpu_nb = { 1149 .common = &pll_cpux_clk.common, 1150 .enable = BIT(29), /* LOCK_ENABLE */ 1151 .lock = BIT(28), 1152}; 1153 1154static struct ccu_mux_nb sun50i_h616_gpu_nb = { 1155 .common = &gpu0_clk.common, 1156 .cm = &gpu0_clk.mux, 1157 .delay_us = 1, /* manual doesn't really say */ 1158 .bypass_index = 1, /* GPU_CLK1@400MHz */ 1159}; 1160 1161static struct ccu_pll_nb sun50i_h616_pll_gpu_nb = { 1162 .common = &pll_gpu_clk.common, 1163 .enable = BIT(29), /* LOCK_ENABLE */ 1164 .lock = BIT(28), 1165}; 1166 1167static int sun50i_h616_ccu_probe(struct platform_device *pdev) 1168{ 1169 void __iomem *reg; 1170 u32 val; 1171 int ret, i; 1172 1173 reg = devm_platform_ioremap_resource(pdev, 0); 1174 if (IS_ERR(reg)) 1175 return PTR_ERR(reg); 1176 1177 /* Enable the lock bits and the output enable bits on all PLLs */ 1178 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { 1179 val = readl(reg + pll_regs[i]); 1180 val |= BIT(29) | BIT(27); 1181 writel(val, reg + pll_regs[i]); 1182 } 1183 1184 /* 1185 * Force the output divider of video PLLs to 0. 1186 * 1187 * See the comment before pll-video0 definition for the reason. 1188 */ 1189 for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) { 1190 val = readl(reg + pll_video_regs[i]); 1191 val &= ~BIT(0); 1192 writel(val, reg + pll_video_regs[i]); 1193 } 1194 1195 /* 1196 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz) 1197 * 1198 * This clock mux is still mysterious, and the code just enforces 1199 * it to have a valid clock parent. 1200 */ 1201 for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) { 1202 val = readl(reg + usb2_clk_regs[i]); 1203 val &= ~GENMASK(25, 24); 1204 writel(val, reg + usb2_clk_regs[i]); 1205 } 1206 1207 /* 1208 * Set the output-divider for the pll-audio clocks (M0) to 2 and the 1209 * input divider (M1) to 1 as recommended by the manual when using 1210 * SDM. 1211 */ 1212 val = readl(reg + SUN50I_H616_PLL_AUDIO_REG); 1213 val &= ~BIT(1); 1214 val |= BIT(0); 1215 writel(val, reg + SUN50I_H616_PLL_AUDIO_REG); 1216 1217 /* 1218 * Set the input-divider for the gpu1 clock to 3, to reach a safe 400 MHz. 1219 */ 1220 val = readl(reg + SUN50I_H616_GPU_CLK1_REG); 1221 val &= ~GENMASK(1, 0); 1222 val |= 2; 1223 writel(val, reg + SUN50I_H616_GPU_CLK1_REG); 1224 1225 /* 1226 * First clock parent (osc32K) is unusable for CEC. But since there 1227 * is no good way to force parent switch (both run with same frequency), 1228 * just set second clock parent here. 1229 */ 1230 val = readl(reg + SUN50I_H616_HDMI_CEC_CLK_REG); 1231 val |= BIT(24); 1232 writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG); 1233 1234 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc); 1235 if (ret) 1236 return ret; 1237 1238 /* Reparent CPU during CPU PLL rate changes */ 1239 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, 1240 &sun50i_h616_cpu_nb); 1241 1242 /* Re-lock the CPU PLL after any rate changes */ 1243 ccu_pll_notifier_register(&sun50i_h616_pll_cpu_nb); 1244 1245 /* Reparent GPU during GPU PLL rate changes */ 1246 ccu_mux_notifier_register(pll_gpu_clk.common.hw.clk, 1247 &sun50i_h616_gpu_nb); 1248 1249 /* Re-lock the GPU PLL after any rate changes */ 1250 ccu_pll_notifier_register(&sun50i_h616_pll_gpu_nb); 1251 1252 return 0; 1253} 1254 1255static const struct of_device_id sun50i_h616_ccu_ids[] = { 1256 { .compatible = "allwinner,sun50i-h616-ccu" }, 1257 { } 1258}; 1259MODULE_DEVICE_TABLE(of, sun50i_h616_ccu_ids); 1260 1261static struct platform_driver sun50i_h616_ccu_driver = { 1262 .probe = sun50i_h616_ccu_probe, 1263 .driver = { 1264 .name = "sun50i-h616-ccu", 1265 .suppress_bind_attrs = true, 1266 .of_match_table = sun50i_h616_ccu_ids, 1267 }, 1268}; 1269module_platform_driver(sun50i_h616_ccu_driver); 1270 1271MODULE_IMPORT_NS("SUNXI_CCU"); 1272MODULE_DESCRIPTION("Support for the Allwinner H616 CCU"); 1273MODULE_LICENSE("GPL");
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