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clkgen-pll.c
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linux-6.19.14/drivers/clk/st/clkgen-pll.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2014 STMicroelectronics (R&D) Limited 4 */ 5 6/* 7 * Authors: 8 * Stephen Gallimore <stephen.gallimore@st.com>, 9 * Pankaj Dev <pankaj.dev@st.com>. 10 */ 11 12#include <linux/slab.h> 13#include <linux/of_address.h> 14#include <linux/clk.h> 15#include <linux/clk-provider.h> 16#include <linux/iopoll.h> 17 18#include "clkgen.h" 19 20static DEFINE_SPINLOCK(clkgena_c32_odf_lock); 21DEFINE_SPINLOCK(clkgen_a9_lock); 22 23/* 24 * PLL configuration register bits for PLL3200 C32 25 */ 26#define C32_NDIV_MASK (0xff) 27#define C32_IDF_MASK (0x7) 28#define C32_ODF_MASK (0x3f) 29#define C32_LDF_MASK (0x7f) 30#define C32_CP_MASK (0x1f) 31 32#define C32_MAX_ODFS (4) 33 34/* 35 * PLL configuration register bits for PLL4600 C28 36 */ 37#define C28_NDIV_MASK (0xff) 38#define C28_IDF_MASK (0x7) 39#define C28_ODF_MASK (0x3f) 40 41struct clkgen_pll_data { 42 struct clkgen_field pdn_status; 43 struct clkgen_field pdn_ctrl; 44 struct clkgen_field locked_status; 45 struct clkgen_field mdiv; 46 struct clkgen_field ndiv; 47 struct clkgen_field pdiv; 48 struct clkgen_field idf; 49 struct clkgen_field ldf; 50 struct clkgen_field cp; 51 unsigned int num_odfs; 52 struct clkgen_field odf[C32_MAX_ODFS]; 53 struct clkgen_field odf_gate[C32_MAX_ODFS]; 54 bool switch2pll_en; 55 struct clkgen_field switch2pll; 56 spinlock_t *lock; 57 const struct clk_ops *ops; 58}; 59 60struct clkgen_clk_out { 61 const char *name; 62 unsigned long flags; 63}; 64 65struct clkgen_pll_data_clks { 66 struct clkgen_pll_data *data; 67 const struct clkgen_clk_out *outputs; 68}; 69 70 71static const struct clk_ops stm_pll3200c32_ops; 72static const struct clk_ops stm_pll3200c32_a9_ops; 73static const struct clk_ops stm_pll4600c28_ops; 74 75static const struct clkgen_pll_data st_pll3200c32_cx_0 = { 76 /* 407 C0 PLL0 */ 77 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), 78 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8), 79 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24), 80 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16), 81 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0), 82 .num_odfs = 1, 83 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) }, 84 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) }, 85 .ops = &stm_pll3200c32_ops, 86}; 87 88static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = { 89 .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0, 90}; 91 92static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = { 93 { .name = "clk-s-a0-pll-odf-0", }, 94}; 95 96static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = { 97 .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0, 98 .outputs = st_pll3200c32_ax_0_clks, 99}; 100 101static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = { 102 { .name = "clk-s-c0-pll0-odf-0", }, 103}; 104 105static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = { 106 .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0, 107 .outputs = st_pll3200c32_cx_0_clks, 108}; 109 110static const struct clkgen_pll_data st_pll3200c32_cx_1 = { 111 /* 407 C0 PLL1 */ 112 .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8), 113 .pdn_ctrl = CLKGEN_FIELD(0x2c8, 0x1, 8), 114 .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24), 115 .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16), 116 .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0), 117 .num_odfs = 1, 118 .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) }, 119 .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) }, 120 .ops = &stm_pll3200c32_ops, 121}; 122 123static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = { 124 .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1, 125}; 126 127static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = { 128 { .name = "clk-s-c0-pll1-odf-0", }, 129}; 130 131static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = { 132 .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1, 133 .outputs = st_pll3200c32_cx_1_clks, 134}; 135 136static const struct clkgen_pll_data st_pll3200c32_407_a9 = { 137 /* 407 A9 */ 138 .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0), 139 .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0), 140 .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0), 141 .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0), 142 .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25), 143 .num_odfs = 1, 144 .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) }, 145 .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) }, 146 .switch2pll_en = true, 147 .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK, 1), 148 .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1), 149 .lock = &clkgen_a9_lock, 150 .ops = &stm_pll3200c32_a9_ops, 151}; 152 153static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = { 154 { .name = "clockgen-a9-pll-odf", }, 155}; 156 157static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = { 158 .data = (struct clkgen_pll_data *)&st_pll3200c32_407_a9, 159 .outputs = st_pll3200c32_407_a9_clks, 160}; 161 162static struct clkgen_pll_data st_pll4600c28_418_a9 = { 163 /* 418 A9 */ 164 .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0), 165 .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0), 166 .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0), 167 .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0), 168 .idf = CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25), 169 .num_odfs = 1, 170 .odf = { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) }, 171 .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) }, 172 .switch2pll_en = true, 173 .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1), 174 .lock = &clkgen_a9_lock, 175 .ops = &stm_pll4600c28_ops, 176}; 177 178static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = { 179 { .name = "clockgen-a9-pll-odf", }, 180}; 181 182static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = { 183 .data = (struct clkgen_pll_data *)&st_pll4600c28_418_a9, 184 .outputs = st_pll4600c28_418_a9_clks, 185}; 186 187/** 188 * DOC: Clock Generated by PLL, rate set and enabled by bootloader 189 * 190 * Traits of this clock: 191 * prepare - clk_(un)prepare only ensures parent is (un)prepared 192 * enable - clk_enable/disable only ensures parent is enabled 193 * rate - rate is fixed. No clk_set_rate support 194 * parent - fixed parent. No clk_set_parent support 195 */ 196 197/* 198 * PLL clock that is integrated in the ClockGenA instances on the STiH415 199 * and STiH416. 200 * 201 * @hw: handle between common and hardware-specific interfaces. 202 * @regs_base: base of the PLL configuration register(s). 203 * 204 */ 205struct clkgen_pll { 206 struct clk_hw hw; 207 struct clkgen_pll_data *data; 208 void __iomem *regs_base; 209 spinlock_t *lock; 210 211 u32 ndiv; 212 u32 idf; 213 u32 cp; 214}; 215 216#define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw) 217 218struct stm_pll { 219 unsigned long mdiv; 220 unsigned long ndiv; 221 unsigned long pdiv; 222 unsigned long odf; 223 unsigned long idf; 224 unsigned long ldf; 225 unsigned long cp; 226}; 227 228static int clkgen_pll_is_locked(struct clk_hw *hw) 229{ 230 struct clkgen_pll *pll = to_clkgen_pll(hw); 231 u32 locked = CLKGEN_READ(pll, locked_status); 232 233 return !!locked; 234} 235 236static int clkgen_pll_is_enabled(struct clk_hw *hw) 237{ 238 struct clkgen_pll *pll = to_clkgen_pll(hw); 239 u32 poweroff = CLKGEN_READ(pll, pdn_status); 240 return !poweroff; 241} 242 243static int __clkgen_pll_enable(struct clk_hw *hw) 244{ 245 struct clkgen_pll *pll = to_clkgen_pll(hw); 246 void __iomem *base = pll->regs_base; 247 struct clkgen_field *field = &pll->data->locked_status; 248 int ret = 0; 249 u32 reg; 250 251 if (clkgen_pll_is_enabled(hw)) 252 return 0; 253 254 CLKGEN_WRITE(pll, pdn_ctrl, 0); 255 256 ret = readl_relaxed_poll_timeout(base + field->offset, reg, 257 !!((reg >> field->shift) & field->mask), 0, 10000); 258 259 if (!ret) { 260 if (pll->data->switch2pll_en) 261 CLKGEN_WRITE(pll, switch2pll, 0); 262 263 pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__); 264 } 265 266 return ret; 267} 268 269static int clkgen_pll_enable(struct clk_hw *hw) 270{ 271 struct clkgen_pll *pll = to_clkgen_pll(hw); 272 unsigned long flags = 0; 273 int ret = 0; 274 275 if (pll->lock) 276 spin_lock_irqsave(pll->lock, flags); 277 278 ret = __clkgen_pll_enable(hw); 279 280 if (pll->lock) 281 spin_unlock_irqrestore(pll->lock, flags); 282 283 return ret; 284} 285 286static void __clkgen_pll_disable(struct clk_hw *hw) 287{ 288 struct clkgen_pll *pll = to_clkgen_pll(hw); 289 290 if (!clkgen_pll_is_enabled(hw)) 291 return; 292 293 if (pll->data->switch2pll_en) 294 CLKGEN_WRITE(pll, switch2pll, 1); 295 296 CLKGEN_WRITE(pll, pdn_ctrl, 1); 297 298 pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__); 299} 300 301static void clkgen_pll_disable(struct clk_hw *hw) 302{ 303 struct clkgen_pll *pll = to_clkgen_pll(hw); 304 unsigned long flags = 0; 305 306 if (pll->lock) 307 spin_lock_irqsave(pll->lock, flags); 308 309 __clkgen_pll_disable(hw); 310 311 if (pll->lock) 312 spin_unlock_irqrestore(pll->lock, flags); 313} 314 315static int clk_pll3200c32_get_params(unsigned long input, unsigned long output, 316 struct stm_pll *pll) 317{ 318 unsigned long i, n; 319 unsigned long deviation = ~0; 320 unsigned long new_freq; 321 long new_deviation; 322 /* Charge pump table: highest ndiv value for cp=6 to 25 */ 323 static const unsigned char cp_table[] = { 324 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 325 128, 136, 144, 152, 160, 168, 176, 184, 192 326 }; 327 328 /* Output clock range: 800Mhz to 1600Mhz */ 329 if (output < 800000000 || output > 1600000000) 330 return -EINVAL; 331 332 input /= 1000; 333 output /= 1000; 334 335 for (i = 1; i <= 7 && deviation; i++) { 336 n = i * output / (2 * input); 337 338 /* Checks */ 339 if (n < 8) 340 continue; 341 if (n > 200) 342 break; 343 344 new_freq = (input * 2 * n) / i; 345 346 new_deviation = abs(new_freq - output); 347 348 if (!new_deviation || new_deviation < deviation) { 349 pll->idf = i; 350 pll->ndiv = n; 351 deviation = new_deviation; 352 } 353 } 354 355 if (deviation == ~0) /* No solution found */ 356 return -EINVAL; 357 358 /* Computing recommended charge pump value */ 359 for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++) 360 ; 361 362 return 0; 363} 364 365static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll, 366 unsigned long *rate) 367{ 368 if (!pll->idf) 369 pll->idf = 1; 370 371 *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000; 372 373 return 0; 374} 375 376static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw, 377 unsigned long parent_rate) 378{ 379 struct clkgen_pll *pll = to_clkgen_pll(hw); 380 unsigned long ndiv, idf; 381 unsigned long rate = 0; 382 383 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw)) 384 return 0; 385 386 ndiv = CLKGEN_READ(pll, ndiv); 387 idf = CLKGEN_READ(pll, idf); 388 389 if (idf) 390 /* Note: input is divided to avoid overflow */ 391 rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000; 392 393 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 394 395 return rate; 396} 397 398static int stm_pll3200c32_determine_rate(struct clk_hw *hw, 399 struct clk_rate_request *req) 400{ 401 struct stm_pll params; 402 403 if (!clk_pll3200c32_get_params(req->best_parent_rate, req->rate, ¶ms)) 404 clk_pll3200c32_get_rate(req->best_parent_rate, ¶ms, 405 &req->rate); 406 else { 407 pr_debug("%s: %s rate %ld Invalid\n", __func__, 408 __clk_get_name(hw->clk), req->rate); 409 req->rate = 0; 410 411 return 0; 412 } 413 414 pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n", 415 __func__, __clk_get_name(hw->clk), 416 req->rate, (unsigned int)params.ndiv, 417 (unsigned int)params.idf); 418 419 return 0; 420} 421 422static int set_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate, 423 unsigned long parent_rate) 424{ 425 struct clkgen_pll *pll = to_clkgen_pll(hw); 426 struct stm_pll params; 427 long hwrate = 0; 428 unsigned long flags = 0; 429 430 if (!rate || !parent_rate) 431 return -EINVAL; 432 433 if (!clk_pll3200c32_get_params(parent_rate, rate, ¶ms)) 434 clk_pll3200c32_get_rate(parent_rate, ¶ms, &hwrate); 435 436 pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n", 437 __func__, __clk_get_name(hw->clk), 438 hwrate, (unsigned int)params.ndiv, 439 (unsigned int)params.idf); 440 441 if (!hwrate) 442 return -EINVAL; 443 444 pll->ndiv = params.ndiv; 445 pll->idf = params.idf; 446 pll->cp = params.cp; 447 448 __clkgen_pll_disable(hw); 449 450 if (pll->lock) 451 spin_lock_irqsave(pll->lock, flags); 452 453 CLKGEN_WRITE(pll, ndiv, pll->ndiv); 454 CLKGEN_WRITE(pll, idf, pll->idf); 455 CLKGEN_WRITE(pll, cp, pll->cp); 456 457 if (pll->lock) 458 spin_unlock_irqrestore(pll->lock, flags); 459 460 __clkgen_pll_enable(hw); 461 462 return 0; 463} 464 465/* PLL output structure 466 * FVCO >> /2 >> FVCOBY2 (no output) 467 * |> Divider (ODF) >> PHI 468 * 469 * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L) 470 * 471 * Rules: 472 * 4Mhz <= INFF input <= 350Mhz 473 * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz 474 * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz 475 * 1 <= i (register/dec value for IDF) <= 7 476 * 8 <= n (register/dec value for NDIV) <= 246 477 */ 478 479static int clk_pll4600c28_get_params(unsigned long input, unsigned long output, 480 struct stm_pll *pll) 481{ 482 483 unsigned long i, infin, n; 484 unsigned long deviation = ~0; 485 unsigned long new_freq, new_deviation; 486 487 /* Output clock range: 19Mhz to 3000Mhz */ 488 if (output < 19000000 || output > 3000000000u) 489 return -EINVAL; 490 491 /* For better jitter, IDF should be smallest and NDIV must be maximum */ 492 for (i = 1; i <= 7 && deviation; i++) { 493 /* INFIN checks */ 494 infin = input / i; 495 if (infin < 4000000 || infin > 50000000) 496 continue; /* Invalid case */ 497 498 n = output / (infin * 2); 499 if (n < 8 || n > 246) 500 continue; /* Invalid case */ 501 if (n < 246) 502 n++; /* To work around 'y' when n=x.y */ 503 504 for (; n >= 8 && deviation; n--) { 505 new_freq = infin * 2 * n; 506 if (new_freq < output) 507 break; /* Optimization: shorting loop */ 508 509 new_deviation = new_freq - output; 510 if (!new_deviation || new_deviation < deviation) { 511 pll->idf = i; 512 pll->ndiv = n; 513 deviation = new_deviation; 514 } 515 } 516 } 517 518 if (deviation == ~0) /* No solution found */ 519 return -EINVAL; 520 521 return 0; 522} 523 524static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll, 525 unsigned long *rate) 526{ 527 if (!pll->idf) 528 pll->idf = 1; 529 530 *rate = (input / pll->idf) * 2 * pll->ndiv; 531 532 return 0; 533} 534 535static unsigned long recalc_stm_pll4600c28(struct clk_hw *hw, 536 unsigned long parent_rate) 537{ 538 struct clkgen_pll *pll = to_clkgen_pll(hw); 539 struct stm_pll params; 540 unsigned long rate; 541 542 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw)) 543 return 0; 544 545 params.ndiv = CLKGEN_READ(pll, ndiv); 546 params.idf = CLKGEN_READ(pll, idf); 547 548 clk_pll4600c28_get_rate(parent_rate, ¶ms, &rate); 549 550 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); 551 552 return rate; 553} 554 555static int stm_pll4600c28_determine_rate(struct clk_hw *hw, 556 struct clk_rate_request *req) 557{ 558 struct stm_pll params; 559 560 if (!clk_pll4600c28_get_params(req->best_parent_rate, req->rate, ¶ms)) { 561 clk_pll4600c28_get_rate(req->best_parent_rate, ¶ms, 562 &req->rate); 563 } else { 564 pr_debug("%s: %s rate %ld Invalid\n", __func__, 565 __clk_get_name(hw->clk), req->rate); 566 req->rate = 0; 567 568 return 0; 569 } 570 571 pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n", 572 __func__, __clk_get_name(hw->clk), 573 req->rate, (unsigned int)params.ndiv, 574 (unsigned int)params.idf); 575 576 return 0; 577} 578 579static int set_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate, 580 unsigned long parent_rate) 581{ 582 struct clkgen_pll *pll = to_clkgen_pll(hw); 583 struct stm_pll params; 584 long hwrate; 585 unsigned long flags = 0; 586 587 if (!rate || !parent_rate) 588 return -EINVAL; 589 590 if (!clk_pll4600c28_get_params(parent_rate, rate, ¶ms)) { 591 clk_pll4600c28_get_rate(parent_rate, ¶ms, &hwrate); 592 } else { 593 pr_debug("%s: %s rate %ld Invalid\n", __func__, 594 __clk_get_name(hw->clk), rate); 595 return -EINVAL; 596 } 597 598 pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n", 599 __func__, __clk_get_name(hw->clk), 600 hwrate, (unsigned int)params.ndiv, 601 (unsigned int)params.idf); 602 603 if (!hwrate) 604 return -EINVAL; 605 606 pll->ndiv = params.ndiv; 607 pll->idf = params.idf; 608 609 __clkgen_pll_disable(hw); 610 611 if (pll->lock) 612 spin_lock_irqsave(pll->lock, flags); 613 614 CLKGEN_WRITE(pll, ndiv, pll->ndiv); 615 CLKGEN_WRITE(pll, idf, pll->idf); 616 617 if (pll->lock) 618 spin_unlock_irqrestore(pll->lock, flags); 619 620 __clkgen_pll_enable(hw); 621 622 return 0; 623} 624 625static const struct clk_ops stm_pll3200c32_ops = { 626 .enable = clkgen_pll_enable, 627 .disable = clkgen_pll_disable, 628 .is_enabled = clkgen_pll_is_enabled, 629 .recalc_rate = recalc_stm_pll3200c32, 630}; 631 632static const struct clk_ops stm_pll3200c32_a9_ops = { 633 .enable = clkgen_pll_enable, 634 .disable = clkgen_pll_disable, 635 .is_enabled = clkgen_pll_is_enabled, 636 .recalc_rate = recalc_stm_pll3200c32, 637 .determine_rate = stm_pll3200c32_determine_rate, 638 .set_rate = set_rate_stm_pll3200c32, 639}; 640 641static const struct clk_ops stm_pll4600c28_ops = { 642 .enable = clkgen_pll_enable, 643 .disable = clkgen_pll_disable, 644 .is_enabled = clkgen_pll_is_enabled, 645 .recalc_rate = recalc_stm_pll4600c28, 646 .determine_rate = stm_pll4600c28_determine_rate, 647 .set_rate = set_rate_stm_pll4600c28, 648}; 649 650static struct clk * __init clkgen_pll_register(const char *parent_name, 651 struct clkgen_pll_data *pll_data, 652 void __iomem *reg, unsigned long pll_flags, 653 const char *clk_name, spinlock_t *lock) 654{ 655 struct clkgen_pll *pll; 656 struct clk *clk; 657 struct clk_init_data init; 658 659 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 660 if (!pll) 661 return ERR_PTR(-ENOMEM); 662 663 init.name = clk_name; 664 init.ops = pll_data->ops; 665 666 init.flags = pll_flags | CLK_GET_RATE_NOCACHE; 667 init.parent_names = &parent_name; 668 init.num_parents = 1; 669 670 pll->data = pll_data; 671 pll->regs_base = reg; 672 pll->hw.init = &init; 673 pll->lock = lock; 674 675 clk = clk_register(NULL, &pll->hw); 676 if (IS_ERR(clk)) { 677 kfree(pll); 678 return clk; 679 } 680 681 pr_debug("%s: parent %s rate %lu\n", 682 __clk_get_name(clk), 683 __clk_get_name(clk_get_parent(clk)), 684 clk_get_rate(clk)); 685 686 return clk; 687} 688 689static void __iomem * __init clkgen_get_register_base( 690 struct device_node *np) 691{ 692 struct device_node *pnode; 693 void __iomem *reg = NULL; 694 695 pnode = of_get_parent(np); 696 if (!pnode) 697 return NULL; 698 699 reg = of_iomap(pnode, 0); 700 701 of_node_put(pnode); 702 return reg; 703} 704 705static struct clk * __init clkgen_odf_register(const char *parent_name, 706 void __iomem *reg, 707 struct clkgen_pll_data *pll_data, 708 unsigned long pll_flags, int odf, 709 spinlock_t *odf_lock, 710 const char *odf_name) 711{ 712 struct clk *clk; 713 unsigned long flags; 714 struct clk_gate *gate; 715 struct clk_divider *div; 716 717 flags = pll_flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT; 718 719 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 720 if (!gate) 721 return ERR_PTR(-ENOMEM); 722 723 gate->flags = CLK_GATE_SET_TO_DISABLE; 724 gate->reg = reg + pll_data->odf_gate[odf].offset; 725 gate->bit_idx = pll_data->odf_gate[odf].shift; 726 gate->lock = odf_lock; 727 728 div = kzalloc(sizeof(*div), GFP_KERNEL); 729 if (!div) { 730 kfree(gate); 731 return ERR_PTR(-ENOMEM); 732 } 733 734 div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; 735 div->reg = reg + pll_data->odf[odf].offset; 736 div->shift = pll_data->odf[odf].shift; 737 div->width = fls(pll_data->odf[odf].mask); 738 div->lock = odf_lock; 739 740 clk = clk_register_composite(NULL, odf_name, &parent_name, 1, 741 NULL, NULL, 742 &div->hw, &clk_divider_ops, 743 &gate->hw, &clk_gate_ops, 744 flags); 745 if (IS_ERR(clk)) 746 return clk; 747 748 pr_debug("%s: parent %s rate %lu\n", 749 __clk_get_name(clk), 750 __clk_get_name(clk_get_parent(clk)), 751 clk_get_rate(clk)); 752 return clk; 753} 754 755 756static void __init clkgen_c32_pll_setup(struct device_node *np, 757 struct clkgen_pll_data_clks *datac) 758{ 759 struct clk *clk; 760 const char *parent_name, *pll_name; 761 void __iomem *pll_base; 762 int num_odfs, odf; 763 struct clk_onecell_data *clk_data; 764 unsigned long pll_flags = 0; 765 766 767 parent_name = of_clk_get_parent_name(np, 0); 768 if (!parent_name) 769 return; 770 771 pll_base = clkgen_get_register_base(np); 772 if (!pll_base) 773 return; 774 775 of_clk_detect_critical(np, 0, &pll_flags); 776 777 clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags, 778 np->name, datac->data->lock); 779 if (IS_ERR(clk)) 780 return; 781 782 pll_name = __clk_get_name(clk); 783 784 num_odfs = datac->data->num_odfs; 785 786 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 787 if (!clk_data) 788 return; 789 790 clk_data->clk_num = num_odfs; 791 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), 792 GFP_KERNEL); 793 794 if (!clk_data->clks) 795 goto err; 796 797 for (odf = 0; odf < num_odfs; odf++) { 798 struct clk *clk; 799 const char *clk_name; 800 unsigned long odf_flags = 0; 801 802 if (datac->outputs) { 803 clk_name = datac->outputs[odf].name; 804 odf_flags = datac->outputs[odf].flags; 805 } else { 806 if (of_property_read_string_index(np, 807 "clock-output-names", 808 odf, &clk_name)) 809 return; 810 811 of_clk_detect_critical(np, odf, &odf_flags); 812 } 813 814 clk = clkgen_odf_register(pll_name, pll_base, datac->data, 815 odf_flags, odf, &clkgena_c32_odf_lock, 816 clk_name); 817 if (IS_ERR(clk)) 818 goto err; 819 820 clk_data->clks[odf] = clk; 821 } 822 823 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 824 return; 825 826err: 827 kfree(pll_name); 828 kfree(clk_data->clks); 829 kfree(clk_data); 830} 831static void __init clkgen_c32_pll0_setup(struct device_node *np) 832{ 833 clkgen_c32_pll_setup(np, 834 (struct clkgen_pll_data_clks *) &st_pll3200c32_cx_0_legacy_data); 835} 836CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup); 837 838static void __init clkgen_c32_pll0_a0_setup(struct device_node *np) 839{ 840 clkgen_c32_pll_setup(np, 841 (struct clkgen_pll_data_clks *) &st_pll3200c32_a0_data); 842} 843CLK_OF_DECLARE(c32_pll0_a0, "st,clkgen-pll0-a0", clkgen_c32_pll0_a0_setup); 844 845static void __init clkgen_c32_pll0_c0_setup(struct device_node *np) 846{ 847 clkgen_c32_pll_setup(np, 848 (struct clkgen_pll_data_clks *) &st_pll3200c32_c0_data); 849} 850CLK_OF_DECLARE(c32_pll0_c0, "st,clkgen-pll0-c0", clkgen_c32_pll0_c0_setup); 851 852static void __init clkgen_c32_pll1_setup(struct device_node *np) 853{ 854 clkgen_c32_pll_setup(np, 855 (struct clkgen_pll_data_clks *) &st_pll3200c32_cx_1_legacy_data); 856} 857CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup); 858 859static void __init clkgen_c32_pll1_c0_setup(struct device_node *np) 860{ 861 clkgen_c32_pll_setup(np, 862 (struct clkgen_pll_data_clks *) &st_pll3200c32_c1_data); 863} 864CLK_OF_DECLARE(c32_pll1_c0, "st,clkgen-pll1-c0", clkgen_c32_pll1_c0_setup); 865 866static void __init clkgen_c32_plla9_setup(struct device_node *np) 867{ 868 clkgen_c32_pll_setup(np, 869 (struct clkgen_pll_data_clks *) &st_pll3200c32_407_a9_data); 870} 871CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup); 872 873static void __init clkgen_c28_plla9_setup(struct device_node *np) 874{ 875 clkgen_c32_pll_setup(np, 876 (struct clkgen_pll_data_clks *) &st_pll4600c28_418_a9_data); 877} 878CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);
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