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ccu-k1.c
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linux-6.19.14/drivers/clk/spacemit/ccu-k1.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2024 SpacemiT Technology Co. Ltd 4 * Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org> 5 */ 6 7#include <linux/array_size.h> 8#include <linux/auxiliary_bus.h> 9#include <linux/clk-provider.h> 10#include <linux/delay.h> 11#include <linux/idr.h> 12#include <linux/mfd/syscon.h> 13#include <linux/minmax.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/slab.h> 17#include <soc/spacemit/k1-syscon.h> 18 19#include "ccu_common.h" 20#include "ccu_pll.h" 21#include "ccu_mix.h" 22#include "ccu_ddn.h" 23 24#include <dt-bindings/clock/spacemit,k1-syscon.h> 25 26struct spacemit_ccu_data { 27 const char *reset_name; 28 struct clk_hw **hws; 29 size_t num; 30}; 31 32static DEFINE_IDA(auxiliary_ids); 33 34/* APBS clocks start, APBS region contains and only contains all PLL clocks */ 35 36/* 37 * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for 38 * peripherals. 39 */ 40static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { 41 CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), 42}; 43 44static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { 45 CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), 46}; 47 48static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { 49 CCU_PLL_RATE(1600000000UL, 0x0050cd61, 0x43eaaaab), 50 CCU_PLL_RATE(1800000000UL, 0x0050cd61, 0x4b000000), 51 CCU_PLL_RATE(2000000000UL, 0x0050dd62, 0x2aeaaaab), 52 CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), 53 CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), 54 CCU_PLL_RATE(3200000000UL, 0x0050dd67, 0x43eaaaab), 55}; 56 57CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK, 58 CLK_SET_RATE_GATE); 59CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK, 60 CLK_SET_RATE_GATE); 61CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK, 62 CLK_SET_RATE_GATE); 63 64CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); 65CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); 66CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); 67CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); 68CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); 69CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); 70CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, 71 CLK_IS_CRITICAL); 72CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1); 73CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1); 74CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1); 75CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(0), 64, 1); 76CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(10), 10, 1); 77CCU_FACTOR_GATE_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(11), 100, 1); 78 79CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); 80CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); 81CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); 82CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); 83CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); 84CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); 85CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); 86CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); 87 88CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); 89CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); 90CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); 91CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); 92CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); 93CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); 94CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); 95CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); 96 97CCU_FACTOR_DEFINE(pll3_20, CCU_PARENT_HW(pll3_d8), 20, 1); 98CCU_FACTOR_DEFINE(pll3_40, CCU_PARENT_HW(pll3_d8), 10, 1); 99CCU_FACTOR_DEFINE(pll3_80, CCU_PARENT_HW(pll3_d8), 5, 1); 100 101/* APBS clocks end */ 102 103/* MPMU clocks start */ 104CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); 105 106CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); 107 108CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); 109 110CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); 111CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); 112CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); 113CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); 114CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); 115CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); 116CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); 117CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); 118CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); 119 120CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); 121CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); 122CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); 123 124CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); 125CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); 126 127CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); 128CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); 129 130CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); 131CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); 132CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); 133 134CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); 135 136CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); 137 138CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); 139CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0); 140CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0); 141 142CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); 143 144CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); 145 146static const struct clk_parent_data i2s_153p6_base_parents[] = { 147 CCU_PARENT_HW(i2s_153p6), 148 CCU_PARENT_HW(pll1_d8_307p2), 149}; 150CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0); 151 152static const struct clk_parent_data i2s_sysclk_src_parents[] = { 153 CCU_PARENT_HW(pll1_d96_25p6), 154 CCU_PARENT_HW(i2s_153p6_base) 155}; 156CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); 157 158CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); 159 160CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1); 161/* 162 * Divider of i2s_bclk always implies a 1/2 factor, which is 163 * described by i2s_bclk_factor. 164 */ 165CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR, 27, 2, BIT(29), 0); 166 167static const struct clk_parent_data apb_parents[] = { 168 CCU_PARENT_HW(pll1_d96_25p6), 169 CCU_PARENT_HW(pll1_d48_51p2), 170 CCU_PARENT_HW(pll1_d96_25p6), 171 CCU_PARENT_HW(pll1_d24_102p4), 172}; 173CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); 174 175CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); 176 177CCU_GATE_DEFINE(ripc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, 0x1, 0); 178/* MPMU clocks end */ 179 180/* APBC clocks start */ 181static const struct clk_parent_data uart_clk_parents[] = { 182 CCU_PARENT_HW(pll1_m3d128_57p6), 183 CCU_PARENT_HW(slow_uart1_14p74), 184 CCU_PARENT_HW(slow_uart2_48), 185}; 186CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART1_CLK_RST, 4, 3, BIT(1), 0); 187CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); 188CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); 189CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); 190CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); 191CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); 192CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); 193CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); 194CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); 195 196CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); 197 198static const struct clk_parent_data pwm_parents[] = { 199 CCU_PARENT_HW(pll1_d192_12p8), 200 CCU_PARENT_NAME(osc), 201}; 202CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); 203CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); 204CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); 205CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); 206CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); 207CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); 208CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); 209CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); 210CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); 211CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); 212CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); 213CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); 214CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); 215CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); 216CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); 217CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); 218CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); 219CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); 220CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); 221CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); 222 223static const struct clk_parent_data ssp_parents[] = { 224 CCU_PARENT_HW(pll1_d384_6p4), 225 CCU_PARENT_HW(pll1_d192_12p8), 226 CCU_PARENT_HW(pll1_d96_25p6), 227 CCU_PARENT_HW(pll1_d48_51p2), 228 CCU_PARENT_HW(pll1_d768_3p2), 229 CCU_PARENT_HW(pll1_d1536_1p6), 230 CCU_PARENT_HW(pll1_d3072_0p8), 231}; 232CCU_MUX_GATE_DEFINE(ssp3_clk, ssp_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); 233 234CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc), APBC_RTC_CLK_RST, 235 BIT(7) | BIT(1), 0); 236 237static const struct clk_parent_data twsi_parents[] = { 238 CCU_PARENT_HW(pll1_d78_31p5), 239 CCU_PARENT_HW(pll1_d48_51p2), 240 CCU_PARENT_HW(pll1_d40_61p44), 241}; 242CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); 243CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); 244CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); 245CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); 246CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); 247CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); 248CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0); 249/* 250 * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero. 251 * Combine functional and bus bits together as a gate to avoid sharing the 252 * write-only register between different clock hardwares. 253 */ 254CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0); 255 256static const struct clk_parent_data timer_parents[] = { 257 CCU_PARENT_HW(pll1_d192_12p8), 258 CCU_PARENT_NAME(osc), 259 CCU_PARENT_HW(pll1_d384_6p4), 260 CCU_PARENT_NAME(vctcxo_3m), 261 CCU_PARENT_NAME(vctcxo_1m), 262}; 263CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); 264CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); 265 266CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); 267 268CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); 269 270/* 271 * When i2s_bclk is selected as the parent clock of sspa, 272 * the hardware requires bit3 to be set 273 */ 274CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RST, BIT(3), 0); 275CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RST, BIT(3), 0); 276 277static const struct clk_parent_data sspa0_parents[] = { 278 CCU_PARENT_HW(pll1_d384_6p4), 279 CCU_PARENT_HW(pll1_d192_12p8), 280 CCU_PARENT_HW(pll1_d96_25p6), 281 CCU_PARENT_HW(pll1_d48_51p2), 282 CCU_PARENT_HW(pll1_d768_3p2), 283 CCU_PARENT_HW(pll1_d1536_1p6), 284 CCU_PARENT_HW(pll1_d3072_0p8), 285 CCU_PARENT_HW(sspa0_i2s_bclk), 286}; 287CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); 288 289static const struct clk_parent_data sspa1_parents[] = { 290 CCU_PARENT_HW(pll1_d384_6p4), 291 CCU_PARENT_HW(pll1_d192_12p8), 292 CCU_PARENT_HW(pll1_d96_25p6), 293 CCU_PARENT_HW(pll1_d48_51p2), 294 CCU_PARENT_HW(pll1_d768_3p2), 295 CCU_PARENT_HW(pll1_d1536_1p6), 296 CCU_PARENT_HW(pll1_d3072_0p8), 297 CCU_PARENT_HW(sspa1_i2s_bclk), 298}; 299CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); 300 301CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); 302CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0); 303CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); 304CCU_GATE_DEFINE(ipc_ap2aud_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); 305 306static const struct clk_parent_data can_parents[] = { 307 CCU_PARENT_HW(pll3_20), 308 CCU_PARENT_HW(pll3_40), 309 CCU_PARENT_HW(pll3_80), 310}; 311CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); 312CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_CAN0_CLK_RST, BIT(0), 0); 313 314CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART1_CLK_RST, BIT(0), 0); 315CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); 316CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); 317CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); 318CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); 319CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); 320CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); 321CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); 322CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); 323 324CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); 325 326CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); 327CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); 328CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); 329CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); 330CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); 331CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); 332CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); 333CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); 334CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); 335CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); 336CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); 337CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); 338CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); 339CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); 340CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); 341CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); 342CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); 343CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); 344CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); 345CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); 346 347CCU_GATE_DEFINE(ssp3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); 348 349CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); 350 351CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); 352CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); 353CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); 354CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); 355CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); 356CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); 357CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0); 358/* Placeholder to workaround quirk of the register */ 359CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1); 360 361CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); 362CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); 363 364CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); 365 366CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); 367 368CCU_GATE_DEFINE(sspa0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); 369CCU_GATE_DEFINE(sspa1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); 370 371CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); 372 373CCU_GATE_DEFINE(ipc_ap2aud_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); 374/* APBC clocks end */ 375 376/* APMU clocks start */ 377static const struct clk_parent_data pmua_aclk_parents[] = { 378 CCU_PARENT_HW(pll1_d10_245p76), 379 CCU_PARENT_HW(pll1_d8_307p2), 380}; 381CCU_MUX_DIV_FC_DEFINE(pmua_aclk, pmua_aclk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); 382 383static const struct clk_parent_data cci550_clk_parents[] = { 384 CCU_PARENT_HW(pll1_d5_491p52), 385 CCU_PARENT_HW(pll1_d4_614p4), 386 CCU_PARENT_HW(pll1_d3_819p2), 387 CCU_PARENT_HW(pll2_d3), 388}; 389CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 3, BIT(12), 0, 2, 390 CLK_IS_CRITICAL); 391 392static const struct clk_parent_data cpu_c0_hi_clk_parents[] = { 393 CCU_PARENT_HW(pll3_d2), 394 CCU_PARENT_HW(pll3_d1), 395}; 396CCU_MUX_DEFINE(cpu_c0_hi_clk, cpu_c0_hi_clk_parents, APMU_CPU_C0_CLK_CTRL, 13, 1, 0); 397static const struct clk_parent_data cpu_c0_clk_parents[] = { 398 CCU_PARENT_HW(pll1_d4_614p4), 399 CCU_PARENT_HW(pll1_d3_819p2), 400 CCU_PARENT_HW(pll1_d6_409p6), 401 CCU_PARENT_HW(pll1_d5_491p52), 402 CCU_PARENT_HW(pll1_d2_1228p8), 403 CCU_PARENT_HW(pll3_d3), 404 CCU_PARENT_HW(pll2_d3), 405 CCU_PARENT_HW(cpu_c0_hi_clk), 406}; 407CCU_MUX_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, BIT(12), 0, 3, 408 CLK_IS_CRITICAL); 409CCU_DIV_DEFINE(cpu_c0_ace_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 6, 3, 410 CLK_IS_CRITICAL); 411CCU_DIV_DEFINE(cpu_c0_tcm_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 9, 3, 412 CLK_IS_CRITICAL); 413 414static const struct clk_parent_data cpu_c1_hi_clk_parents[] = { 415 CCU_PARENT_HW(pll3_d2), 416 CCU_PARENT_HW(pll3_d1), 417}; 418CCU_MUX_DEFINE(cpu_c1_hi_clk, cpu_c1_hi_clk_parents, APMU_CPU_C1_CLK_CTRL, 13, 1, 0); 419static const struct clk_parent_data cpu_c1_clk_parents[] = { 420 CCU_PARENT_HW(pll1_d4_614p4), 421 CCU_PARENT_HW(pll1_d3_819p2), 422 CCU_PARENT_HW(pll1_d6_409p6), 423 CCU_PARENT_HW(pll1_d5_491p52), 424 CCU_PARENT_HW(pll1_d2_1228p8), 425 CCU_PARENT_HW(pll3_d3), 426 CCU_PARENT_HW(pll2_d3), 427 CCU_PARENT_HW(cpu_c1_hi_clk), 428}; 429CCU_MUX_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, BIT(12), 0, 3, 430 CLK_IS_CRITICAL); 431CCU_DIV_DEFINE(cpu_c1_ace_clk, CCU_PARENT_HW(cpu_c1_core_clk), APMU_CPU_C1_CLK_CTRL, 6, 3, 432 CLK_IS_CRITICAL); 433 434static const struct clk_parent_data jpg_parents[] = { 435 CCU_PARENT_HW(pll1_d4_614p4), 436 CCU_PARENT_HW(pll1_d6_409p6), 437 CCU_PARENT_HW(pll1_d5_491p52), 438 CCU_PARENT_HW(pll1_d3_819p2), 439 CCU_PARENT_HW(pll1_d2_1228p8), 440 CCU_PARENT_HW(pll2_d4), 441 CCU_PARENT_HW(pll2_d3), 442}; 443CCU_MUX_DIV_GATE_FC_DEFINE(jpg_clk, jpg_parents, APMU_JPG_CLK_RES_CTRL, 5, 3, BIT(15), 2, 3, 444 BIT(1), 0); 445 446static const struct clk_parent_data ccic2phy_parents[] = { 447 CCU_PARENT_HW(pll1_d24_102p4), 448 CCU_PARENT_HW(pll1_d48_51p2_ap), 449}; 450CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); 451 452static const struct clk_parent_data ccic3phy_parents[] = { 453 CCU_PARENT_HW(pll1_d24_102p4), 454 CCU_PARENT_HW(pll1_d48_51p2_ap), 455}; 456CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); 457 458static const struct clk_parent_data csi_parents[] = { 459 CCU_PARENT_HW(pll1_d5_491p52), 460 CCU_PARENT_HW(pll1_d6_409p6), 461 CCU_PARENT_HW(pll1_d4_614p4), 462 CCU_PARENT_HW(pll1_d3_819p2), 463 CCU_PARENT_HW(pll2_d2), 464 CCU_PARENT_HW(pll2_d3), 465 CCU_PARENT_HW(pll2_d4), 466 CCU_PARENT_HW(pll1_d2_1228p8), 467}; 468CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), 469 16, 3, BIT(4), 0); 470 471static const struct clk_parent_data camm_parents[] = { 472 CCU_PARENT_HW(pll1_d8_307p2), 473 CCU_PARENT_HW(pll2_d5), 474 CCU_PARENT_HW(pll1_d6_409p6), 475 CCU_PARENT_NAME(vctcxo_24m), 476}; 477CCU_MUX_DIV_GATE_DEFINE(camm0_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 478 BIT(28), 0); 479CCU_MUX_DIV_GATE_DEFINE(camm1_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 480 BIT(6), 0); 481CCU_MUX_DIV_GATE_DEFINE(camm2_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 482 BIT(3), 0); 483 484static const struct clk_parent_data isp_cpp_parents[] = { 485 CCU_PARENT_HW(pll1_d8_307p2), 486 CCU_PARENT_HW(pll1_d6_409p6), 487}; 488CCU_MUX_DIV_GATE_DEFINE(isp_cpp_clk, isp_cpp_parents, APMU_ISP_CLK_RES_CTRL, 24, 2, 26, 1, 489 BIT(28), 0); 490static const struct clk_parent_data isp_bus_parents[] = { 491 CCU_PARENT_HW(pll1_d6_409p6), 492 CCU_PARENT_HW(pll1_d5_491p52), 493 CCU_PARENT_HW(pll1_d8_307p2), 494 CCU_PARENT_HW(pll1_d10_245p76), 495}; 496CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), 497 21, 2, BIT(17), 0); 498static const struct clk_parent_data isp_parents[] = { 499 CCU_PARENT_HW(pll1_d6_409p6), 500 CCU_PARENT_HW(pll1_d5_491p52), 501 CCU_PARENT_HW(pll1_d4_614p4), 502 CCU_PARENT_HW(pll1_d8_307p2), 503}; 504CCU_MUX_DIV_GATE_FC_DEFINE(isp_clk, isp_parents, APMU_ISP_CLK_RES_CTRL, 4, 3, BIT(7), 8, 2, 505 BIT(1), 0); 506 507static const struct clk_parent_data dpumclk_parents[] = { 508 CCU_PARENT_HW(pll1_d6_409p6), 509 CCU_PARENT_HW(pll1_d5_491p52), 510 CCU_PARENT_HW(pll1_d4_614p4), 511 CCU_PARENT_HW(pll1_d8_307p2), 512}; 513CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_mclk, dpumclk_parents, APMU_LCD_CLK_RES_CTRL2, 514 APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); 515 516static const struct clk_parent_data dpuesc_parents[] = { 517 CCU_PARENT_HW(pll1_d48_51p2_ap), 518 CCU_PARENT_HW(pll1_d52_47p26), 519 CCU_PARENT_HW(pll1_d96_25p6), 520 CCU_PARENT_HW(pll1_d32_76p8), 521}; 522CCU_MUX_GATE_DEFINE(dpu_esc_clk, dpuesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); 523 524static const struct clk_parent_data dpubit_parents[] = { 525 CCU_PARENT_HW(pll1_d3_819p2), 526 CCU_PARENT_HW(pll2_d2), 527 CCU_PARENT_HW(pll2_d3), 528 CCU_PARENT_HW(pll1_d2_1228p8), 529 CCU_PARENT_HW(pll2_d4), 530 CCU_PARENT_HW(pll2_d5), 531 CCU_PARENT_HW(pll2_d7), 532 CCU_PARENT_HW(pll2_d8), 533}; 534CCU_MUX_DIV_GATE_FC_DEFINE(dpu_bit_clk, dpubit_parents, APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(31), 535 20, 3, BIT(16), 0); 536 537static const struct clk_parent_data dpupx_parents[] = { 538 CCU_PARENT_HW(pll1_d6_409p6), 539 CCU_PARENT_HW(pll1_d5_491p52), 540 CCU_PARENT_HW(pll1_d4_614p4), 541 CCU_PARENT_HW(pll1_d8_307p2), 542 CCU_PARENT_HW(pll2_d7), 543 CCU_PARENT_HW(pll2_d8), 544}; 545CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_pxclk, dpupx_parents, APMU_LCD_CLK_RES_CTRL2, 546 APMU_LCD_CLK_RES_CTRL1, 17, 4, BIT(30), 21, 3, BIT(16), 0); 547 548CCU_GATE_DEFINE(dpu_hclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_CLK_RES_CTRL1, 549 BIT(5), 0); 550 551static const struct clk_parent_data dpu_spi_parents[] = { 552 CCU_PARENT_HW(pll1_d8_307p2), 553 CCU_PARENT_HW(pll1_d6_409p6), 554 CCU_PARENT_HW(pll1_d10_245p76), 555 CCU_PARENT_HW(pll1_d11_223p4), 556 CCU_PARENT_HW(pll1_d13_189), 557 CCU_PARENT_HW(pll1_d23_106p8), 558 CCU_PARENT_HW(pll2_d3), 559 CCU_PARENT_HW(pll2_d5), 560}; 561CCU_MUX_DIV_GATE_FC_DEFINE(dpu_spi_clk, dpu_spi_parents, APMU_LCD_SPI_CLK_RES_CTRL, 8, 3, 562 BIT(7), 12, 3, BIT(1), 0); 563CCU_GATE_DEFINE(dpu_spi_hbus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(3), 0); 564CCU_GATE_DEFINE(dpu_spi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(5), 0); 565CCU_GATE_DEFINE(dpu_spi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(6), 0); 566 567static const struct clk_parent_data v2d_parents[] = { 568 CCU_PARENT_HW(pll1_d5_491p52), 569 CCU_PARENT_HW(pll1_d6_409p6), 570 CCU_PARENT_HW(pll1_d8_307p2), 571 CCU_PARENT_HW(pll1_d4_614p4), 572}; 573CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, 574 BIT(8), 0); 575 576static const struct clk_parent_data ccic_4x_parents[] = { 577 CCU_PARENT_HW(pll1_d5_491p52), 578 CCU_PARENT_HW(pll1_d6_409p6), 579 CCU_PARENT_HW(pll1_d4_614p4), 580 CCU_PARENT_HW(pll1_d3_819p2), 581 CCU_PARENT_HW(pll2_d2), 582 CCU_PARENT_HW(pll2_d3), 583 CCU_PARENT_HW(pll2_d4), 584 CCU_PARENT_HW(pll1_d2_1228p8), 585}; 586CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, 587 BIT(15), 23, 2, BIT(4), 0); 588 589static const struct clk_parent_data ccic1phy_parents[] = { 590 CCU_PARENT_HW(pll1_d24_102p4), 591 CCU_PARENT_HW(pll1_d48_51p2_ap), 592}; 593CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); 594 595CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); 596static const struct clk_parent_data sdh01_parents[] = { 597 CCU_PARENT_HW(pll1_d6_409p6), 598 CCU_PARENT_HW(pll1_d4_614p4), 599 CCU_PARENT_HW(pll2_d8), 600 CCU_PARENT_HW(pll2_d5), 601 CCU_PARENT_HW(pll1_d11_223p4), 602 CCU_PARENT_HW(pll1_d13_189), 603 CCU_PARENT_HW(pll1_d23_106p8), 604}; 605CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 606 BIT(4), 0); 607CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 608 BIT(4), 0); 609static const struct clk_parent_data sdh2_parents[] = { 610 CCU_PARENT_HW(pll1_d6_409p6), 611 CCU_PARENT_HW(pll1_d4_614p4), 612 CCU_PARENT_HW(pll2_d8), 613 CCU_PARENT_HW(pll1_d3_819p2), 614 CCU_PARENT_HW(pll1_d11_223p4), 615 CCU_PARENT_HW(pll1_d13_189), 616 CCU_PARENT_HW(pll1_d23_106p8), 617}; 618CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 619 BIT(4), 0); 620 621CCU_GATE_DEFINE(usb_axi_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); 622CCU_GATE_DEFINE(usb_p1_aclk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(5), 0); 623CCU_GATE_DEFINE(usb30_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); 624 625static const struct clk_parent_data qspi_parents[] = { 626 CCU_PARENT_HW(pll1_d6_409p6), 627 CCU_PARENT_HW(pll2_d8), 628 CCU_PARENT_HW(pll1_d8_307p2), 629 CCU_PARENT_HW(pll1_d10_245p76), 630 CCU_PARENT_HW(pll1_d11_223p4), 631 CCU_PARENT_HW(pll1_d23_106p8), 632 CCU_PARENT_HW(pll1_d5_491p52), 633 CCU_PARENT_HW(pll1_d13_189), 634}; 635CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, BIT(12), 6, 3, 636 BIT(4), 0); 637CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); 638CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(pmua_aclk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); 639 640static const struct clk_parent_data aes_parents[] = { 641 CCU_PARENT_HW(pll1_d12_204p8), 642 CCU_PARENT_HW(pll1_d24_102p4), 643}; 644CCU_MUX_GATE_DEFINE(aes_clk, aes_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); 645 646static const struct clk_parent_data vpu_parents[] = { 647 CCU_PARENT_HW(pll1_d4_614p4), 648 CCU_PARENT_HW(pll1_d5_491p52), 649 CCU_PARENT_HW(pll1_d3_819p2), 650 CCU_PARENT_HW(pll1_d6_409p6), 651 CCU_PARENT_HW(pll3_d6), 652 CCU_PARENT_HW(pll2_d3), 653 CCU_PARENT_HW(pll2_d4), 654 CCU_PARENT_HW(pll2_d5), 655}; 656CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, BIT(21), 10, 3, 657 BIT(3), 0); 658 659static const struct clk_parent_data gpu_parents[] = { 660 CCU_PARENT_HW(pll1_d4_614p4), 661 CCU_PARENT_HW(pll1_d5_491p52), 662 CCU_PARENT_HW(pll1_d3_819p2), 663 CCU_PARENT_HW(pll1_d6_409p6), 664 CCU_PARENT_HW(pll3_d6), 665 CCU_PARENT_HW(pll2_d3), 666 CCU_PARENT_HW(pll2_d4), 667 CCU_PARENT_HW(pll2_d5), 668}; 669CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, BIT(15), 18, 3, 670 BIT(4), 0); 671 672static const struct clk_parent_data emmc_parents[] = { 673 CCU_PARENT_HW(pll1_d6_409p6), 674 CCU_PARENT_HW(pll1_d4_614p4), 675 CCU_PARENT_HW(pll1_d52_47p26), 676 CCU_PARENT_HW(pll1_d3_819p2), 677}; 678CCU_MUX_DIV_GATE_FC_DEFINE(emmc_clk, emmc_parents, APMU_PMUA_EM_CLK_RES_CTRL, 8, 3, BIT(11), 679 6, 2, BIT(4), 0); 680CCU_DIV_GATE_DEFINE(emmc_x_clk, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMUA_EM_CLK_RES_CTRL, 12, 681 3, BIT(15), 0); 682 683static const struct clk_parent_data audio_parents[] = { 684 CCU_PARENT_HW(pll1_aud_245p7), 685 CCU_PARENT_HW(pll1_d8_307p2), 686 CCU_PARENT_HW(pll1_d6_409p6), 687}; 688CCU_MUX_DIV_GATE_FC_DEFINE(audio_clk, audio_parents, APMU_AUDIO_CLK_RES_CTRL, 4, 3, BIT(15), 689 7, 3, BIT(12), 0); 690 691static const struct clk_parent_data hdmi_parents[] = { 692 CCU_PARENT_HW(pll1_d6_409p6), 693 CCU_PARENT_HW(pll1_d5_491p52), 694 CCU_PARENT_HW(pll1_d4_614p4), 695 CCU_PARENT_HW(pll1_d8_307p2), 696}; 697CCU_MUX_DIV_GATE_FC_DEFINE(hdmi_mclk, hdmi_parents, APMU_HDMI_CLK_RES_CTRL, 1, 4, BIT(29), 5, 698 3, BIT(0), 0); 699 700CCU_GATE_DEFINE(pcie0_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(2), 0); 701CCU_GATE_DEFINE(pcie0_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(1), 0); 702CCU_GATE_DEFINE(pcie0_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(0), 0); 703 704CCU_GATE_DEFINE(pcie1_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(2), 0); 705CCU_GATE_DEFINE(pcie1_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(1), 0); 706CCU_GATE_DEFINE(pcie1_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(0), 0); 707 708CCU_GATE_DEFINE(pcie2_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(2), 0); 709CCU_GATE_DEFINE(pcie2_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(1), 0); 710CCU_GATE_DEFINE(pcie2_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(0), 0); 711 712CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); 713CCU_GATE_DEFINE(emac0_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC0_CLK_RES_CTRL, BIT(15), 0); 714CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); 715CCU_GATE_DEFINE(emac1_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC1_CLK_RES_CTRL, BIT(15), 0); 716 717CCU_GATE_DEFINE(emmc_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_PMUA_EM_CLK_RES_CTRL, BIT(3), 0); 718/* APMU clocks end */ 719 720static struct clk_hw *k1_ccu_pll_hws[] = { 721 [CLK_PLL1] = &pll1.common.hw, 722 [CLK_PLL2] = &pll2.common.hw, 723 [CLK_PLL3] = &pll3.common.hw, 724 [CLK_PLL1_D2] = &pll1_d2.common.hw, 725 [CLK_PLL1_D3] = &pll1_d3.common.hw, 726 [CLK_PLL1_D4] = &pll1_d4.common.hw, 727 [CLK_PLL1_D5] = &pll1_d5.common.hw, 728 [CLK_PLL1_D6] = &pll1_d6.common.hw, 729 [CLK_PLL1_D7] = &pll1_d7.common.hw, 730 [CLK_PLL1_D8] = &pll1_d8.common.hw, 731 [CLK_PLL1_D11] = &pll1_d11_223p4.common.hw, 732 [CLK_PLL1_D13] = &pll1_d13_189.common.hw, 733 [CLK_PLL1_D23] = &pll1_d23_106p8.common.hw, 734 [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, 735 [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, 736 [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, 737 [CLK_PLL2_D1] = &pll2_d1.common.hw, 738 [CLK_PLL2_D2] = &pll2_d2.common.hw, 739 [CLK_PLL2_D3] = &pll2_d3.common.hw, 740 [CLK_PLL2_D4] = &pll2_d4.common.hw, 741 [CLK_PLL2_D5] = &pll2_d5.common.hw, 742 [CLK_PLL2_D6] = &pll2_d6.common.hw, 743 [CLK_PLL2_D7] = &pll2_d7.common.hw, 744 [CLK_PLL2_D8] = &pll2_d8.common.hw, 745 [CLK_PLL3_D1] = &pll3_d1.common.hw, 746 [CLK_PLL3_D2] = &pll3_d2.common.hw, 747 [CLK_PLL3_D3] = &pll3_d3.common.hw, 748 [CLK_PLL3_D4] = &pll3_d4.common.hw, 749 [CLK_PLL3_D5] = &pll3_d5.common.hw, 750 [CLK_PLL3_D6] = &pll3_d6.common.hw, 751 [CLK_PLL3_D7] = &pll3_d7.common.hw, 752 [CLK_PLL3_D8] = &pll3_d8.common.hw, 753 [CLK_PLL3_80] = &pll3_80.common.hw, 754 [CLK_PLL3_40] = &pll3_40.common.hw, 755 [CLK_PLL3_20] = &pll3_20.common.hw, 756}; 757 758static const struct spacemit_ccu_data k1_ccu_pll_data = { 759 /* The PLL CCU implements no resets */ 760 .hws = k1_ccu_pll_hws, 761 .num = ARRAY_SIZE(k1_ccu_pll_hws), 762}; 763 764static struct clk_hw *k1_ccu_mpmu_hws[] = { 765 [CLK_PLL1_307P2] = &pll1_d8_307p2.common.hw, 766 [CLK_PLL1_76P8] = &pll1_d32_76p8.common.hw, 767 [CLK_PLL1_61P44] = &pll1_d40_61p44.common.hw, 768 [CLK_PLL1_153P6] = &pll1_d16_153p6.common.hw, 769 [CLK_PLL1_102P4] = &pll1_d24_102p4.common.hw, 770 [CLK_PLL1_51P2] = &pll1_d48_51p2.common.hw, 771 [CLK_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, 772 [CLK_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, 773 [CLK_PLL1_25P6] = &pll1_d96_25p6.common.hw, 774 [CLK_PLL1_12P8] = &pll1_d192_12p8.common.hw, 775 [CLK_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, 776 [CLK_PLL1_6P4] = &pll1_d384_6p4.common.hw, 777 [CLK_PLL1_3P2] = &pll1_d768_3p2.common.hw, 778 [CLK_PLL1_1P6] = &pll1_d1536_1p6.common.hw, 779 [CLK_PLL1_0P8] = &pll1_d3072_0p8.common.hw, 780 [CLK_PLL1_409P6] = &pll1_d6_409p6.common.hw, 781 [CLK_PLL1_204P8] = &pll1_d12_204p8.common.hw, 782 [CLK_PLL1_491] = &pll1_d5_491p52.common.hw, 783 [CLK_PLL1_245P76] = &pll1_d10_245p76.common.hw, 784 [CLK_PLL1_614] = &pll1_d4_614p4.common.hw, 785 [CLK_PLL1_47P26] = &pll1_d52_47p26.common.hw, 786 [CLK_PLL1_31P5] = &pll1_d78_31p5.common.hw, 787 [CLK_PLL1_819] = &pll1_d3_819p2.common.hw, 788 [CLK_PLL1_1228] = &pll1_d2_1228p8.common.hw, 789 [CLK_SLOW_UART] = &slow_uart.common.hw, 790 [CLK_SLOW_UART1] = &slow_uart1_14p74.common.hw, 791 [CLK_SLOW_UART2] = &slow_uart2_48.common.hw, 792 [CLK_WDT] = &wdt_clk.common.hw, 793 [CLK_RIPC] = &ripc_clk.common.hw, 794 [CLK_I2S_SYSCLK] = &i2s_sysclk.common.hw, 795 [CLK_I2S_BCLK] = &i2s_bclk.common.hw, 796 [CLK_APB] = &apb_clk.common.hw, 797 [CLK_WDT_BUS] = &wdt_bus_clk.common.hw, 798 [CLK_I2S_153P6] = &i2s_153p6.common.hw, 799 [CLK_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, 800 [CLK_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, 801 [CLK_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw, 802}; 803 804static const struct spacemit_ccu_data k1_ccu_mpmu_data = { 805 .reset_name = "mpmu-reset", 806 .hws = k1_ccu_mpmu_hws, 807 .num = ARRAY_SIZE(k1_ccu_mpmu_hws), 808}; 809 810static struct clk_hw *k1_ccu_apbc_hws[] = { 811 [CLK_UART0] = &uart0_clk.common.hw, 812 [CLK_UART2] = &uart2_clk.common.hw, 813 [CLK_UART3] = &uart3_clk.common.hw, 814 [CLK_UART4] = &uart4_clk.common.hw, 815 [CLK_UART5] = &uart5_clk.common.hw, 816 [CLK_UART6] = &uart6_clk.common.hw, 817 [CLK_UART7] = &uart7_clk.common.hw, 818 [CLK_UART8] = &uart8_clk.common.hw, 819 [CLK_UART9] = &uart9_clk.common.hw, 820 [CLK_GPIO] = &gpio_clk.common.hw, 821 [CLK_PWM0] = &pwm0_clk.common.hw, 822 [CLK_PWM1] = &pwm1_clk.common.hw, 823 [CLK_PWM2] = &pwm2_clk.common.hw, 824 [CLK_PWM3] = &pwm3_clk.common.hw, 825 [CLK_PWM4] = &pwm4_clk.common.hw, 826 [CLK_PWM5] = &pwm5_clk.common.hw, 827 [CLK_PWM6] = &pwm6_clk.common.hw, 828 [CLK_PWM7] = &pwm7_clk.common.hw, 829 [CLK_PWM8] = &pwm8_clk.common.hw, 830 [CLK_PWM9] = &pwm9_clk.common.hw, 831 [CLK_PWM10] = &pwm10_clk.common.hw, 832 [CLK_PWM11] = &pwm11_clk.common.hw, 833 [CLK_PWM12] = &pwm12_clk.common.hw, 834 [CLK_PWM13] = &pwm13_clk.common.hw, 835 [CLK_PWM14] = &pwm14_clk.common.hw, 836 [CLK_PWM15] = &pwm15_clk.common.hw, 837 [CLK_PWM16] = &pwm16_clk.common.hw, 838 [CLK_PWM17] = &pwm17_clk.common.hw, 839 [CLK_PWM18] = &pwm18_clk.common.hw, 840 [CLK_PWM19] = &pwm19_clk.common.hw, 841 [CLK_SSP3] = &ssp3_clk.common.hw, 842 [CLK_RTC] = &rtc_clk.common.hw, 843 [CLK_TWSI0] = &twsi0_clk.common.hw, 844 [CLK_TWSI1] = &twsi1_clk.common.hw, 845 [CLK_TWSI2] = &twsi2_clk.common.hw, 846 [CLK_TWSI4] = &twsi4_clk.common.hw, 847 [CLK_TWSI5] = &twsi5_clk.common.hw, 848 [CLK_TWSI6] = &twsi6_clk.common.hw, 849 [CLK_TWSI7] = &twsi7_clk.common.hw, 850 [CLK_TWSI8] = &twsi8_clk.common.hw, 851 [CLK_TIMERS1] = &timers1_clk.common.hw, 852 [CLK_TIMERS2] = &timers2_clk.common.hw, 853 [CLK_AIB] = &aib_clk.common.hw, 854 [CLK_ONEWIRE] = &onewire_clk.common.hw, 855 [CLK_SSPA0] = &sspa0_clk.common.hw, 856 [CLK_SSPA1] = &sspa1_clk.common.hw, 857 [CLK_DRO] = &dro_clk.common.hw, 858 [CLK_IR] = &ir_clk.common.hw, 859 [CLK_TSEN] = &tsen_clk.common.hw, 860 [CLK_IPC_AP2AUD] = &ipc_ap2aud_clk.common.hw, 861 [CLK_CAN0] = &can0_clk.common.hw, 862 [CLK_CAN0_BUS] = &can0_bus_clk.common.hw, 863 [CLK_UART0_BUS] = &uart0_bus_clk.common.hw, 864 [CLK_UART2_BUS] = &uart2_bus_clk.common.hw, 865 [CLK_UART3_BUS] = &uart3_bus_clk.common.hw, 866 [CLK_UART4_BUS] = &uart4_bus_clk.common.hw, 867 [CLK_UART5_BUS] = &uart5_bus_clk.common.hw, 868 [CLK_UART6_BUS] = &uart6_bus_clk.common.hw, 869 [CLK_UART7_BUS] = &uart7_bus_clk.common.hw, 870 [CLK_UART8_BUS] = &uart8_bus_clk.common.hw, 871 [CLK_UART9_BUS] = &uart9_bus_clk.common.hw, 872 [CLK_GPIO_BUS] = &gpio_bus_clk.common.hw, 873 [CLK_PWM0_BUS] = &pwm0_bus_clk.common.hw, 874 [CLK_PWM1_BUS] = &pwm1_bus_clk.common.hw, 875 [CLK_PWM2_BUS] = &pwm2_bus_clk.common.hw, 876 [CLK_PWM3_BUS] = &pwm3_bus_clk.common.hw, 877 [CLK_PWM4_BUS] = &pwm4_bus_clk.common.hw, 878 [CLK_PWM5_BUS] = &pwm5_bus_clk.common.hw, 879 [CLK_PWM6_BUS] = &pwm6_bus_clk.common.hw, 880 [CLK_PWM7_BUS] = &pwm7_bus_clk.common.hw, 881 [CLK_PWM8_BUS] = &pwm8_bus_clk.common.hw, 882 [CLK_PWM9_BUS] = &pwm9_bus_clk.common.hw, 883 [CLK_PWM10_BUS] = &pwm10_bus_clk.common.hw, 884 [CLK_PWM11_BUS] = &pwm11_bus_clk.common.hw, 885 [CLK_PWM12_BUS] = &pwm12_bus_clk.common.hw, 886 [CLK_PWM13_BUS] = &pwm13_bus_clk.common.hw, 887 [CLK_PWM14_BUS] = &pwm14_bus_clk.common.hw, 888 [CLK_PWM15_BUS] = &pwm15_bus_clk.common.hw, 889 [CLK_PWM16_BUS] = &pwm16_bus_clk.common.hw, 890 [CLK_PWM17_BUS] = &pwm17_bus_clk.common.hw, 891 [CLK_PWM18_BUS] = &pwm18_bus_clk.common.hw, 892 [CLK_PWM19_BUS] = &pwm19_bus_clk.common.hw, 893 [CLK_SSP3_BUS] = &ssp3_bus_clk.common.hw, 894 [CLK_RTC_BUS] = &rtc_bus_clk.common.hw, 895 [CLK_TWSI0_BUS] = &twsi0_bus_clk.common.hw, 896 [CLK_TWSI1_BUS] = &twsi1_bus_clk.common.hw, 897 [CLK_TWSI2_BUS] = &twsi2_bus_clk.common.hw, 898 [CLK_TWSI4_BUS] = &twsi4_bus_clk.common.hw, 899 [CLK_TWSI5_BUS] = &twsi5_bus_clk.common.hw, 900 [CLK_TWSI6_BUS] = &twsi6_bus_clk.common.hw, 901 [CLK_TWSI7_BUS] = &twsi7_bus_clk.common.hw, 902 [CLK_TWSI8_BUS] = &twsi8_bus_clk.common.hw, 903 [CLK_TIMERS1_BUS] = &timers1_bus_clk.common.hw, 904 [CLK_TIMERS2_BUS] = &timers2_bus_clk.common.hw, 905 [CLK_AIB_BUS] = &aib_bus_clk.common.hw, 906 [CLK_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, 907 [CLK_SSPA0_BUS] = &sspa0_bus_clk.common.hw, 908 [CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw, 909 [CLK_TSEN_BUS] = &tsen_bus_clk.common.hw, 910 [CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw, 911 [CLK_SSPA0_I2S_BCLK] = &sspa0_i2s_bclk.common.hw, 912 [CLK_SSPA1_I2S_BCLK] = &sspa1_i2s_bclk.common.hw, 913}; 914 915static const struct spacemit_ccu_data k1_ccu_apbc_data = { 916 .reset_name = "apbc-reset", 917 .hws = k1_ccu_apbc_hws, 918 .num = ARRAY_SIZE(k1_ccu_apbc_hws), 919}; 920 921static struct clk_hw *k1_ccu_apmu_hws[] = { 922 [CLK_CCI550] = &cci550_clk.common.hw, 923 [CLK_CPU_C0_HI] = &cpu_c0_hi_clk.common.hw, 924 [CLK_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, 925 [CLK_CPU_C0_ACE] = &cpu_c0_ace_clk.common.hw, 926 [CLK_CPU_C0_TCM] = &cpu_c0_tcm_clk.common.hw, 927 [CLK_CPU_C1_HI] = &cpu_c1_hi_clk.common.hw, 928 [CLK_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, 929 [CLK_CPU_C1_ACE] = &cpu_c1_ace_clk.common.hw, 930 [CLK_CCIC_4X] = &ccic_4x_clk.common.hw, 931 [CLK_CCIC1PHY] = &ccic1phy_clk.common.hw, 932 [CLK_SDH_AXI] = &sdh_axi_aclk.common.hw, 933 [CLK_SDH0] = &sdh0_clk.common.hw, 934 [CLK_SDH1] = &sdh1_clk.common.hw, 935 [CLK_SDH2] = &sdh2_clk.common.hw, 936 [CLK_USB_P1] = &usb_p1_aclk.common.hw, 937 [CLK_USB_AXI] = &usb_axi_clk.common.hw, 938 [CLK_USB30] = &usb30_clk.common.hw, 939 [CLK_QSPI] = &qspi_clk.common.hw, 940 [CLK_QSPI_BUS] = &qspi_bus_clk.common.hw, 941 [CLK_DMA] = &dma_clk.common.hw, 942 [CLK_AES] = &aes_clk.common.hw, 943 [CLK_VPU] = &vpu_clk.common.hw, 944 [CLK_GPU] = &gpu_clk.common.hw, 945 [CLK_EMMC] = &emmc_clk.common.hw, 946 [CLK_EMMC_X] = &emmc_x_clk.common.hw, 947 [CLK_AUDIO] = &audio_clk.common.hw, 948 [CLK_HDMI] = &hdmi_mclk.common.hw, 949 [CLK_PMUA_ACLK] = &pmua_aclk.common.hw, 950 [CLK_PCIE0_MASTER] = &pcie0_master_clk.common.hw, 951 [CLK_PCIE0_SLAVE] = &pcie0_slave_clk.common.hw, 952 [CLK_PCIE0_DBI] = &pcie0_dbi_clk.common.hw, 953 [CLK_PCIE1_MASTER] = &pcie1_master_clk.common.hw, 954 [CLK_PCIE1_SLAVE] = &pcie1_slave_clk.common.hw, 955 [CLK_PCIE1_DBI] = &pcie1_dbi_clk.common.hw, 956 [CLK_PCIE2_MASTER] = &pcie2_master_clk.common.hw, 957 [CLK_PCIE2_SLAVE] = &pcie2_slave_clk.common.hw, 958 [CLK_PCIE2_DBI] = &pcie2_dbi_clk.common.hw, 959 [CLK_EMAC0_BUS] = &emac0_bus_clk.common.hw, 960 [CLK_EMAC0_PTP] = &emac0_ptp_clk.common.hw, 961 [CLK_EMAC1_BUS] = &emac1_bus_clk.common.hw, 962 [CLK_EMAC1_PTP] = &emac1_ptp_clk.common.hw, 963 [CLK_JPG] = &jpg_clk.common.hw, 964 [CLK_CCIC2PHY] = &ccic2phy_clk.common.hw, 965 [CLK_CCIC3PHY] = &ccic3phy_clk.common.hw, 966 [CLK_CSI] = &csi_clk.common.hw, 967 [CLK_CAMM0] = &camm0_clk.common.hw, 968 [CLK_CAMM1] = &camm1_clk.common.hw, 969 [CLK_CAMM2] = &camm2_clk.common.hw, 970 [CLK_ISP_CPP] = &isp_cpp_clk.common.hw, 971 [CLK_ISP_BUS] = &isp_bus_clk.common.hw, 972 [CLK_ISP] = &isp_clk.common.hw, 973 [CLK_DPU_MCLK] = &dpu_mclk.common.hw, 974 [CLK_DPU_ESC] = &dpu_esc_clk.common.hw, 975 [CLK_DPU_BIT] = &dpu_bit_clk.common.hw, 976 [CLK_DPU_PXCLK] = &dpu_pxclk.common.hw, 977 [CLK_DPU_HCLK] = &dpu_hclk.common.hw, 978 [CLK_DPU_SPI] = &dpu_spi_clk.common.hw, 979 [CLK_DPU_SPI_HBUS] = &dpu_spi_hbus_clk.common.hw, 980 [CLK_DPU_SPIBUS] = &dpu_spi_bus_clk.common.hw, 981 [CLK_DPU_SPI_ACLK] = &dpu_spi_aclk.common.hw, 982 [CLK_V2D] = &v2d_clk.common.hw, 983 [CLK_EMMC_BUS] = &emmc_bus_clk.common.hw, 984}; 985 986static const struct spacemit_ccu_data k1_ccu_apmu_data = { 987 .reset_name = "apmu-reset", 988 .hws = k1_ccu_apmu_hws, 989 .num = ARRAY_SIZE(k1_ccu_apmu_hws), 990}; 991 992static const struct spacemit_ccu_data k1_ccu_rcpu_data = { 993 .reset_name = "rcpu-reset", 994}; 995 996static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { 997 .reset_name = "rcpu2-reset", 998}; 999 1000static const struct spacemit_ccu_data k1_ccu_apbc2_data = { 1001 .reset_name = "apbc2-reset", 1002}; 1003 1004static int spacemit_ccu_register(struct device *dev, 1005 struct regmap *regmap, 1006 struct regmap *lock_regmap, 1007 const struct spacemit_ccu_data *data) 1008{ 1009 struct clk_hw_onecell_data *clk_data; 1010 int i, ret; 1011 1012 /* Nothing to do if the CCU does not implement any clocks */ 1013 if (!data->hws) 1014 return 0; 1015 1016 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), 1017 GFP_KERNEL); 1018 if (!clk_data) 1019 return -ENOMEM; 1020 1021 clk_data->num = data->num; 1022 1023 for (i = 0; i < data->num; i++) { 1024 struct clk_hw *hw = data->hws[i]; 1025 struct ccu_common *common; 1026 const char *name; 1027 1028 if (!hw) { 1029 clk_data->hws[i] = ERR_PTR(-ENOENT); 1030 continue; 1031 } 1032 1033 name = hw->init->name; 1034 1035 common = hw_to_ccu_common(hw); 1036 common->regmap = regmap; 1037 common->lock_regmap = lock_regmap; 1038 1039 ret = devm_clk_hw_register(dev, hw); 1040 if (ret) { 1041 dev_err(dev, "Cannot register clock %d - %s\n", 1042 i, name); 1043 return ret; 1044 } 1045 1046 clk_data->hws[i] = hw; 1047 } 1048 1049 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); 1050 if (ret) 1051 dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); 1052 1053 return ret; 1054} 1055 1056static void spacemit_cadev_release(struct device *dev) 1057{ 1058 struct auxiliary_device *adev = to_auxiliary_dev(dev); 1059 1060 ida_free(&auxiliary_ids, adev->id); 1061 kfree(to_spacemit_ccu_adev(adev)); 1062} 1063 1064static void spacemit_adev_unregister(void *data) 1065{ 1066 struct auxiliary_device *adev = data; 1067 1068 auxiliary_device_delete(adev); 1069 auxiliary_device_uninit(adev); 1070} 1071 1072static int spacemit_ccu_reset_register(struct device *dev, 1073 struct regmap *regmap, 1074 const char *reset_name) 1075{ 1076 struct spacemit_ccu_adev *cadev; 1077 struct auxiliary_device *adev; 1078 int ret; 1079 1080 /* Nothing to do if the CCU does not implement a reset controller */ 1081 if (!reset_name) 1082 return 0; 1083 1084 cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); 1085 if (!cadev) 1086 return -ENOMEM; 1087 1088 cadev->regmap = regmap; 1089 1090 adev = &cadev->adev; 1091 adev->name = reset_name; 1092 adev->dev.parent = dev; 1093 adev->dev.release = spacemit_cadev_release; 1094 adev->dev.of_node = dev->of_node; 1095 ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); 1096 if (ret < 0) 1097 goto err_free_cadev; 1098 adev->id = ret; 1099 1100 ret = auxiliary_device_init(adev); 1101 if (ret) 1102 goto err_free_aux_id; 1103 1104 ret = auxiliary_device_add(adev); 1105 if (ret) { 1106 auxiliary_device_uninit(adev); 1107 return ret; 1108 } 1109 1110 return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); 1111 1112err_free_aux_id: 1113 ida_free(&auxiliary_ids, adev->id); 1114err_free_cadev: 1115 kfree(cadev); 1116 1117 return ret; 1118} 1119 1120static int k1_ccu_probe(struct platform_device *pdev) 1121{ 1122 struct regmap *base_regmap, *lock_regmap = NULL; 1123 const struct spacemit_ccu_data *data; 1124 struct device *dev = &pdev->dev; 1125 int ret; 1126 1127 base_regmap = device_node_to_regmap(dev->of_node); 1128 if (IS_ERR(base_regmap)) 1129 return dev_err_probe(dev, PTR_ERR(base_regmap), 1130 "failed to get regmap\n"); 1131 1132 /* 1133 * The lock status of PLLs locate in MPMU region, while PLLs themselves 1134 * are in APBS region. Reference to MPMU syscon is required to check PLL 1135 * status. 1136 */ 1137 if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) { 1138 struct device_node *mpmu = of_parse_phandle(dev->of_node, 1139 "spacemit,mpmu", 0); 1140 if (!mpmu) 1141 return dev_err_probe(dev, -ENODEV, 1142 "Cannot parse MPMU region\n"); 1143 1144 lock_regmap = device_node_to_regmap(mpmu); 1145 of_node_put(mpmu); 1146 1147 if (IS_ERR(lock_regmap)) 1148 return dev_err_probe(dev, PTR_ERR(lock_regmap), 1149 "failed to get lock regmap\n"); 1150 } 1151 1152 data = of_device_get_match_data(dev); 1153 1154 ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); 1155 if (ret) 1156 return dev_err_probe(dev, ret, "failed to register clocks\n"); 1157 1158 ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); 1159 if (ret) 1160 return dev_err_probe(dev, ret, "failed to register resets\n"); 1161 1162 return 0; 1163} 1164 1165static const struct of_device_id of_k1_ccu_match[] = { 1166 { 1167 .compatible = "spacemit,k1-pll", 1168 .data = &k1_ccu_pll_data, 1169 }, 1170 { 1171 .compatible = "spacemit,k1-syscon-mpmu", 1172 .data = &k1_ccu_mpmu_data, 1173 }, 1174 { 1175 .compatible = "spacemit,k1-syscon-apbc", 1176 .data = &k1_ccu_apbc_data, 1177 }, 1178 { 1179 .compatible = "spacemit,k1-syscon-apmu", 1180 .data = &k1_ccu_apmu_data, 1181 }, 1182 { 1183 .compatible = "spacemit,k1-syscon-rcpu", 1184 .data = &k1_ccu_rcpu_data, 1185 }, 1186 { 1187 .compatible = "spacemit,k1-syscon-rcpu2", 1188 .data = &k1_ccu_rcpu2_data, 1189 }, 1190 { 1191 .compatible = "spacemit,k1-syscon-apbc2", 1192 .data = &k1_ccu_apbc2_data, 1193 }, 1194 { } 1195}; 1196MODULE_DEVICE_TABLE(of, of_k1_ccu_match); 1197 1198static struct platform_driver k1_ccu_driver = { 1199 .driver = { 1200 .name = "spacemit,k1-ccu", 1201 .of_match_table = of_k1_ccu_match, 1202 }, 1203 .probe = k1_ccu_probe, 1204}; 1205module_platform_driver(k1_ccu_driver); 1206 1207MODULE_IMPORT_NS("CLK_SPACEMIT"); 1208MODULE_DESCRIPTION("SpacemiT K1 CCU driver"); 1209MODULE_AUTHOR("Haylen Chu <heylenay@4d2.org>"); 1210MODULE_LICENSE("GPL");
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