clk-cv1800.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
  4 */
  5
  6#ifndef _CLK_SOPHGO_CV1800_H_
  7#define _CLK_SOPHGO_CV1800_H_
  8
  9#include <dt-bindings/clock/sophgo,cv1800.h>
 10
 11#define CV1800_CLK_MAX			(CLK_XTAL_AP + 1)
 12#define CV1810_CLK_MAX			(CLK_DISP_SRC_VIP + 1)
 13
 14#define REG_PLL_G2_CTRL			0x800
 15#define REG_PLL_G2_STATUS		0x804
 16#define REG_MIPIMPLL_CSR		0x808
 17#define REG_A0PLL_CSR			0x80C
 18#define REG_DISPPLL_CSR			0x810
 19#define REG_CAM0PLL_CSR			0x814
 20#define REG_CAM1PLL_CSR			0x818
 21#define REG_PLL_G2_SSC_SYN_CTRL		0x840
 22#define REG_A0PLL_SSC_SYN_CTRL		0x850
 23#define REG_A0PLL_SSC_SYN_SET		0x854
 24#define REG_A0PLL_SSC_SYN_SPAN		0x858
 25#define REG_A0PLL_SSC_SYN_STEP		0x85C
 26#define REG_DISPPLL_SSC_SYN_CTRL	0x860
 27#define REG_DISPPLL_SSC_SYN_SET		0x864
 28#define REG_DISPPLL_SSC_SYN_SPAN	0x868
 29#define REG_DISPPLL_SSC_SYN_STEP	0x86C
 30#define REG_CAM0PLL_SSC_SYN_CTRL	0x870
 31#define REG_CAM0PLL_SSC_SYN_SET		0x874
 32#define REG_CAM0PLL_SSC_SYN_SPAN	0x878
 33#define REG_CAM0PLL_SSC_SYN_STEP	0x87C
 34#define REG_CAM1PLL_SSC_SYN_CTRL	0x880
 35#define REG_CAM1PLL_SSC_SYN_SET		0x884
 36#define REG_CAM1PLL_SSC_SYN_SPAN	0x888
 37#define REG_CAM1PLL_SSC_SYN_STEP	0x88C
 38#define REG_APLL_FRAC_DIV_CTRL		0x890
 39#define REG_APLL_FRAC_DIV_M		0x894
 40#define REG_APLL_FRAC_DIV_N		0x898
 41#define REG_MIPIMPLL_CLK_CSR		0x8A0
 42#define REG_A0PLL_CLK_CSR		0x8A4
 43#define REG_DISPPLL_CLK_CSR		0x8A8
 44#define REG_CAM0PLL_CLK_CSR		0x8AC
 45#define REG_CAM1PLL_CLK_CSR		0x8B0
 46#define REG_CLK_CAM0_SRC_DIV		0x8C0
 47#define REG_CLK_CAM1_SRC_DIV		0x8C4
 48
 49/* top_pll_g6 */
 50#define REG_PLL_G6_CTRL			0x900
 51#define REG_PLL_G6_STATUS		0x904
 52#define REG_MPLL_CSR			0x908
 53#define REG_TPLL_CSR			0x90C
 54#define REG_FPLL_CSR			0x910
 55#define REG_PLL_G6_SSC_SYN_CTRL		0x940
 56#define REG_DPLL_SSC_SYN_CTRL		0x950
 57#define REG_DPLL_SSC_SYN_SET		0x954
 58#define REG_DPLL_SSC_SYN_SPAN		0x958
 59#define REG_DPLL_SSC_SYN_STEP		0x95C
 60#define REG_MPLL_SSC_SYN_CTRL		0x960
 61#define REG_MPLL_SSC_SYN_SET		0x964
 62#define REG_MPLL_SSC_SYN_SPAN		0x968
 63#define REG_MPLL_SSC_SYN_STEP		0x96C
 64#define REG_TPLL_SSC_SYN_CTRL		0x970
 65#define REG_TPLL_SSC_SYN_SET		0x974
 66#define REG_TPLL_SSC_SYN_SPAN		0x978
 67#define REG_TPLL_SSC_SYN_STEP		0x97C
 68
 69/* clkgen */
 70#define REG_CLK_EN_0			0x000
 71#define REG_CLK_EN_1			0x004
 72#define REG_CLK_EN_2			0x008
 73#define REG_CLK_EN_3			0x00C
 74#define REG_CLK_EN_4			0x010
 75#define REG_CLK_SEL_0			0x020
 76#define REG_CLK_BYP_0			0x030
 77#define REG_CLK_BYP_1			0x034
 78
 79#define REG_DIV_CLK_A53_0		0x040
 80#define REG_DIV_CLK_A53_1		0x044
 81#define REG_DIV_CLK_CPU_AXI0		0x048
 82#define REG_DIV_CLK_CPU_GIC		0x050
 83#define REG_DIV_CLK_TPU			0x054
 84#define REG_DIV_CLK_EMMC		0x064
 85#define REG_DIV_CLK_EMMC_100K		0x06C
 86#define REG_DIV_CLK_SD0			0x070
 87#define REG_DIV_CLK_SD0_100K		0x078
 88#define REG_DIV_CLK_SD1			0x07C
 89#define REG_DIV_CLK_SD1_100K		0x084
 90#define REG_DIV_CLK_SPI_NAND		0x088
 91#define REG_DIV_CLK_ETH0_500M		0x08C
 92#define REG_DIV_CLK_ETH1_500M		0x090
 93#define REG_DIV_CLK_GPIO_DB		0x094
 94#define REG_DIV_CLK_SDMA_AUD0		0x098
 95#define REG_DIV_CLK_SDMA_AUD1		0x09C
 96#define REG_DIV_CLK_SDMA_AUD2		0x0A0
 97#define REG_DIV_CLK_SDMA_AUD3		0x0A4
 98#define REG_DIV_CLK_CAM0_200		0x0A8
 99#define REG_DIV_CLK_AXI4		0x0B8
100#define REG_DIV_CLK_AXI6		0x0BC
101#define REG_DIV_CLK_DSI_ESC		0x0C4
102#define REG_DIV_CLK_AXI_VIP		0x0C8
103#define REG_DIV_CLK_SRC_VIP_SYS_0	0x0D0
104#define REG_DIV_CLK_SRC_VIP_SYS_1	0x0D8
105#define REG_DIV_CLK_DISP_SRC_VIP	0x0E0
106#define REG_DIV_CLK_AXI_VIDEO_CODEC	0x0E4
107#define REG_DIV_CLK_VC_SRC0		0x0EC
108#define REG_DIV_CLK_1M			0x0FC
109#define REG_DIV_CLK_SPI			0x100
110#define REG_DIV_CLK_I2C			0x104
111#define REG_DIV_CLK_SRC_VIP_SYS_2	0x110
112#define REG_DIV_CLK_AUDSRC		0x118
113#define REG_DIV_CLK_PWM_SRC_0		0x120
114#define REG_DIV_CLK_AP_DEBUG		0x128
115#define REG_DIV_CLK_RTCSYS_SRC_0	0x12C
116#define REG_DIV_CLK_C906_0_0		0x130
117#define REG_DIV_CLK_C906_0_1		0x134
118#define REG_DIV_CLK_C906_1_0		0x138
119#define REG_DIV_CLK_C906_1_1		0x13C
120#define REG_DIV_CLK_SRC_VIP_SYS_3	0x140
121#define REG_DIV_CLK_SRC_VIP_SYS_4	0x144
122
123#endif /* _CLK_SOPHGO_CV1800_H_ */