clk-cv1800.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
   4 */
   5
   6#include <linux/module.h>
   7#include <linux/clk-provider.h>
   8#include <linux/platform_device.h>
   9#include <linux/io.h>
  10#include <linux/spinlock.h>
  11
  12#include "clk-cv1800.h"
  13
  14#include "clk-cv18xx-common.h"
  15#include "clk-cv18xx-ip.h"
  16#include "clk-cv18xx-pll.h"
  17
  18struct cv1800_clk_ctrl;
  19
  20struct cv1800_clk_desc {
  21	struct clk_hw_onecell_data	*clks_data;
  22
  23	int (*pre_init)(struct device *dev, void __iomem *base,
  24			struct cv1800_clk_ctrl *ctrl,
  25			const struct cv1800_clk_desc *desc);
  26};
  27
  28struct cv1800_clk_ctrl {
  29	const struct cv1800_clk_desc	*desc;
  30	spinlock_t			lock;
  31};
  32
  33#define CV1800_DIV_FLAG	\
  34	(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)
  35static const struct clk_parent_data osc_parents[] = {
  36	{ .index = 0 },
  37};
  38
  39static const struct cv1800_clk_pll_limit pll_limits[] = {
  40	{
  41		.pre_div	= _CV1800_PLL_LIMIT(1, 127),
  42		.div		= _CV1800_PLL_LIMIT(6, 127),
  43		.post_div	= _CV1800_PLL_LIMIT(1, 127),
  44		.ictrl		= _CV1800_PLL_LIMIT(0, 7),
  45		.mode		= _CV1800_PLL_LIMIT(0, 3),
  46	},
  47	{
  48		.pre_div	= _CV1800_PLL_LIMIT(1, 127),
  49		.div		= _CV1800_PLL_LIMIT(6, 127),
  50		.post_div	= _CV1800_PLL_LIMIT(1, 127),
  51		.ictrl		= _CV1800_PLL_LIMIT(0, 7),
  52		.mode		= _CV1800_PLL_LIMIT(0, 3),
  53	},
  54};
  55
  56static CV1800_INTEGRAL_PLL(clk_fpll, osc_parents,
  57			   REG_FPLL_CSR,
  58			   REG_PLL_G6_CTRL, 8,
  59			   REG_PLL_G6_STATUS, 2,
  60			   pll_limits,
  61			   CLK_IS_CRITICAL);
  62
  63static CV1800_INTEGRAL_PLL(clk_mipimpll, osc_parents,
  64			   REG_MIPIMPLL_CSR,
  65			   REG_PLL_G2_CTRL, 0,
  66			   REG_PLL_G2_STATUS, 0,
  67			   pll_limits,
  68			   CLK_IS_CRITICAL);
  69
  70static const struct clk_parent_data clk_mipimpll_parents[] = {
  71	{ .hw = &clk_mipimpll.common.hw },
  72};
  73static const struct clk_parent_data clk_bypass_mipimpll_parents[] = {
  74	{ .index = 0 },
  75	{ .hw = &clk_mipimpll.common.hw },
  76};
  77static const struct clk_parent_data clk_bypass_fpll_parents[] = {
  78	{ .index = 0 },
  79	{ .hw = &clk_fpll.common.hw },
  80};
  81
  82static struct cv1800_clk_pll_synthesizer clk_mpll_synthesizer = {
  83	.en		= CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 2),
  84	.clk_half	= CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
  85	.ctrl		= REG_MPLL_SSC_SYN_CTRL,
  86	.set		= REG_MPLL_SSC_SYN_SET,
  87};
  88static CV1800_FACTIONAL_PLL(clk_mpll, clk_bypass_mipimpll_parents,
  89			    REG_MPLL_CSR,
  90			    REG_PLL_G6_CTRL, 0,
  91			    REG_PLL_G6_STATUS, 0,
  92			    pll_limits,
  93			    &clk_mpll_synthesizer,
  94			    CLK_IS_CRITICAL);
  95
  96static struct cv1800_clk_pll_synthesizer clk_tpll_synthesizer = {
  97	.en		= CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 3),
  98	.clk_half	= CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
  99	.ctrl		= REG_TPLL_SSC_SYN_CTRL,
 100	.set		= REG_TPLL_SSC_SYN_SET,
 101};
 102static CV1800_FACTIONAL_PLL(clk_tpll, clk_bypass_mipimpll_parents,
 103			    REG_TPLL_CSR,
 104			    REG_PLL_G6_CTRL, 4,
 105			    REG_PLL_G6_STATUS, 1,
 106			    pll_limits,
 107			    &clk_tpll_synthesizer,
 108			    CLK_IS_CRITICAL);
 109
 110static struct cv1800_clk_pll_synthesizer clk_a0pll_synthesizer = {
 111	.en		= CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 2),
 112	.clk_half	= CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
 113	.ctrl		= REG_A0PLL_SSC_SYN_CTRL,
 114	.set		= REG_A0PLL_SSC_SYN_SET,
 115};
 116static CV1800_FACTIONAL_PLL(clk_a0pll, clk_bypass_mipimpll_parents,
 117			    REG_A0PLL_CSR,
 118			    REG_PLL_G2_CTRL, 4,
 119			    REG_PLL_G2_STATUS, 1,
 120			    pll_limits,
 121			    &clk_a0pll_synthesizer,
 122			    CLK_IS_CRITICAL);
 123
 124static struct cv1800_clk_pll_synthesizer clk_disppll_synthesizer = {
 125	.en		= CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 3),
 126	.clk_half	= CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
 127	.ctrl		= REG_DISPPLL_SSC_SYN_CTRL,
 128	.set		= REG_DISPPLL_SSC_SYN_SET,
 129};
 130static CV1800_FACTIONAL_PLL(clk_disppll, clk_bypass_mipimpll_parents,
 131			    REG_DISPPLL_CSR,
 132			    REG_PLL_G2_CTRL, 8,
 133			    REG_PLL_G2_STATUS, 2,
 134			    pll_limits,
 135			    &clk_disppll_synthesizer,
 136			    CLK_IS_CRITICAL);
 137
 138static struct cv1800_clk_pll_synthesizer clk_cam0pll_synthesizer = {
 139	.en		= CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 4),
 140	.clk_half	= CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
 141	.ctrl		= REG_CAM0PLL_SSC_SYN_CTRL,
 142	.set		= REG_CAM0PLL_SSC_SYN_SET,
 143};
 144static CV1800_FACTIONAL_PLL(clk_cam0pll, clk_bypass_mipimpll_parents,
 145			    REG_CAM0PLL_CSR,
 146			    REG_PLL_G2_CTRL, 12,
 147			    REG_PLL_G2_STATUS, 3,
 148			    pll_limits,
 149			    &clk_cam0pll_synthesizer,
 150			    CLK_IGNORE_UNUSED);
 151
 152static struct cv1800_clk_pll_synthesizer clk_cam1pll_synthesizer = {
 153	.en		= CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 5),
 154	.clk_half	= CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
 155	.ctrl		= REG_CAM1PLL_SSC_SYN_CTRL,
 156	.set		= REG_CAM1PLL_SSC_SYN_SET,
 157};
 158static CV1800_FACTIONAL_PLL(clk_cam1pll, clk_bypass_mipimpll_parents,
 159			    REG_CAM1PLL_CSR,
 160			    REG_PLL_G2_CTRL, 16,
 161			    REG_PLL_G2_STATUS, 4,
 162			    pll_limits,
 163			    &clk_cam1pll_synthesizer,
 164			    CLK_IS_CRITICAL);
 165
 166static const struct clk_parent_data clk_cam0pll_parents[] = {
 167	{ .hw = &clk_cam0pll.common.hw },
 168};
 169
 170/* G2D */
 171static CV1800_FIXED_DIV(clk_cam0pll_d2, clk_cam0pll_parents,
 172			REG_CAM0PLL_CLK_CSR, 1,
 173			2,
 174			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 175static CV1800_FIXED_DIV(clk_cam0pll_d3, clk_cam0pll_parents,
 176			REG_CAM0PLL_CLK_CSR, 2,
 177			3,
 178			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 179static CV1800_FIXED_DIV(clk_mipimpll_d3, clk_mipimpll_parents,
 180			REG_MIPIMPLL_CLK_CSR, 2,
 181			3,
 182			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 183
 184/* TPU */
 185static const struct clk_parent_data clk_tpu_parents[] = {
 186	{ .index = 0 },
 187	{ .hw = &clk_tpll.common.hw },
 188	{ .hw = &clk_a0pll.common.hw },
 189	{ .hw = &clk_mipimpll.common.hw },
 190	{ .hw = &clk_fpll.common.hw },
 191};
 192
 193static CV1800_BYPASS_MUX(clk_tpu, clk_tpu_parents,
 194			 REG_CLK_EN_0, 4,
 195			 REG_DIV_CLK_TPU, 16, 4, 3, CV1800_DIV_FLAG,
 196			 REG_DIV_CLK_TPU, 8, 2,
 197			 REG_CLK_BYP_0, 3,
 198			 0);
 199static CV1800_GATE(clk_tpu_fab, clk_mipimpll_parents,
 200		   REG_CLK_EN_0, 5,
 201		   0);
 202
 203/* FABRIC_AXI6 */
 204static CV1800_BYPASS_DIV(clk_axi6, clk_bypass_fpll_parents,
 205			 REG_CLK_EN_2, 2,
 206			 REG_DIV_CLK_AXI6, 16, 4, 15, CV1800_DIV_FLAG,
 207			 REG_CLK_BYP_0, 20,
 208			 CLK_IS_CRITICAL);
 209
 210static const struct clk_parent_data clk_axi6_bus_parents[] = {
 211	{ .hw = &clk_axi6.div.common.hw },
 212};
 213static const struct clk_parent_data clk_bypass_axi6_bus_parents[] = {
 214	{ .index = 0 },
 215	{ .hw = &clk_axi6.div.common.hw },
 216};
 217
 218/* FABRIC_AXI4 */
 219static const struct clk_parent_data clk_axi4_parents[] = {
 220	{ .index = 0 },
 221	{ .hw = &clk_fpll.common.hw },
 222	{ .hw = &clk_disppll.common.hw },
 223};
 224
 225static CV1800_BYPASS_MUX(clk_axi4, clk_axi4_parents,
 226			 REG_CLK_EN_2, 1,
 227			 REG_DIV_CLK_AXI4, 16, 4, 5, CV1800_DIV_FLAG,
 228			 REG_DIV_CLK_AXI4, 8, 2,
 229			 REG_CLK_BYP_0, 19,
 230			 CLK_IS_CRITICAL);
 231
 232static const struct clk_parent_data clk_axi4_bus_parents[] = {
 233	{ .hw = &clk_axi4.mux.common.hw },
 234};
 235
 236/* XTAL_MISC */
 237static CV1800_GATE(clk_xtal_misc, osc_parents,
 238		   REG_CLK_EN_0, 14,
 239		   CLK_IS_CRITICAL);
 240
 241static const struct clk_parent_data clk_timer_parents[] = {
 242	{ .hw = &clk_xtal_misc.common.hw },
 243};
 244
 245/* TOP */
 246static const struct clk_parent_data clk_cam0_200_parents[] = {
 247	{ .index = 0 },
 248	{ .index = 0 },
 249	{ .hw = &clk_disppll.common.hw },
 250};
 251
 252static CV1800_BYPASS_MUX(clk_cam0_200, clk_cam0_200_parents,
 253			 REG_CLK_EN_1, 13,
 254			 REG_DIV_CLK_CAM0_200, 16, 4, 1, CV1800_DIV_FLAG,
 255			 REG_DIV_CLK_CAM0_200, 8, 2,
 256			 REG_CLK_BYP_0, 16,
 257			 CLK_IS_CRITICAL);
 258static CV1800_DIV(clk_1m, osc_parents,
 259		  REG_CLK_EN_3, 5,
 260		  REG_DIV_CLK_1M, 16, 6, 25, CV1800_DIV_FLAG,
 261		  CLK_IS_CRITICAL);
 262static CV1800_GATE(clk_pm, clk_axi6_bus_parents,
 263		   REG_CLK_EN_3, 8,
 264		   CLK_IS_CRITICAL);
 265static CV1800_GATE(clk_timer0, clk_timer_parents,
 266		   REG_CLK_EN_3, 9,
 267		   CLK_IS_CRITICAL);
 268static CV1800_GATE(clk_timer1, clk_timer_parents,
 269		   REG_CLK_EN_3, 10,
 270		   CLK_IS_CRITICAL);
 271static CV1800_GATE(clk_timer2, clk_timer_parents,
 272		   REG_CLK_EN_3, 11,
 273		   CLK_IS_CRITICAL);
 274static CV1800_GATE(clk_timer3, clk_timer_parents,
 275		   REG_CLK_EN_3, 12,
 276		   CLK_IS_CRITICAL);
 277static CV1800_GATE(clk_timer4, clk_timer_parents,
 278		   REG_CLK_EN_3, 13,
 279		   CLK_IS_CRITICAL);
 280static CV1800_GATE(clk_timer5, clk_timer_parents,
 281		   REG_CLK_EN_3, 14,
 282		   CLK_IS_CRITICAL);
 283static CV1800_GATE(clk_timer6, clk_timer_parents,
 284		   REG_CLK_EN_3, 15,
 285		   CLK_IS_CRITICAL);
 286static CV1800_GATE(clk_timer7, clk_timer_parents,
 287		   REG_CLK_EN_3, 16,
 288		   CLK_IS_CRITICAL);
 289
 290static const struct clk_parent_data clk_parents_1m[] = {
 291	{ .hw = &clk_1m.common.hw },
 292};
 293static const struct clk_parent_data clk_uart_parents[] = {
 294	{ .hw = &clk_cam0_200.mux.common.hw },
 295};
 296
 297/* AHB ROM */
 298static CV1800_GATE(clk_ahb_rom, clk_axi4_bus_parents,
 299		   REG_CLK_EN_0, 6,
 300		   0);
 301
 302/* RTC */
 303static CV1800_GATE(clk_rtc_25m, osc_parents,
 304		   REG_CLK_EN_0, 8,
 305		   CLK_IS_CRITICAL);
 306static CV1800_BYPASS_DIV(clk_src_rtc_sys_0, clk_bypass_fpll_parents,
 307			 REG_CLK_EN_4, 6,
 308			 REG_DIV_CLK_RTCSYS_SRC_0, 16, 4, 5, CV1800_DIV_FLAG,
 309			 REG_CLK_BYP_1, 5,
 310			 CLK_IS_CRITICAL);
 311
 312/* TEMPSEN */
 313static CV1800_GATE(clk_tempsen, osc_parents,
 314		   REG_CLK_EN_0, 9,
 315		   0);
 316
 317/* SARADC */
 318static CV1800_GATE(clk_saradc, osc_parents,
 319		   REG_CLK_EN_0, 10,
 320		   0);
 321
 322/* EFUSE */
 323static CV1800_GATE(clk_efuse, osc_parents,
 324		   REG_CLK_EN_0, 11,
 325		   0);
 326static CV1800_GATE(clk_apb_efuse, osc_parents,
 327		   REG_CLK_EN_0, 12,
 328		   0);
 329
 330/* WDT */
 331static CV1800_GATE(clk_apb_wdt, osc_parents,
 332		   REG_CLK_EN_1, 7,
 333		   CLK_IS_CRITICAL);
 334
 335/* WGN */
 336static CV1800_GATE(clk_wgn, osc_parents,
 337		   REG_CLK_EN_3, 22,
 338		   0);
 339static CV1800_GATE(clk_wgn0, osc_parents,
 340		   REG_CLK_EN_3, 23,
 341		   0);
 342static CV1800_GATE(clk_wgn1, osc_parents,
 343		   REG_CLK_EN_3, 24,
 344		   0);
 345static CV1800_GATE(clk_wgn2, osc_parents,
 346		   REG_CLK_EN_3, 25,
 347		   0);
 348
 349/* KEYSCAN */
 350static CV1800_GATE(clk_keyscan, osc_parents,
 351		   REG_CLK_EN_3, 26,
 352		   0);
 353
 354/* EMMC */
 355static CV1800_GATE(clk_axi4_emmc, clk_axi4_bus_parents,
 356		   REG_CLK_EN_0, 15,
 357		   0);
 358static CV1800_BYPASS_MUX(clk_emmc, clk_axi4_parents,
 359			 REG_CLK_EN_0, 16,
 360			 REG_DIV_CLK_EMMC, 16, 5, 15, CV1800_DIV_FLAG,
 361			 REG_DIV_CLK_EMMC, 8, 2,
 362			 REG_CLK_BYP_0, 5,
 363			 0);
 364static CV1800_DIV(clk_emmc_100k, clk_parents_1m,
 365		  REG_CLK_EN_0, 17,
 366		  REG_DIV_CLK_EMMC_100K, 16, 8, 10, CV1800_DIV_FLAG,
 367		  0);
 368
 369/* SD */
 370static CV1800_GATE(clk_axi4_sd0, clk_axi4_bus_parents,
 371		   REG_CLK_EN_0, 18,
 372		   0);
 373static CV1800_BYPASS_MUX(clk_sd0, clk_axi4_parents,
 374			 REG_CLK_EN_0, 19,
 375			 REG_DIV_CLK_SD0, 16, 5, 15, CV1800_DIV_FLAG,
 376			 REG_DIV_CLK_SD0, 8, 2,
 377			 REG_CLK_BYP_0, 6,
 378			 0);
 379static CV1800_DIV(clk_sd0_100k, clk_parents_1m,
 380		  REG_CLK_EN_0, 20,
 381		  REG_DIV_CLK_SD0_100K, 16, 8, 10, CV1800_DIV_FLAG,
 382		  0);
 383static CV1800_GATE(clk_axi4_sd1, clk_axi4_bus_parents,
 384		   REG_CLK_EN_0, 21,
 385		   0);
 386static CV1800_BYPASS_MUX(clk_sd1, clk_axi4_parents,
 387			 REG_CLK_EN_0, 22,
 388			 REG_DIV_CLK_SD1, 16, 5, 15, CV1800_DIV_FLAG,
 389			 REG_DIV_CLK_SD1, 8, 2,
 390			 REG_CLK_BYP_0, 7,
 391			 0);
 392static CV1800_DIV(clk_sd1_100k, clk_parents_1m,
 393		  REG_CLK_EN_0, 23,
 394		  REG_DIV_CLK_SD1_100K, 16, 8, 10, CV1800_DIV_FLAG,
 395		  0);
 396
 397/* SPI NAND */
 398static CV1800_BYPASS_MUX(clk_spi_nand, clk_axi4_parents,
 399			 REG_CLK_EN_0, 24,
 400			 REG_DIV_CLK_SPI_NAND, 16, 5, 8, CV1800_DIV_FLAG,
 401			 REG_DIV_CLK_SPI_NAND, 8, 2,
 402			 REG_CLK_BYP_0, 8,
 403			 0);
 404
 405/* GPIO */
 406static CV1800_DIV(clk_gpio_db, clk_parents_1m,
 407		  REG_CLK_EN_0, 31,
 408		  REG_DIV_CLK_GPIO_DB, 16, 16, 10, CV1800_DIV_FLAG,
 409		  CLK_IS_CRITICAL);
 410static CV1800_GATE(clk_apb_gpio, clk_axi6_bus_parents,
 411		   REG_CLK_EN_0, 29,
 412		   CLK_IS_CRITICAL);
 413static CV1800_GATE(clk_apb_gpio_intr, clk_axi6_bus_parents,
 414		   REG_CLK_EN_0, 30,
 415		   CLK_IS_CRITICAL);
 416
 417/* ETH */
 418static CV1800_BYPASS_DIV(clk_eth0_500m, clk_bypass_fpll_parents,
 419			 REG_CLK_EN_0, 25,
 420			 REG_DIV_CLK_GPIO_DB, 16, 4, 3, CV1800_DIV_FLAG,
 421			 REG_CLK_BYP_0, 9,
 422			 0);
 423static CV1800_GATE(clk_axi4_eth0, clk_axi4_bus_parents,
 424		   REG_CLK_EN_0, 26,
 425		   0);
 426static CV1800_BYPASS_DIV(clk_eth1_500m, clk_bypass_fpll_parents,
 427			 REG_CLK_EN_0, 27,
 428			 REG_DIV_CLK_GPIO_DB, 16, 4, 3, CV1800_DIV_FLAG,
 429			 REG_CLK_BYP_0, 10,
 430			 0);
 431static CV1800_GATE(clk_axi4_eth1, clk_axi4_bus_parents,
 432		   REG_CLK_EN_0, 28,
 433		   0);
 434
 435/* SF */
 436static CV1800_GATE(clk_ahb_sf, clk_axi4_bus_parents,
 437		   REG_CLK_EN_1, 0,
 438		   0);
 439static CV1800_GATE(clk_ahb_sf1, clk_axi4_bus_parents,
 440		   REG_CLK_EN_3, 27,
 441		   0);
 442
 443/* AUDSRC */
 444static CV1800_ACLK(clk_a24m, clk_mipimpll_parents,
 445		   REG_APLL_FRAC_DIV_CTRL, 0,
 446		   REG_APLL_FRAC_DIV_CTRL, 3,
 447		   REG_APLL_FRAC_DIV_CTRL, 1,
 448		   REG_APLL_FRAC_DIV_CTRL, 2,
 449		   REG_APLL_FRAC_DIV_M, 0, 22, CV1800_DIV_FLAG,
 450		   REG_APLL_FRAC_DIV_N, 0, 22, CV1800_DIV_FLAG,
 451		   24576000,
 452		   0);
 453
 454static const struct clk_parent_data clk_aud_parents[] = {
 455	{ .index = 0 },
 456	{ .hw = &clk_a0pll.common.hw },
 457	{ .hw = &clk_a24m.common.hw },
 458};
 459
 460static CV1800_BYPASS_MUX(clk_audsrc, clk_aud_parents,
 461			 REG_CLK_EN_4, 1,
 462			 REG_DIV_CLK_AUDSRC, 16, 8, 18, CV1800_DIV_FLAG,
 463			 REG_DIV_CLK_AUDSRC, 8, 2,
 464			 REG_CLK_BYP_1, 2,
 465			 0);
 466static CV1800_GATE(clk_apb_audsrc, clk_axi4_bus_parents,
 467		   REG_CLK_EN_4, 2,
 468		   0);
 469
 470/* SDMA */
 471static CV1800_GATE(clk_sdma_axi, clk_axi4_bus_parents,
 472		   REG_CLK_EN_1, 1,
 473		   0);
 474static CV1800_BYPASS_MUX(clk_sdma_aud0, clk_aud_parents,
 475			 REG_CLK_EN_1, 2,
 476			 REG_DIV_CLK_SDMA_AUD0, 16, 8, 18, CV1800_DIV_FLAG,
 477			 REG_DIV_CLK_SDMA_AUD0, 8, 2,
 478			 REG_CLK_BYP_0, 11,
 479			 0);
 480static CV1800_BYPASS_MUX(clk_sdma_aud1, clk_aud_parents,
 481			 REG_CLK_EN_1, 3,
 482			 REG_DIV_CLK_SDMA_AUD1, 16, 8, 18, CV1800_DIV_FLAG,
 483			 REG_DIV_CLK_SDMA_AUD1, 8, 2,
 484			 REG_CLK_BYP_0, 12,
 485			 0);
 486static CV1800_BYPASS_MUX(clk_sdma_aud2, clk_aud_parents,
 487			 REG_CLK_EN_1, 3,
 488			 REG_DIV_CLK_SDMA_AUD2, 16, 8, 18, CV1800_DIV_FLAG,
 489			 REG_DIV_CLK_SDMA_AUD2, 8, 2,
 490			 REG_CLK_BYP_0, 13,
 491			 0);
 492static CV1800_BYPASS_MUX(clk_sdma_aud3, clk_aud_parents,
 493			 REG_CLK_EN_1, 3,
 494			 REG_DIV_CLK_SDMA_AUD3, 16, 8, 18, CV1800_DIV_FLAG,
 495			 REG_DIV_CLK_SDMA_AUD3, 8, 2,
 496			 REG_CLK_BYP_0, 14,
 497			 0);
 498
 499/* SPI */
 500static CV1800_GATE(clk_apb_spi0, clk_axi4_bus_parents,
 501		   REG_CLK_EN_1, 9,
 502		   0);
 503static CV1800_GATE(clk_apb_spi1, clk_axi4_bus_parents,
 504		   REG_CLK_EN_1, 10,
 505		   0);
 506static CV1800_GATE(clk_apb_spi2, clk_axi4_bus_parents,
 507		   REG_CLK_EN_1, 11,
 508		   0);
 509static CV1800_GATE(clk_apb_spi3, clk_axi4_bus_parents,
 510		   REG_CLK_EN_1, 12,
 511		   0);
 512static CV1800_BYPASS_DIV(clk_spi, clk_bypass_fpll_parents,
 513			 REG_CLK_EN_3, 6,
 514			 REG_DIV_CLK_SPI, 16, 6, 8, CV1800_DIV_FLAG,
 515			 REG_CLK_BYP_0, 30,
 516			 0);
 517
 518/* UART */
 519static CV1800_GATE(clk_uart0, clk_uart_parents,
 520		   REG_CLK_EN_1, 14,
 521		   CLK_IS_CRITICAL);
 522static CV1800_GATE(clk_apb_uart0, clk_axi4_bus_parents,
 523		   REG_CLK_EN_1, 15,
 524		   CLK_IS_CRITICAL);
 525static CV1800_GATE(clk_uart1, clk_uart_parents,
 526		   REG_CLK_EN_1, 16,
 527		   0);
 528static CV1800_GATE(clk_apb_uart1, clk_axi4_bus_parents,
 529		   REG_CLK_EN_1, 17,
 530		   0);
 531static CV1800_GATE(clk_uart2, clk_uart_parents,
 532		   REG_CLK_EN_1, 18,
 533		   0);
 534static CV1800_GATE(clk_apb_uart2, clk_axi4_bus_parents,
 535		   REG_CLK_EN_1, 19,
 536		   0);
 537static CV1800_GATE(clk_uart3, clk_uart_parents,
 538		   REG_CLK_EN_1, 20,
 539		   0);
 540static CV1800_GATE(clk_apb_uart3, clk_axi4_bus_parents,
 541		   REG_CLK_EN_1, 21,
 542		   0);
 543static CV1800_GATE(clk_uart4, clk_uart_parents,
 544		   REG_CLK_EN_1, 22,
 545		   0);
 546static CV1800_GATE(clk_apb_uart4, clk_axi4_bus_parents,
 547		   REG_CLK_EN_1, 23,
 548		   0);
 549
 550/* I2S */
 551static CV1800_GATE(clk_apb_i2s0, clk_axi4_bus_parents,
 552		   REG_CLK_EN_1, 24,
 553		   0);
 554static CV1800_GATE(clk_apb_i2s1, clk_axi4_bus_parents,
 555		   REG_CLK_EN_1, 25,
 556		   0);
 557static CV1800_GATE(clk_apb_i2s2, clk_axi4_bus_parents,
 558		   REG_CLK_EN_1, 26,
 559		   0);
 560static CV1800_GATE(clk_apb_i2s3, clk_axi4_bus_parents,
 561		   REG_CLK_EN_1, 27,
 562		   0);
 563
 564/* DEBUG */
 565static CV1800_GATE(clk_debug, osc_parents,
 566		   REG_CLK_EN_0, 13,
 567		   CLK_IS_CRITICAL);
 568static CV1800_BYPASS_DIV(clk_ap_debug, clk_bypass_fpll_parents,
 569			 REG_CLK_EN_4, 5,
 570			 REG_DIV_CLK_AP_DEBUG, 16, 4, 5, CV1800_DIV_FLAG,
 571			 REG_CLK_BYP_1, 4,
 572			 CLK_IS_CRITICAL);
 573
 574/* DDR */
 575static CV1800_GATE(clk_ddr_axi_reg, clk_axi6_bus_parents,
 576		   REG_CLK_EN_0, 7,
 577		   CLK_IS_CRITICAL);
 578
 579/* I2C */
 580static CV1800_GATE(clk_apb_i2c, clk_axi4_bus_parents,
 581		   REG_CLK_EN_1, 6,
 582		   0);
 583static CV1800_BYPASS_DIV(clk_i2c, clk_bypass_axi6_bus_parents,
 584			 REG_CLK_EN_3, 7,
 585			 REG_DIV_CLK_I2C, 16, 4, 1, CV1800_DIV_FLAG,
 586			 REG_CLK_BYP_0, 31,
 587			 0);
 588static CV1800_GATE(clk_apb_i2c0, clk_axi4_bus_parents,
 589		   REG_CLK_EN_3, 17,
 590		   0);
 591static CV1800_GATE(clk_apb_i2c1, clk_axi4_bus_parents,
 592		   REG_CLK_EN_3, 18,
 593		   0);
 594static CV1800_GATE(clk_apb_i2c2, clk_axi4_bus_parents,
 595		   REG_CLK_EN_3, 19,
 596		   0);
 597static CV1800_GATE(clk_apb_i2c3, clk_axi4_bus_parents,
 598		   REG_CLK_EN_3, 20,
 599		   0);
 600static CV1800_GATE(clk_apb_i2c4, clk_axi4_bus_parents,
 601		   REG_CLK_EN_3, 21,
 602		   0);
 603
 604/* USB */
 605static CV1800_GATE(clk_axi4_usb, clk_axi4_bus_parents,
 606		   REG_CLK_EN_1, 28,
 607		   0);
 608static CV1800_GATE(clk_apb_usb, clk_axi4_bus_parents,
 609		   REG_CLK_EN_1, 29,
 610		   0);
 611static CV1800_BYPASS_FIXED_DIV(clk_usb_125m, clk_bypass_fpll_parents,
 612			       REG_CLK_EN_1, 30,
 613			       12,
 614			       REG_CLK_BYP_0, 17,
 615			       CLK_SET_RATE_PARENT);
 616static CV1800_FIXED_DIV(clk_usb_33k, clk_parents_1m,
 617			REG_CLK_EN_1, 31,
 618			3,
 619			0);
 620static CV1800_BYPASS_FIXED_DIV(clk_usb_12m, clk_bypass_fpll_parents,
 621			       REG_CLK_EN_2, 0,
 622			       125,
 623			       REG_CLK_BYP_0, 18,
 624			       CLK_SET_RATE_PARENT);
 625
 626/* VIP SYS */
 627static const struct clk_parent_data clk_vip_sys_parents[] = {
 628	{ .index = 0 },
 629	{ .hw = &clk_mipimpll.common.hw },
 630	{ .hw = &clk_cam0pll.common.hw },
 631	{ .hw = &clk_disppll.common.hw },
 632	{ .hw = &clk_fpll.common.hw },
 633};
 634static const struct clk_parent_data clk_disp_vip_parents[] = {
 635	{ .index = 0 },
 636	{ .hw = &clk_disppll.common.hw },
 637};
 638
 639static CV1800_BYPASS_DIV(clk_dsi_esc, clk_bypass_axi6_bus_parents,
 640			 REG_CLK_EN_2, 3,
 641			 REG_DIV_CLK_DSI_ESC, 16, 4, 5, CV1800_DIV_FLAG,
 642			 REG_CLK_BYP_0, 21,
 643			 0);
 644static CV1800_BYPASS_MUX(clk_axi_vip, clk_vip_sys_parents,
 645			 REG_CLK_EN_2, 4,
 646			 REG_DIV_CLK_AXI_VIP, 16, 4, 3, CV1800_DIV_FLAG,
 647			 REG_DIV_CLK_AXI_VIP, 8, 2,
 648			 REG_CLK_BYP_0, 22,
 649			 0);
 650
 651static const struct clk_parent_data clk_axi_vip_bus_parents[] = {
 652	{ .hw = &clk_axi_vip.mux.common.hw },
 653};
 654
 655static CV1800_BYPASS_MUX(clk_src_vip_sys_0, clk_vip_sys_parents,
 656			 REG_CLK_EN_2, 5,
 657			 REG_DIV_CLK_SRC_VIP_SYS_0, 16, 4, 6, CV1800_DIV_FLAG,
 658			 REG_DIV_CLK_SRC_VIP_SYS_0, 8, 2,
 659			 REG_CLK_BYP_0, 23,
 660			 0);
 661static CV1800_BYPASS_MUX(clk_src_vip_sys_1, clk_vip_sys_parents,
 662			 REG_CLK_EN_2, 6,
 663			 REG_DIV_CLK_SRC_VIP_SYS_1, 16, 4, 6, CV1800_DIV_FLAG,
 664			 REG_DIV_CLK_SRC_VIP_SYS_1, 8, 2,
 665			 REG_CLK_BYP_0, 24,
 666			 0);
 667static CV1800_BYPASS_DIV(clk_disp_src_vip, clk_disp_vip_parents,
 668			 REG_CLK_EN_2, 7,
 669			 REG_DIV_CLK_DISP_SRC_VIP, 16, 4, 8, CV1800_DIV_FLAG,
 670			 REG_CLK_BYP_0, 25,
 671			 0);
 672static CV1800_BYPASS_MUX(clk_src_vip_sys_2, clk_vip_sys_parents,
 673			 REG_CLK_EN_3, 29,
 674			 REG_DIV_CLK_SRC_VIP_SYS_2, 16, 4, 2, CV1800_DIV_FLAG,
 675			 REG_DIV_CLK_SRC_VIP_SYS_2, 8, 2,
 676			 REG_CLK_BYP_1, 1,
 677			 0);
 678static CV1800_GATE(clk_csi_mac0_vip, clk_axi_vip_bus_parents,
 679		   REG_CLK_EN_2, 18,
 680		   0);
 681static CV1800_GATE(clk_csi_mac1_vip, clk_axi_vip_bus_parents,
 682		   REG_CLK_EN_2, 19,
 683		   0);
 684static CV1800_GATE(clk_isp_top_vip, clk_axi_vip_bus_parents,
 685		   REG_CLK_EN_2, 20,
 686		   0);
 687static CV1800_GATE(clk_img_d_vip, clk_axi_vip_bus_parents,
 688		   REG_CLK_EN_2, 21,
 689		   0);
 690static CV1800_GATE(clk_img_v_vip, clk_axi_vip_bus_parents,
 691		   REG_CLK_EN_2, 22,
 692		   0);
 693static CV1800_GATE(clk_sc_top_vip, clk_axi_vip_bus_parents,
 694		   REG_CLK_EN_2, 23,
 695		   0);
 696static CV1800_GATE(clk_sc_d_vip, clk_axi_vip_bus_parents,
 697		   REG_CLK_EN_2, 24,
 698		   0);
 699static CV1800_GATE(clk_sc_v1_vip, clk_axi_vip_bus_parents,
 700		   REG_CLK_EN_2, 25,
 701		   0);
 702static CV1800_GATE(clk_sc_v2_vip, clk_axi_vip_bus_parents,
 703		   REG_CLK_EN_2, 26,
 704		   0);
 705static CV1800_GATE(clk_sc_v3_vip, clk_axi_vip_bus_parents,
 706		   REG_CLK_EN_2, 27,
 707		   0);
 708static CV1800_GATE(clk_dwa_vip, clk_axi_vip_bus_parents,
 709		   REG_CLK_EN_2, 28,
 710		   0);
 711static CV1800_GATE(clk_bt_vip, clk_axi_vip_bus_parents,
 712		   REG_CLK_EN_2, 29,
 713		   0);
 714static CV1800_GATE(clk_disp_vip, clk_axi_vip_bus_parents,
 715		   REG_CLK_EN_2, 30,
 716		   0);
 717static CV1800_GATE(clk_dsi_mac_vip, clk_axi_vip_bus_parents,
 718		   REG_CLK_EN_2, 31,
 719		   0);
 720static CV1800_GATE(clk_lvds0_vip, clk_axi_vip_bus_parents,
 721		   REG_CLK_EN_3, 0,
 722		   0);
 723static CV1800_GATE(clk_lvds1_vip, clk_axi_vip_bus_parents,
 724		   REG_CLK_EN_3, 1,
 725		   0);
 726static CV1800_GATE(clk_csi0_rx_vip, clk_axi_vip_bus_parents,
 727		   REG_CLK_EN_3, 2,
 728		   0);
 729static CV1800_GATE(clk_csi1_rx_vip, clk_axi_vip_bus_parents,
 730		   REG_CLK_EN_3, 3,
 731		   0);
 732static CV1800_GATE(clk_pad_vi_vip, clk_axi_vip_bus_parents,
 733		   REG_CLK_EN_3, 4,
 734		   0);
 735static CV1800_GATE(clk_pad_vi1_vip, clk_axi_vip_bus_parents,
 736		   REG_CLK_EN_3, 30,
 737		   0);
 738static CV1800_GATE(clk_cfg_reg_vip, clk_axi6_bus_parents,
 739		   REG_CLK_EN_3, 31,
 740		   0);
 741static CV1800_GATE(clk_pad_vi2_vip, clk_axi_vip_bus_parents,
 742		   REG_CLK_EN_4, 7,
 743		   0);
 744static CV1800_GATE(clk_csi_be_vip, clk_axi_vip_bus_parents,
 745		   REG_CLK_EN_4, 8,
 746		   0);
 747static CV1800_GATE(clk_vip_ip0, clk_axi_vip_bus_parents,
 748		   REG_CLK_EN_4, 9,
 749		   0);
 750static CV1800_GATE(clk_vip_ip1, clk_axi_vip_bus_parents,
 751		   REG_CLK_EN_4, 10,
 752		   0);
 753static CV1800_GATE(clk_vip_ip2, clk_axi_vip_bus_parents,
 754		   REG_CLK_EN_4, 11,
 755		   0);
 756static CV1800_GATE(clk_vip_ip3, clk_axi_vip_bus_parents,
 757		   REG_CLK_EN_4, 12,
 758		   0);
 759static CV1800_BYPASS_MUX(clk_src_vip_sys_3, clk_vip_sys_parents,
 760			 REG_CLK_EN_4, 15,
 761			 REG_DIV_CLK_SRC_VIP_SYS_3, 16, 4, 2, CV1800_DIV_FLAG,
 762			 REG_DIV_CLK_SRC_VIP_SYS_3, 8, 2,
 763			 REG_CLK_BYP_1, 8,
 764			 0);
 765static CV1800_BYPASS_MUX(clk_src_vip_sys_4, clk_vip_sys_parents,
 766			 REG_CLK_EN_4, 16,
 767			 REG_DIV_CLK_SRC_VIP_SYS_4, 16, 4, 3, CV1800_DIV_FLAG,
 768			 REG_DIV_CLK_SRC_VIP_SYS_4, 8, 2,
 769			 REG_CLK_BYP_1, 9,
 770			 0);
 771static CV1800_GATE(clk_ive_vip, clk_axi_vip_bus_parents,
 772		   REG_CLK_EN_4, 17,
 773		   0);
 774static CV1800_GATE(clk_raw_vip, clk_axi_vip_bus_parents,
 775		   REG_CLK_EN_4, 18,
 776		   0);
 777static CV1800_GATE(clk_osdc_vip, clk_axi_vip_bus_parents,
 778		   REG_CLK_EN_4, 19,
 779		   0);
 780static CV1800_GATE(clk_csi_mac2_vip, clk_axi_vip_bus_parents,
 781		   REG_CLK_EN_4, 20,
 782		   0);
 783static CV1800_GATE(clk_cam0_vip, clk_axi_vip_bus_parents,
 784		   REG_CLK_EN_4, 21,
 785		   0);
 786
 787/* CAM OUT */
 788static const struct clk_parent_data clk_cam_parents[] = {
 789	{ .hw = &clk_cam0pll.common.hw },
 790	{ .hw = &clk_cam0pll_d2.common.hw },
 791	{ .hw = &clk_cam0pll_d3.common.hw },
 792	{ .hw = &clk_mipimpll_d3.common.hw },
 793};
 794
 795static CV1800_MUX(clk_cam0, clk_cam_parents,
 796		  REG_CLK_EN_2, 16,
 797		  REG_CLK_CAM0_SRC_DIV, 16, 6, 0, CV1800_DIV_FLAG,
 798		  REG_CLK_CAM0_SRC_DIV, 8, 2,
 799		  CLK_IGNORE_UNUSED);
 800static CV1800_MUX(clk_cam1, clk_cam_parents,
 801		  REG_CLK_EN_2, 17,
 802		  REG_CLK_CAM1_SRC_DIV, 16, 6, 0, CV1800_DIV_FLAG,
 803		  REG_CLK_CAM1_SRC_DIV, 8, 2,
 804		  CLK_IGNORE_UNUSED);
 805
 806/* VIDEO SUBSYS */
 807static const struct clk_parent_data clk_axi_video_codec_parents[] = {
 808	{ .index = 0 },
 809	{ .hw = &clk_a0pll.common.hw },
 810	{ .hw = &clk_mipimpll.common.hw },
 811	{ .hw = &clk_cam1pll.common.hw },
 812	{ .hw = &clk_fpll.common.hw },
 813};
 814static const struct clk_parent_data clk_vc_src0_parents[] = {
 815	{ .index = 0 },
 816	{ .hw = &clk_disppll.common.hw },
 817	{ .hw = &clk_mipimpll.common.hw },
 818	{ .hw = &clk_cam1pll.common.hw },
 819	{ .hw = &clk_fpll.common.hw },
 820};
 821static const struct clk_parent_data clk_vc_src1_parents[] = {
 822	{ .index = 0 },
 823	{ .hw = &clk_cam1pll.common.hw },
 824};
 825
 826static CV1800_BYPASS_MUX(clk_axi_video_codec, clk_axi_video_codec_parents,
 827			 REG_CLK_EN_2, 8,
 828			 REG_DIV_CLK_AXI_VIDEO_CODEC, 16, 4, 2, CV1800_DIV_FLAG,
 829			 REG_DIV_CLK_AXI_VIDEO_CODEC, 8, 2,
 830			 REG_CLK_BYP_0, 26,
 831			 0);
 832
 833static const struct clk_parent_data clk_axi_video_codec_bus_parents[] = {
 834	{ .hw = &clk_axi_video_codec.mux.common.hw },
 835};
 836
 837static CV1800_BYPASS_MUX(clk_vc_src0, clk_vc_src0_parents,
 838			 REG_CLK_EN_2, 9,
 839			 REG_DIV_CLK_VC_SRC0, 16, 4, 2, CV1800_DIV_FLAG,
 840			 REG_DIV_CLK_VC_SRC0, 8, 2,
 841			 REG_CLK_BYP_0, 27,
 842			 0);
 843
 844static CV1800_GATE(clk_h264c, clk_axi_video_codec_bus_parents,
 845		   REG_CLK_EN_2, 10,
 846		   0);
 847static CV1800_GATE(clk_h265c, clk_axi_video_codec_bus_parents,
 848		   REG_CLK_EN_2, 11,
 849		   0);
 850static CV1800_GATE(clk_jpeg, clk_axi_video_codec_bus_parents,
 851		   REG_CLK_EN_2, 12,
 852		   CLK_IGNORE_UNUSED);
 853static CV1800_GATE(clk_apb_jpeg, clk_axi6_bus_parents,
 854		   REG_CLK_EN_2, 13,
 855		   CLK_IGNORE_UNUSED);
 856static CV1800_GATE(clk_apb_h264c, clk_axi6_bus_parents,
 857		   REG_CLK_EN_2, 14,
 858		   0);
 859static CV1800_GATE(clk_apb_h265c, clk_axi6_bus_parents,
 860		   REG_CLK_EN_2, 15,
 861		   0);
 862static CV1800_BYPASS_FIXED_DIV(clk_vc_src1, clk_vc_src1_parents,
 863			       REG_CLK_EN_3, 28,
 864			       2,
 865			       REG_CLK_BYP_1, 0,
 866			       CLK_SET_RATE_PARENT);
 867static CV1800_BYPASS_FIXED_DIV(clk_vc_src2, clk_bypass_fpll_parents,
 868			       REG_CLK_EN_4, 3,
 869			       3,
 870			       REG_CLK_BYP_1, 3,
 871			       CLK_SET_RATE_PARENT);
 872
 873/* VC SYS */
 874static CV1800_GATE(clk_cfg_reg_vc, clk_axi6_bus_parents,
 875		   REG_CLK_EN_4, 0,
 876		   CLK_IGNORE_UNUSED);
 877
 878/* PWM */
 879static CV1800_BYPASS_MUX(clk_pwm_src, clk_axi4_parents,
 880			 REG_CLK_EN_4, 4,
 881			 REG_DIV_CLK_PWM_SRC_0, 16, 6, 10, CV1800_DIV_FLAG,
 882			 REG_DIV_CLK_PWM_SRC_0, 8, 2,
 883			 REG_CLK_BYP_0, 15,
 884			 CLK_IS_CRITICAL);
 885
 886static const struct clk_parent_data clk_pwm_parents[] = {
 887	{ .hw = &clk_pwm_src.mux.common.hw },
 888};
 889
 890static CV1800_GATE(clk_pwm, clk_pwm_parents,
 891		   REG_CLK_EN_1, 8,
 892		   CLK_IS_CRITICAL);
 893
 894/* C906 */
 895static const struct clk_parent_data clk_c906_0_parents[] = {
 896	{ .index = 0 },
 897	{ .hw = &clk_tpll.common.hw },
 898	{ .hw = &clk_a0pll.common.hw },
 899	{ .hw = &clk_mipimpll.common.hw },
 900	{ .hw = &clk_mpll.common.hw },
 901	{ .hw = &clk_fpll.common.hw },
 902};
 903static const struct clk_parent_data clk_c906_1_parents[] = {
 904	{ .index = 0 },
 905	{ .hw = &clk_tpll.common.hw },
 906	{ .hw = &clk_a0pll.common.hw },
 907	{ .hw = &clk_disppll.common.hw },
 908	{ .hw = &clk_mpll.common.hw },
 909	{ .hw = &clk_fpll.common.hw },
 910};
 911
 912static const s8 clk_c906_parent2sel[] = {
 913	-1,	/* osc */
 914	0,	/* mux 0: clk_tpll(c906_0), clk_tpll(c906_1) */
 915	0,	/* mux 0: clk_a0pll(c906_0), clk_a0pll(c906_1) */
 916	0,	/* mux 0: clk_mipimpll(c906_0), clk_disppll(c906_1) */
 917	0,	/* mux 0: clk_mpll(c906_0), clk_mpll(c906_1) */
 918	1	/* mux 1: clk_fpll(c906_0), clk_fpll(c906_1) */
 919};
 920
 921static const u8 clk_c906_sel2parent[2][4] = {
 922	[0] = {
 923		1,
 924		2,
 925		3,
 926		4
 927	},
 928	[1] = {
 929		5,
 930		5,
 931		5,
 932		5
 933	},
 934};
 935
 936static CV1800_MMUX(clk_c906_0, clk_c906_0_parents,
 937		   REG_CLK_EN_4, 13,
 938		   REG_DIV_CLK_C906_0_0, 16, 4, 1, CV1800_DIV_FLAG,
 939		   REG_DIV_CLK_C906_0_1, 16, 4, 2, CV1800_DIV_FLAG,
 940		   REG_DIV_CLK_C906_0_0, 8, 2,
 941		   REG_DIV_CLK_C906_0_1, 8, 2,
 942		   REG_CLK_BYP_1, 6,
 943		   REG_CLK_SEL_0, 23,
 944		   clk_c906_parent2sel,
 945		   clk_c906_sel2parent[0], clk_c906_sel2parent[1],
 946		   CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
 947static CV1800_MMUX(clk_c906_1, clk_c906_1_parents,
 948		   REG_CLK_EN_4, 14,
 949		   REG_DIV_CLK_C906_1_0, 16, 4, 2, CV1800_DIV_FLAG,
 950		   REG_DIV_CLK_C906_1_1, 16, 4, 3, CV1800_DIV_FLAG,
 951		   REG_DIV_CLK_C906_1_0, 8, 2,
 952		   REG_DIV_CLK_C906_1_1, 8, 2,
 953		   REG_CLK_BYP_1, 7,
 954		   REG_CLK_SEL_0, 24,
 955		   clk_c906_parent2sel,
 956		   clk_c906_sel2parent[0], clk_c906_sel2parent[1],
 957		   CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
 958
 959/* A53 */
 960static CV1800_BYPASS_DIV(clk_cpu_axi0, clk_axi4_parents,
 961			 REG_CLK_EN_0, 1,
 962			 REG_DIV_CLK_CPU_AXI0, 16, 4, 3, CV1800_DIV_FLAG,
 963			 REG_CLK_BYP_0, 1,
 964			 CLK_IS_CRITICAL);
 965static CV1800_BYPASS_DIV(clk_cpu_gic, clk_bypass_fpll_parents,
 966			 REG_CLK_EN_0, 2,
 967			 REG_DIV_CLK_CPU_GIC, 16, 4, 5, CV1800_DIV_FLAG,
 968			 REG_CLK_BYP_0, 2,
 969			 CLK_IS_CRITICAL);
 970static CV1800_GATE(clk_xtal_ap, osc_parents,
 971		   REG_CLK_EN_0, 3,
 972		   CLK_IS_CRITICAL);
 973
 974static const struct clk_parent_data clk_a53_parents[] = {
 975	{ .index = 0 },
 976	{ .hw = &clk_tpll.common.hw },
 977	{ .hw = &clk_a0pll.common.hw },
 978	{ .hw = &clk_mipimpll.common.hw },
 979	{ .hw = &clk_mpll.common.hw },
 980	{ .hw = &clk_fpll.common.hw },
 981};
 982
 983static const s8 clk_a53_parent2sel[] = {
 984	-1,	/* osc */
 985	0,	/* mux 0: clk_tpll */
 986	0,	/* mux 0: clk_a0pll */
 987	0,	/* mux 0: clk_mipimpll */
 988	0,	/* mux 0: clk_mpll */
 989	1	/* mux 1: clk_fpll */
 990};
 991
 992static const u8 clk_a53_sel2parent[2][4] = {
 993	[0] = {
 994		1,
 995		2,
 996		3,
 997		4
 998	},
 999	[1] = {
1000		5,
1001		5,
1002		5,
1003		5
1004	},
1005};
1006
1007/*
1008 * Clock for A53 cpu in the CV18XX/SG200X series.
1009 * For CV180X and CV181X series, this clock is not used, but can not
1010 * be set to bypass mode, or the SoC will hang.
1011 */
1012static CV1800_MMUX(clk_a53, clk_a53_parents,
1013		   REG_CLK_EN_0, 0,
1014		   REG_DIV_CLK_A53_0, 16, 4, 1, CV1800_DIV_FLAG,
1015		   REG_DIV_CLK_A53_1, 16, 4, 2, CV1800_DIV_FLAG,
1016		   REG_DIV_CLK_A53_0, 8, 2,
1017		   REG_DIV_CLK_A53_1, 8, 2,
1018		   REG_CLK_BYP_0, 0,
1019		   REG_CLK_SEL_0, 0,
1020		   clk_a53_parent2sel,
1021		   clk_a53_sel2parent[0], clk_a53_sel2parent[1],
1022		   CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
1023
1024static struct clk_hw_onecell_data cv1800_hw_clks = {
1025	.num	= CV1800_CLK_MAX,
1026	.hws	= {
1027		[CLK_MPLL]		= &clk_mpll.common.hw,
1028		[CLK_TPLL]		= &clk_tpll.common.hw,
1029		[CLK_FPLL]		= &clk_fpll.common.hw,
1030		[CLK_MIPIMPLL]		= &clk_mipimpll.common.hw,
1031		[CLK_A0PLL]		= &clk_a0pll.common.hw,
1032		[CLK_DISPPLL]		= &clk_disppll.common.hw,
1033		[CLK_CAM0PLL]		= &clk_cam0pll.common.hw,
1034		[CLK_CAM1PLL]		= &clk_cam1pll.common.hw,
1035
1036		[CLK_MIPIMPLL_D3]	= &clk_mipimpll_d3.common.hw,
1037		[CLK_CAM0PLL_D2]	= &clk_cam0pll_d2.common.hw,
1038		[CLK_CAM0PLL_D3]	= &clk_cam0pll_d3.common.hw,
1039
1040		[CLK_TPU]		= &clk_tpu.mux.common.hw,
1041		[CLK_TPU_FAB]		= &clk_tpu_fab.common.hw,
1042		[CLK_AHB_ROM]		= &clk_ahb_rom.common.hw,
1043		[CLK_DDR_AXI_REG]	= &clk_ddr_axi_reg.common.hw,
1044		[CLK_RTC_25M]		= &clk_rtc_25m.common.hw,
1045		[CLK_SRC_RTC_SYS_0]	= &clk_src_rtc_sys_0.div.common.hw,
1046		[CLK_TEMPSEN]		= &clk_tempsen.common.hw,
1047		[CLK_SARADC]		= &clk_saradc.common.hw,
1048		[CLK_EFUSE]		= &clk_efuse.common.hw,
1049		[CLK_APB_EFUSE]		= &clk_apb_efuse.common.hw,
1050		[CLK_DEBUG]		= &clk_debug.common.hw,
1051		[CLK_AP_DEBUG]		= &clk_ap_debug.div.common.hw,
1052		[CLK_XTAL_MISC]		= &clk_xtal_misc.common.hw,
1053		[CLK_AXI4_EMMC]		= &clk_axi4_emmc.common.hw,
1054		[CLK_EMMC]		= &clk_emmc.mux.common.hw,
1055		[CLK_EMMC_100K]		= &clk_emmc_100k.common.hw,
1056		[CLK_AXI4_SD0]		= &clk_axi4_sd0.common.hw,
1057		[CLK_SD0]		= &clk_sd0.mux.common.hw,
1058		[CLK_SD0_100K]		= &clk_sd0_100k.common.hw,
1059		[CLK_AXI4_SD1]		= &clk_axi4_sd1.common.hw,
1060		[CLK_SD1]		= &clk_sd1.mux.common.hw,
1061		[CLK_SD1_100K]		= &clk_sd1_100k.common.hw,
1062		[CLK_SPI_NAND]		= &clk_spi_nand.mux.common.hw,
1063		[CLK_ETH0_500M]		= &clk_eth0_500m.div.common.hw,
1064		[CLK_AXI4_ETH0]		= &clk_axi4_eth0.common.hw,
1065		[CLK_ETH1_500M]		= &clk_eth1_500m.div.common.hw,
1066		[CLK_AXI4_ETH1]		= &clk_axi4_eth1.common.hw,
1067		[CLK_APB_GPIO]		= &clk_apb_gpio.common.hw,
1068		[CLK_APB_GPIO_INTR]	= &clk_apb_gpio_intr.common.hw,
1069		[CLK_GPIO_DB]		= &clk_gpio_db.common.hw,
1070		[CLK_AHB_SF]		= &clk_ahb_sf.common.hw,
1071		[CLK_AHB_SF1]		= &clk_ahb_sf1.common.hw,
1072		[CLK_A24M]		= &clk_a24m.common.hw,
1073		[CLK_AUDSRC]		= &clk_audsrc.mux.common.hw,
1074		[CLK_APB_AUDSRC]	= &clk_apb_audsrc.common.hw,
1075		[CLK_SDMA_AXI]		= &clk_sdma_axi.common.hw,
1076		[CLK_SDMA_AUD0]		= &clk_sdma_aud0.mux.common.hw,
1077		[CLK_SDMA_AUD1]		= &clk_sdma_aud1.mux.common.hw,
1078		[CLK_SDMA_AUD2]		= &clk_sdma_aud2.mux.common.hw,
1079		[CLK_SDMA_AUD3]		= &clk_sdma_aud3.mux.common.hw,
1080		[CLK_I2C]		= &clk_i2c.div.common.hw,
1081		[CLK_APB_I2C]		= &clk_apb_i2c.common.hw,
1082		[CLK_APB_I2C0]		= &clk_apb_i2c0.common.hw,
1083		[CLK_APB_I2C1]		= &clk_apb_i2c1.common.hw,
1084		[CLK_APB_I2C2]		= &clk_apb_i2c2.common.hw,
1085		[CLK_APB_I2C3]		= &clk_apb_i2c3.common.hw,
1086		[CLK_APB_I2C4]		= &clk_apb_i2c4.common.hw,
1087		[CLK_APB_WDT]		= &clk_apb_wdt.common.hw,
1088		[CLK_PWM_SRC]		= &clk_pwm_src.mux.common.hw,
1089		[CLK_PWM]		= &clk_pwm.common.hw,
1090		[CLK_SPI]		= &clk_spi.div.common.hw,
1091		[CLK_APB_SPI0]		= &clk_apb_spi0.common.hw,
1092		[CLK_APB_SPI1]		= &clk_apb_spi1.common.hw,
1093		[CLK_APB_SPI2]		= &clk_apb_spi2.common.hw,
1094		[CLK_APB_SPI3]		= &clk_apb_spi3.common.hw,
1095		[CLK_1M]		= &clk_1m.common.hw,
1096		[CLK_CAM0_200]		= &clk_cam0_200.mux.common.hw,
1097		[CLK_PM]		= &clk_pm.common.hw,
1098		[CLK_TIMER0]		= &clk_timer0.common.hw,
1099		[CLK_TIMER1]		= &clk_timer1.common.hw,
1100		[CLK_TIMER2]		= &clk_timer2.common.hw,
1101		[CLK_TIMER3]		= &clk_timer3.common.hw,
1102		[CLK_TIMER4]		= &clk_timer4.common.hw,
1103		[CLK_TIMER5]		= &clk_timer5.common.hw,
1104		[CLK_TIMER6]		= &clk_timer6.common.hw,
1105		[CLK_TIMER7]		= &clk_timer7.common.hw,
1106		[CLK_UART0]		= &clk_uart0.common.hw,
1107		[CLK_APB_UART0]		= &clk_apb_uart0.common.hw,
1108		[CLK_UART1]		= &clk_uart1.common.hw,
1109		[CLK_APB_UART1]		= &clk_apb_uart1.common.hw,
1110		[CLK_UART2]		= &clk_uart2.common.hw,
1111		[CLK_APB_UART2]		= &clk_apb_uart2.common.hw,
1112		[CLK_UART3]		= &clk_uart3.common.hw,
1113		[CLK_APB_UART3]		= &clk_apb_uart3.common.hw,
1114		[CLK_UART4]		= &clk_uart4.common.hw,
1115		[CLK_APB_UART4]		= &clk_apb_uart4.common.hw,
1116		[CLK_APB_I2S0]		= &clk_apb_i2s0.common.hw,
1117		[CLK_APB_I2S1]		= &clk_apb_i2s1.common.hw,
1118		[CLK_APB_I2S2]		= &clk_apb_i2s2.common.hw,
1119		[CLK_APB_I2S3]		= &clk_apb_i2s3.common.hw,
1120		[CLK_AXI4_USB]		= &clk_axi4_usb.common.hw,
1121		[CLK_APB_USB]		= &clk_apb_usb.common.hw,
1122		[CLK_USB_125M]		= &clk_usb_125m.div.common.hw,
1123		[CLK_USB_33K]		= &clk_usb_33k.common.hw,
1124		[CLK_USB_12M]		= &clk_usb_12m.div.common.hw,
1125		[CLK_AXI4]		= &clk_axi4.mux.common.hw,
1126		[CLK_AXI6]		= &clk_axi6.div.common.hw,
1127		[CLK_DSI_ESC]		= &clk_dsi_esc.div.common.hw,
1128		[CLK_AXI_VIP]		= &clk_axi_vip.mux.common.hw,
1129		[CLK_SRC_VIP_SYS_0]	= &clk_src_vip_sys_0.mux.common.hw,
1130		[CLK_SRC_VIP_SYS_1]	= &clk_src_vip_sys_1.mux.common.hw,
1131		[CLK_SRC_VIP_SYS_2]	= &clk_src_vip_sys_2.mux.common.hw,
1132		[CLK_SRC_VIP_SYS_3]	= &clk_src_vip_sys_3.mux.common.hw,
1133		[CLK_SRC_VIP_SYS_4]	= &clk_src_vip_sys_4.mux.common.hw,
1134		[CLK_CSI_BE_VIP]	= &clk_csi_be_vip.common.hw,
1135		[CLK_CSI_MAC0_VIP]	= &clk_csi_mac0_vip.common.hw,
1136		[CLK_CSI_MAC1_VIP]	= &clk_csi_mac1_vip.common.hw,
1137		[CLK_CSI_MAC2_VIP]	= &clk_csi_mac2_vip.common.hw,
1138		[CLK_CSI0_RX_VIP]	= &clk_csi0_rx_vip.common.hw,
1139		[CLK_CSI1_RX_VIP]	= &clk_csi1_rx_vip.common.hw,
1140		[CLK_ISP_TOP_VIP]	= &clk_isp_top_vip.common.hw,
1141		[CLK_IMG_D_VIP]		= &clk_img_d_vip.common.hw,
1142		[CLK_IMG_V_VIP]		= &clk_img_v_vip.common.hw,
1143		[CLK_SC_TOP_VIP]	= &clk_sc_top_vip.common.hw,
1144		[CLK_SC_D_VIP]		= &clk_sc_d_vip.common.hw,
1145		[CLK_SC_V1_VIP]		= &clk_sc_v1_vip.common.hw,
1146		[CLK_SC_V2_VIP]		= &clk_sc_v2_vip.common.hw,
1147		[CLK_SC_V3_VIP]		= &clk_sc_v3_vip.common.hw,
1148		[CLK_DWA_VIP]		= &clk_dwa_vip.common.hw,
1149		[CLK_BT_VIP]		= &clk_bt_vip.common.hw,
1150		[CLK_DISP_VIP]		= &clk_disp_vip.common.hw,
1151		[CLK_DSI_MAC_VIP]	= &clk_dsi_mac_vip.common.hw,
1152		[CLK_LVDS0_VIP]		= &clk_lvds0_vip.common.hw,
1153		[CLK_LVDS1_VIP]		= &clk_lvds1_vip.common.hw,
1154		[CLK_PAD_VI_VIP]	= &clk_pad_vi_vip.common.hw,
1155		[CLK_PAD_VI1_VIP]	= &clk_pad_vi1_vip.common.hw,
1156		[CLK_PAD_VI2_VIP]	= &clk_pad_vi2_vip.common.hw,
1157		[CLK_CFG_REG_VIP]	= &clk_cfg_reg_vip.common.hw,
1158		[CLK_VIP_IP0]		= &clk_vip_ip0.common.hw,
1159		[CLK_VIP_IP1]		= &clk_vip_ip1.common.hw,
1160		[CLK_VIP_IP2]		= &clk_vip_ip2.common.hw,
1161		[CLK_VIP_IP3]		= &clk_vip_ip3.common.hw,
1162		[CLK_IVE_VIP]		= &clk_ive_vip.common.hw,
1163		[CLK_RAW_VIP]		= &clk_raw_vip.common.hw,
1164		[CLK_OSDC_VIP]		= &clk_osdc_vip.common.hw,
1165		[CLK_CAM0_VIP]		= &clk_cam0_vip.common.hw,
1166		[CLK_AXI_VIDEO_CODEC]	= &clk_axi_video_codec.mux.common.hw,
1167		[CLK_VC_SRC0]		= &clk_vc_src0.mux.common.hw,
1168		[CLK_VC_SRC1]		= &clk_vc_src1.div.common.hw,
1169		[CLK_VC_SRC2]		= &clk_vc_src2.div.common.hw,
1170		[CLK_H264C]		= &clk_h264c.common.hw,
1171		[CLK_APB_H264C]		= &clk_apb_h264c.common.hw,
1172		[CLK_H265C]		= &clk_h265c.common.hw,
1173		[CLK_APB_H265C]		= &clk_apb_h265c.common.hw,
1174		[CLK_JPEG]		= &clk_jpeg.common.hw,
1175		[CLK_APB_JPEG]		= &clk_apb_jpeg.common.hw,
1176		[CLK_CAM0]		= &clk_cam0.common.hw,
1177		[CLK_CAM1]		= &clk_cam1.common.hw,
1178		[CLK_WGN]		= &clk_wgn.common.hw,
1179		[CLK_WGN0]		= &clk_wgn0.common.hw,
1180		[CLK_WGN1]		= &clk_wgn1.common.hw,
1181		[CLK_WGN2]		= &clk_wgn2.common.hw,
1182		[CLK_KEYSCAN]		= &clk_keyscan.common.hw,
1183		[CLK_CFG_REG_VC]	= &clk_cfg_reg_vc.common.hw,
1184		[CLK_C906_0]		= &clk_c906_0.common.hw,
1185		[CLK_C906_1]		= &clk_c906_1.common.hw,
1186		[CLK_A53]		= &clk_a53.common.hw,
1187		[CLK_CPU_AXI0]		= &clk_cpu_axi0.div.common.hw,
1188		[CLK_CPU_GIC]		= &clk_cpu_gic.div.common.hw,
1189		[CLK_XTAL_AP]		= &clk_xtal_ap.common.hw,
1190	},
1191};
1192
1193static void cv18xx_clk_disable_auto_pd(void __iomem *base)
1194{
1195	static const u16 CV1800_PD_CLK[] = {
1196		REG_MIPIMPLL_CLK_CSR,
1197		REG_A0PLL_CLK_CSR,
1198		REG_DISPPLL_CLK_CSR,
1199		REG_CAM0PLL_CLK_CSR,
1200		REG_CAM1PLL_CLK_CSR,
1201	};
1202
1203	u32 val;
1204	int i;
1205
1206	/* disable auto power down */
1207	for (i = 0; i < ARRAY_SIZE(CV1800_PD_CLK); i++) {
1208		u32 reg = CV1800_PD_CLK[i];
1209
1210		val = readl(base + reg);
1211		val |= GENMASK(12, 9);
1212		val &= ~BIT(8);
1213		writel(val, base + reg);
1214	}
1215}
1216
1217static void cv18xx_clk_disable_a53(void __iomem *base)
1218{
1219	u32 val = readl(base + REG_CLK_BYP_0);
1220
1221	/* Set bypass clock for clk_a53 */
1222	val |= BIT(0);
1223
1224	/* Set bypass clock for clk_cpu_axi0 */
1225	val |= BIT(1);
1226
1227	/* Set bypass clock for clk_cpu_gic */
1228	val |= BIT(2);
1229
1230	writel(val, base + REG_CLK_BYP_0);
1231}
1232
1233static int cv1800_pre_init(struct device *dev, void __iomem *base,
1234			   struct cv1800_clk_ctrl *ctrl,
1235			   const struct cv1800_clk_desc *desc)
1236{
1237	u32 val = readl(base + REG_CLK_EN_2);
1238
1239	/* disable unsupported clk_disp_src_vip */
1240	val &= ~BIT(7);
1241
1242	writel(val, base + REG_CLK_EN_2);
1243
1244	cv18xx_clk_disable_a53(base);
1245	cv18xx_clk_disable_auto_pd(base);
1246
1247	return 0;
1248}
1249
1250static const struct cv1800_clk_desc cv1800_desc = {
1251	.clks_data	= &cv1800_hw_clks,
1252	.pre_init	= cv1800_pre_init,
1253};
1254
1255static struct clk_hw_onecell_data cv1810_hw_clks = {
1256	.num	= CV1810_CLK_MAX,
1257	.hws	= {
1258		[CLK_MPLL]		= &clk_mpll.common.hw,
1259		[CLK_TPLL]		= &clk_tpll.common.hw,
1260		[CLK_FPLL]		= &clk_fpll.common.hw,
1261		[CLK_MIPIMPLL]		= &clk_mipimpll.common.hw,
1262		[CLK_A0PLL]		= &clk_a0pll.common.hw,
1263		[CLK_DISPPLL]		= &clk_disppll.common.hw,
1264		[CLK_CAM0PLL]		= &clk_cam0pll.common.hw,
1265		[CLK_CAM1PLL]		= &clk_cam1pll.common.hw,
1266
1267		[CLK_MIPIMPLL_D3]	= &clk_mipimpll_d3.common.hw,
1268		[CLK_CAM0PLL_D2]	= &clk_cam0pll_d2.common.hw,
1269		[CLK_CAM0PLL_D3]	= &clk_cam0pll_d3.common.hw,
1270
1271		[CLK_TPU]		= &clk_tpu.mux.common.hw,
1272		[CLK_TPU_FAB]		= &clk_tpu_fab.common.hw,
1273		[CLK_AHB_ROM]		= &clk_ahb_rom.common.hw,
1274		[CLK_DDR_AXI_REG]	= &clk_ddr_axi_reg.common.hw,
1275		[CLK_RTC_25M]		= &clk_rtc_25m.common.hw,
1276		[CLK_SRC_RTC_SYS_0]	= &clk_src_rtc_sys_0.div.common.hw,
1277		[CLK_TEMPSEN]		= &clk_tempsen.common.hw,
1278		[CLK_SARADC]		= &clk_saradc.common.hw,
1279		[CLK_EFUSE]		= &clk_efuse.common.hw,
1280		[CLK_APB_EFUSE]		= &clk_apb_efuse.common.hw,
1281		[CLK_DEBUG]		= &clk_debug.common.hw,
1282		[CLK_AP_DEBUG]		= &clk_ap_debug.div.common.hw,
1283		[CLK_XTAL_MISC]		= &clk_xtal_misc.common.hw,
1284		[CLK_AXI4_EMMC]		= &clk_axi4_emmc.common.hw,
1285		[CLK_EMMC]		= &clk_emmc.mux.common.hw,
1286		[CLK_EMMC_100K]		= &clk_emmc_100k.common.hw,
1287		[CLK_AXI4_SD0]		= &clk_axi4_sd0.common.hw,
1288		[CLK_SD0]		= &clk_sd0.mux.common.hw,
1289		[CLK_SD0_100K]		= &clk_sd0_100k.common.hw,
1290		[CLK_AXI4_SD1]		= &clk_axi4_sd1.common.hw,
1291		[CLK_SD1]		= &clk_sd1.mux.common.hw,
1292		[CLK_SD1_100K]		= &clk_sd1_100k.common.hw,
1293		[CLK_SPI_NAND]		= &clk_spi_nand.mux.common.hw,
1294		[CLK_ETH0_500M]		= &clk_eth0_500m.div.common.hw,
1295		[CLK_AXI4_ETH0]		= &clk_axi4_eth0.common.hw,
1296		[CLK_ETH1_500M]		= &clk_eth1_500m.div.common.hw,
1297		[CLK_AXI4_ETH1]		= &clk_axi4_eth1.common.hw,
1298		[CLK_APB_GPIO]		= &clk_apb_gpio.common.hw,
1299		[CLK_APB_GPIO_INTR]	= &clk_apb_gpio_intr.common.hw,
1300		[CLK_GPIO_DB]		= &clk_gpio_db.common.hw,
1301		[CLK_AHB_SF]		= &clk_ahb_sf.common.hw,
1302		[CLK_AHB_SF1]		= &clk_ahb_sf1.common.hw,
1303		[CLK_A24M]		= &clk_a24m.common.hw,
1304		[CLK_AUDSRC]		= &clk_audsrc.mux.common.hw,
1305		[CLK_APB_AUDSRC]	= &clk_apb_audsrc.common.hw,
1306		[CLK_SDMA_AXI]		= &clk_sdma_axi.common.hw,
1307		[CLK_SDMA_AUD0]		= &clk_sdma_aud0.mux.common.hw,
1308		[CLK_SDMA_AUD1]		= &clk_sdma_aud1.mux.common.hw,
1309		[CLK_SDMA_AUD2]		= &clk_sdma_aud2.mux.common.hw,
1310		[CLK_SDMA_AUD3]		= &clk_sdma_aud3.mux.common.hw,
1311		[CLK_I2C]		= &clk_i2c.div.common.hw,
1312		[CLK_APB_I2C]		= &clk_apb_i2c.common.hw,
1313		[CLK_APB_I2C0]		= &clk_apb_i2c0.common.hw,
1314		[CLK_APB_I2C1]		= &clk_apb_i2c1.common.hw,
1315		[CLK_APB_I2C2]		= &clk_apb_i2c2.common.hw,
1316		[CLK_APB_I2C3]		= &clk_apb_i2c3.common.hw,
1317		[CLK_APB_I2C4]		= &clk_apb_i2c4.common.hw,
1318		[CLK_APB_WDT]		= &clk_apb_wdt.common.hw,
1319		[CLK_PWM_SRC]		= &clk_pwm_src.mux.common.hw,
1320		[CLK_PWM]		= &clk_pwm.common.hw,
1321		[CLK_SPI]		= &clk_spi.div.common.hw,
1322		[CLK_APB_SPI0]		= &clk_apb_spi0.common.hw,
1323		[CLK_APB_SPI1]		= &clk_apb_spi1.common.hw,
1324		[CLK_APB_SPI2]		= &clk_apb_spi2.common.hw,
1325		[CLK_APB_SPI3]		= &clk_apb_spi3.common.hw,
1326		[CLK_1M]		= &clk_1m.common.hw,
1327		[CLK_CAM0_200]		= &clk_cam0_200.mux.common.hw,
1328		[CLK_PM]		= &clk_pm.common.hw,
1329		[CLK_TIMER0]		= &clk_timer0.common.hw,
1330		[CLK_TIMER1]		= &clk_timer1.common.hw,
1331		[CLK_TIMER2]		= &clk_timer2.common.hw,
1332		[CLK_TIMER3]		= &clk_timer3.common.hw,
1333		[CLK_TIMER4]		= &clk_timer4.common.hw,
1334		[CLK_TIMER5]		= &clk_timer5.common.hw,
1335		[CLK_TIMER6]		= &clk_timer6.common.hw,
1336		[CLK_TIMER7]		= &clk_timer7.common.hw,
1337		[CLK_UART0]		= &clk_uart0.common.hw,
1338		[CLK_APB_UART0]		= &clk_apb_uart0.common.hw,
1339		[CLK_UART1]		= &clk_uart1.common.hw,
1340		[CLK_APB_UART1]		= &clk_apb_uart1.common.hw,
1341		[CLK_UART2]		= &clk_uart2.common.hw,
1342		[CLK_APB_UART2]		= &clk_apb_uart2.common.hw,
1343		[CLK_UART3]		= &clk_uart3.common.hw,
1344		[CLK_APB_UART3]		= &clk_apb_uart3.common.hw,
1345		[CLK_UART4]		= &clk_uart4.common.hw,
1346		[CLK_APB_UART4]		= &clk_apb_uart4.common.hw,
1347		[CLK_APB_I2S0]		= &clk_apb_i2s0.common.hw,
1348		[CLK_APB_I2S1]		= &clk_apb_i2s1.common.hw,
1349		[CLK_APB_I2S2]		= &clk_apb_i2s2.common.hw,
1350		[CLK_APB_I2S3]		= &clk_apb_i2s3.common.hw,
1351		[CLK_AXI4_USB]		= &clk_axi4_usb.common.hw,
1352		[CLK_APB_USB]		= &clk_apb_usb.common.hw,
1353		[CLK_USB_125M]		= &clk_usb_125m.div.common.hw,
1354		[CLK_USB_33K]		= &clk_usb_33k.common.hw,
1355		[CLK_USB_12M]		= &clk_usb_12m.div.common.hw,
1356		[CLK_AXI4]		= &clk_axi4.mux.common.hw,
1357		[CLK_AXI6]		= &clk_axi6.div.common.hw,
1358		[CLK_DSI_ESC]		= &clk_dsi_esc.div.common.hw,
1359		[CLK_AXI_VIP]		= &clk_axi_vip.mux.common.hw,
1360		[CLK_SRC_VIP_SYS_0]	= &clk_src_vip_sys_0.mux.common.hw,
1361		[CLK_SRC_VIP_SYS_1]	= &clk_src_vip_sys_1.mux.common.hw,
1362		[CLK_SRC_VIP_SYS_2]	= &clk_src_vip_sys_2.mux.common.hw,
1363		[CLK_SRC_VIP_SYS_3]	= &clk_src_vip_sys_3.mux.common.hw,
1364		[CLK_SRC_VIP_SYS_4]	= &clk_src_vip_sys_4.mux.common.hw,
1365		[CLK_CSI_BE_VIP]	= &clk_csi_be_vip.common.hw,
1366		[CLK_CSI_MAC0_VIP]	= &clk_csi_mac0_vip.common.hw,
1367		[CLK_CSI_MAC1_VIP]	= &clk_csi_mac1_vip.common.hw,
1368		[CLK_CSI_MAC2_VIP]	= &clk_csi_mac2_vip.common.hw,
1369		[CLK_CSI0_RX_VIP]	= &clk_csi0_rx_vip.common.hw,
1370		[CLK_CSI1_RX_VIP]	= &clk_csi1_rx_vip.common.hw,
1371		[CLK_ISP_TOP_VIP]	= &clk_isp_top_vip.common.hw,
1372		[CLK_IMG_D_VIP]		= &clk_img_d_vip.common.hw,
1373		[CLK_IMG_V_VIP]		= &clk_img_v_vip.common.hw,
1374		[CLK_SC_TOP_VIP]	= &clk_sc_top_vip.common.hw,
1375		[CLK_SC_D_VIP]		= &clk_sc_d_vip.common.hw,
1376		[CLK_SC_V1_VIP]		= &clk_sc_v1_vip.common.hw,
1377		[CLK_SC_V2_VIP]		= &clk_sc_v2_vip.common.hw,
1378		[CLK_SC_V3_VIP]		= &clk_sc_v3_vip.common.hw,
1379		[CLK_DWA_VIP]		= &clk_dwa_vip.common.hw,
1380		[CLK_BT_VIP]		= &clk_bt_vip.common.hw,
1381		[CLK_DISP_VIP]		= &clk_disp_vip.common.hw,
1382		[CLK_DSI_MAC_VIP]	= &clk_dsi_mac_vip.common.hw,
1383		[CLK_LVDS0_VIP]		= &clk_lvds0_vip.common.hw,
1384		[CLK_LVDS1_VIP]		= &clk_lvds1_vip.common.hw,
1385		[CLK_PAD_VI_VIP]	= &clk_pad_vi_vip.common.hw,
1386		[CLK_PAD_VI1_VIP]	= &clk_pad_vi1_vip.common.hw,
1387		[CLK_PAD_VI2_VIP]	= &clk_pad_vi2_vip.common.hw,
1388		[CLK_CFG_REG_VIP]	= &clk_cfg_reg_vip.common.hw,
1389		[CLK_VIP_IP0]		= &clk_vip_ip0.common.hw,
1390		[CLK_VIP_IP1]		= &clk_vip_ip1.common.hw,
1391		[CLK_VIP_IP2]		= &clk_vip_ip2.common.hw,
1392		[CLK_VIP_IP3]		= &clk_vip_ip3.common.hw,
1393		[CLK_IVE_VIP]		= &clk_ive_vip.common.hw,
1394		[CLK_RAW_VIP]		= &clk_raw_vip.common.hw,
1395		[CLK_OSDC_VIP]		= &clk_osdc_vip.common.hw,
1396		[CLK_CAM0_VIP]		= &clk_cam0_vip.common.hw,
1397		[CLK_AXI_VIDEO_CODEC]	= &clk_axi_video_codec.mux.common.hw,
1398		[CLK_VC_SRC0]		= &clk_vc_src0.mux.common.hw,
1399		[CLK_VC_SRC1]		= &clk_vc_src1.div.common.hw,
1400		[CLK_VC_SRC2]		= &clk_vc_src2.div.common.hw,
1401		[CLK_H264C]		= &clk_h264c.common.hw,
1402		[CLK_APB_H264C]		= &clk_apb_h264c.common.hw,
1403		[CLK_H265C]		= &clk_h265c.common.hw,
1404		[CLK_APB_H265C]		= &clk_apb_h265c.common.hw,
1405		[CLK_JPEG]		= &clk_jpeg.common.hw,
1406		[CLK_APB_JPEG]		= &clk_apb_jpeg.common.hw,
1407		[CLK_CAM0]		= &clk_cam0.common.hw,
1408		[CLK_CAM1]		= &clk_cam1.common.hw,
1409		[CLK_WGN]		= &clk_wgn.common.hw,
1410		[CLK_WGN0]		= &clk_wgn0.common.hw,
1411		[CLK_WGN1]		= &clk_wgn1.common.hw,
1412		[CLK_WGN2]		= &clk_wgn2.common.hw,
1413		[CLK_KEYSCAN]		= &clk_keyscan.common.hw,
1414		[CLK_CFG_REG_VC]	= &clk_cfg_reg_vc.common.hw,
1415		[CLK_C906_0]		= &clk_c906_0.common.hw,
1416		[CLK_C906_1]		= &clk_c906_1.common.hw,
1417		[CLK_A53]		= &clk_a53.common.hw,
1418		[CLK_CPU_AXI0]		= &clk_cpu_axi0.div.common.hw,
1419		[CLK_CPU_GIC]		= &clk_cpu_gic.div.common.hw,
1420		[CLK_XTAL_AP]		= &clk_xtal_ap.common.hw,
1421		[CLK_DISP_SRC_VIP]	= &clk_disp_src_vip.div.common.hw,
1422	},
1423};
1424
1425static int cv1810_pre_init(struct device *dev, void __iomem *base,
1426			   struct cv1800_clk_ctrl *ctrl,
1427			   const struct cv1800_clk_desc *desc)
1428{
1429	cv18xx_clk_disable_a53(base);
1430	cv18xx_clk_disable_auto_pd(base);
1431
1432	return 0;
1433}
1434
1435static const struct cv1800_clk_desc cv1810_desc = {
1436	.clks_data	= &cv1810_hw_clks,
1437	.pre_init	= cv1810_pre_init,
1438};
1439
1440static int sg2000_pre_init(struct device *dev, void __iomem *base,
1441			   struct cv1800_clk_ctrl *ctrl,
1442			   const struct cv1800_clk_desc *desc)
1443{
1444	cv18xx_clk_disable_auto_pd(base);
1445
1446	return 0;
1447}
1448
1449static const struct cv1800_clk_desc sg2000_desc = {
1450	.clks_data	= &cv1810_hw_clks,
1451	.pre_init	= sg2000_pre_init,
1452};
1453
1454static int cv1800_clk_init_ctrl(struct device *dev, void __iomem *reg,
1455				struct cv1800_clk_ctrl *ctrl,
1456				const struct cv1800_clk_desc *desc)
1457{
1458	int i, ret;
1459
1460	ctrl->desc = desc;
1461	spin_lock_init(&ctrl->lock);
1462
1463	for (i = 0; i < desc->clks_data->num; i++) {
1464		struct clk_hw *hw = desc->clks_data->hws[i];
1465		struct cv1800_clk_common *common;
1466		const char *name;
1467
1468		if (!hw)
1469			continue;
1470
1471		name = hw->init->name;
1472
1473		common = hw_to_cv1800_clk_common(hw);
1474		common->base = reg;
1475		common->lock = &ctrl->lock;
1476
1477		ret = devm_clk_hw_register(dev, hw);
1478		if (ret) {
1479			dev_err(dev, "Couldn't register clock %d - %s\n",
1480				i, name);
1481			return ret;
1482		}
1483	}
1484
1485	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1486					   desc->clks_data);
1487}
1488
1489static int cv1800_clk_probe(struct platform_device *pdev)
1490{
1491	struct device *dev = &pdev->dev;
1492	void __iomem *reg;
1493	int ret;
1494	const struct cv1800_clk_desc *desc;
1495	struct cv1800_clk_ctrl *ctrl;
1496
1497	reg = devm_platform_ioremap_resource(pdev, 0);
1498	if (IS_ERR(reg))
1499		return PTR_ERR(reg);
1500
1501	desc = device_get_match_data(dev);
1502	if (!desc) {
1503		dev_err(dev, "no match data for platform\n");
1504		return -EINVAL;
1505	}
1506
1507	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1508	if (!ctrl)
1509		return -ENOMEM;
1510
1511	if (desc->pre_init) {
1512		ret = desc->pre_init(dev, reg, ctrl, desc);
1513		if (ret)
1514			return ret;
1515	}
1516
1517	return cv1800_clk_init_ctrl(dev, reg, ctrl, desc);
1518}
1519
1520static const struct of_device_id cv1800_clk_ids[] = {
1521	{ .compatible = "sophgo,cv1800-clk", .data = &cv1800_desc },
1522	{ .compatible = "sophgo,cv1800b-clk", .data = &cv1800_desc },
1523	{ .compatible = "sophgo,cv1810-clk", .data = &cv1810_desc },
1524	{ .compatible = "sophgo,cv1812h-clk", .data = &cv1810_desc },
1525	{ .compatible = "sophgo,sg2000-clk", .data = &sg2000_desc },
1526	{ }
1527};
1528MODULE_DEVICE_TABLE(of, cv1800_clk_ids);
1529
1530static struct platform_driver cv1800_clk_driver = {
1531	.probe	= cv1800_clk_probe,
1532	.driver	= {
1533		.name			= "cv1800-clk",
1534		.suppress_bind_attrs	= true,
1535		.of_match_table		= cv1800_clk_ids,
1536	},
1537};
1538module_platform_driver(cv1800_clk_driver);
1539MODULE_DESCRIPTION("Sophgo CV1800 series SoCs clock controller");
1540MODULE_LICENSE("GPL");