stratix10-clk.h

  1/* SPDX-License-Identifier:    GPL-2.0 */
  2/*
  3 * Copyright (C) 2017, Intel Corporation
  4 */
  5
  6#ifndef	__STRATIX10_CLK_H
  7#define	__STRATIX10_CLK_H
  8
  9struct stratix10_clock_data {
 10	void __iomem		*base;
 11
 12	/* Must be last */
 13	struct clk_hw_onecell_data	clk_data;
 14};
 15
 16struct stratix10_pll_clock {
 17	unsigned int		id;
 18	const char		*name;
 19	const struct clk_parent_data	*parent_data;
 20	u8			num_parents;
 21	unsigned long		flags;
 22	unsigned long		offset;
 23};
 24
 25struct stratix10_perip_c_clock {
 26	unsigned int		id;
 27	const char		*name;
 28	const char		*parent_name;
 29	const struct clk_parent_data	*parent_data;
 30	u8			num_parents;
 31	unsigned long		flags;
 32	unsigned long		offset;
 33};
 34
 35struct n5x_perip_c_clock {
 36	unsigned int		id;
 37	const char		*name;
 38	const char		*parent_name;
 39	const char		*const *parent_names;
 40	u8			num_parents;
 41	unsigned long		flags;
 42	unsigned long		offset;
 43	unsigned long		shift;
 44};
 45
 46struct stratix10_perip_cnt_clock {
 47	unsigned int		id;
 48	const char		*name;
 49	const char		*parent_name;
 50	const struct clk_parent_data	*parent_data;
 51	u8			num_parents;
 52	unsigned long		flags;
 53	unsigned long		offset;
 54	u8			fixed_divider;
 55	unsigned long		bypass_reg;
 56	unsigned long		bypass_shift;
 57};
 58
 59struct stratix10_gate_clock {
 60	unsigned int		id;
 61	const char		*name;
 62	const char		*parent_name;
 63	const struct clk_parent_data	*parent_data;
 64	u8			num_parents;
 65	unsigned long		flags;
 66	unsigned long		gate_reg;
 67	u8			gate_idx;
 68	unsigned long		div_reg;
 69	u8			div_offset;
 70	u8			div_width;
 71	unsigned long		bypass_reg;
 72	u8			bypass_shift;
 73	u8			fixed_div;
 74};
 75
 76struct agilex5_pll_clock {
 77	unsigned int	id;
 78	const char	*name;
 79	const char	* const *parent_names;
 80	u8	num_parents;
 81	unsigned long   flags;
 82	unsigned long   offset;
 83};
 84
 85struct agilex5_perip_cnt_clock {
 86	unsigned int		id;
 87	const char		*name;
 88	const char	* const *parent_names;
 89	u8			num_parents;
 90	unsigned long		flags;
 91	unsigned long		offset;
 92	u8			fixed_divider;
 93	unsigned long		bypass_reg;
 94	unsigned long		bypass_shift;
 95};
 96
 97struct agilex5_gate_clock {
 98	unsigned int		id;
 99	const char		*name;
100	const char	* const *parent_names;
101	u8			num_parents;
102	unsigned long		flags;
103	unsigned long		gate_reg;
104	u8			gate_idx;
105	unsigned long		div_reg;
106	u8			div_offset;
107	u8			div_width;
108	unsigned long		bypass_reg;
109	u8			bypass_shift;
110	u8			fixed_div;
111};
112
113struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
114			     void __iomem *reg);
115struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
116				void __iomem *reg);
117struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
118			     void __iomem *reg);
119struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks,
120				    void __iomem *reg);
121struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock *clks,
122					   void __iomem *regbase);
123struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks,
124				     void __iomem *regbase);
125struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
126				void __iomem *reg);
127struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
128				void __iomem *reg);
129struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
130				    void __iomem *reg);
131struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
132			      void __iomem *reg);
133struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
134			      void __iomem *reg);
135#endif	/* __STRATIX10_CLK_H */