clk-s5pv210-audss.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com>
  4 *
  5 * Based on Exynos Audio Subsystem Clock Controller driver:
  6 *
  7 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  8 * Author: Padmavathi Venna <padma.v@samsung.com>
  9 *
 10 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
 11 */
 12
 13#include <linux/io.h>
 14#include <linux/clk.h>
 15#include <linux/clk-provider.h>
 16#include <linux/mod_devicetable.h>
 17#include <linux/of_address.h>
 18#include <linux/syscore_ops.h>
 19#include <linux/init.h>
 20#include <linux/platform_device.h>
 21
 22#include <dt-bindings/clock/s5pv210-audss.h>
 23
 24static DEFINE_SPINLOCK(lock);
 25static void __iomem *reg_base;
 26static struct clk_hw_onecell_data *clk_data;
 27
 28#define ASS_CLK_SRC 0x0
 29#define ASS_CLK_DIV 0x4
 30#define ASS_CLK_GATE 0x8
 31
 32#ifdef CONFIG_PM_SLEEP
 33static unsigned long reg_save[][2] = {
 34	{ASS_CLK_SRC,  0},
 35	{ASS_CLK_DIV,  0},
 36	{ASS_CLK_GATE, 0},
 37};
 38
 39static int s5pv210_audss_clk_suspend(void *data)
 40{
 41	int i;
 42
 43	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
 44		reg_save[i][1] = readl(reg_base + reg_save[i][0]);
 45
 46	return 0;
 47}
 48
 49static void s5pv210_audss_clk_resume(void *data)
 50{
 51	int i;
 52
 53	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
 54		writel(reg_save[i][1], reg_base + reg_save[i][0]);
 55}
 56
 57static const struct syscore_ops s5pv210_audss_clk_syscore_ops = {
 58	.suspend	= s5pv210_audss_clk_suspend,
 59	.resume		= s5pv210_audss_clk_resume,
 60};
 61
 62static struct syscore s5pv210_audss_clk_syscore = {
 63	.ops = &s5pv210_audss_clk_syscore_ops,
 64};
 65#endif /* CONFIG_PM_SLEEP */
 66
 67/* register s5pv210_audss clocks */
 68static int s5pv210_audss_clk_probe(struct platform_device *pdev)
 69{
 70	int i, ret = 0;
 71	const char *mout_audss_p[2];
 72	const char *mout_i2s_p[3];
 73	const char *hclk_p;
 74	struct clk_hw **clk_table;
 75	struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
 76
 77	reg_base = devm_platform_ioremap_resource(pdev, 0);
 78	if (IS_ERR(reg_base))
 79		return PTR_ERR(reg_base);
 80
 81	clk_data = devm_kzalloc(&pdev->dev,
 82				struct_size(clk_data, hws, AUDSS_MAX_CLKS),
 83				GFP_KERNEL);
 84
 85	if (!clk_data)
 86		return -ENOMEM;
 87
 88	clk_data->num = AUDSS_MAX_CLKS;
 89	clk_table = clk_data->hws;
 90
 91	hclk = devm_clk_get(&pdev->dev, "hclk");
 92	if (IS_ERR(hclk)) {
 93		dev_err(&pdev->dev, "failed to get hclk clock\n");
 94		return PTR_ERR(hclk);
 95	}
 96
 97	pll_in = devm_clk_get(&pdev->dev, "fout_epll");
 98	if (IS_ERR(pll_in)) {
 99		dev_err(&pdev->dev, "failed to get fout_epll clock\n");
100		return PTR_ERR(pll_in);
101	}
102
103	sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0");
104	if (IS_ERR(sclk_audio)) {
105		dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n");
106		return PTR_ERR(sclk_audio);
107	}
108
109	/* iiscdclk0 is an optional external I2S codec clock */
110	cdclk = devm_clk_get(&pdev->dev, "iiscdclk0");
111	pll_ref = devm_clk_get(&pdev->dev, "xxti");
112
113	if (!IS_ERR(pll_ref))
114		mout_audss_p[0] = __clk_get_name(pll_ref);
115	else
116		mout_audss_p[0] = "xxti";
117	mout_audss_p[1] = __clk_get_name(pll_in);
118	clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
119				mout_audss_p, ARRAY_SIZE(mout_audss_p),
120				CLK_SET_RATE_NO_REPARENT,
121				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
122
123	mout_i2s_p[0] = "mout_audss";
124	if (!IS_ERR(cdclk))
125		mout_i2s_p[1] = __clk_get_name(cdclk);
126	else
127		mout_i2s_p[1] = "iiscdclk0";
128	mout_i2s_p[2] = __clk_get_name(sclk_audio);
129	clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss",
130				mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
131				CLK_SET_RATE_NO_REPARENT,
132				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
133
134	clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
135				"dout_aud_bus", "mout_audss", 0,
136				reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
137	clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
138				"dout_i2s_audss", "mout_i2s_audss", 0,
139				reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
140
141	clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
142				"dout_i2s_audss", CLK_SET_RATE_PARENT,
143				reg_base + ASS_CLK_GATE, 6, 0, &lock);
144
145	hclk_p = __clk_get_name(hclk);
146
147	clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
148				hclk_p, CLK_IGNORE_UNUSED,
149				reg_base + ASS_CLK_GATE, 5, 0, &lock);
150	clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
151				hclk_p, CLK_IGNORE_UNUSED,
152				reg_base + ASS_CLK_GATE, 4, 0, &lock);
153	clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
154				hclk_p, CLK_IGNORE_UNUSED,
155				reg_base + ASS_CLK_GATE, 3, 0, &lock);
156	clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
157				hclk_p, CLK_IGNORE_UNUSED,
158				reg_base + ASS_CLK_GATE, 2, 0, &lock);
159	clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
160				hclk_p, CLK_IGNORE_UNUSED,
161				reg_base + ASS_CLK_GATE, 1, 0, &lock);
162	clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
163				hclk_p, CLK_IGNORE_UNUSED,
164				reg_base + ASS_CLK_GATE, 0, 0, &lock);
165
166	for (i = 0; i < clk_data->num; i++) {
167		if (IS_ERR(clk_table[i])) {
168			dev_err(&pdev->dev, "failed to register clock %d\n", i);
169			ret = PTR_ERR(clk_table[i]);
170			goto unregister;
171		}
172	}
173
174	ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
175				     clk_data);
176	if (ret) {
177		dev_err(&pdev->dev, "failed to add clock provider\n");
178		goto unregister;
179	}
180
181#ifdef CONFIG_PM_SLEEP
182	register_syscore(&s5pv210_audss_clk_syscore);
183#endif
184
185	return 0;
186
187unregister:
188	for (i = 0; i < clk_data->num; i++) {
189		if (!IS_ERR(clk_table[i]))
190			clk_hw_unregister(clk_table[i]);
191	}
192
193	return ret;
194}
195
196static const struct of_device_id s5pv210_audss_clk_of_match[] = {
197	{ .compatible = "samsung,s5pv210-audss-clock", },
198	{},
199};
200
201static struct platform_driver s5pv210_audss_clk_driver = {
202	.driver	= {
203		.name = "s5pv210-audss-clk",
204		.suppress_bind_attrs = true,
205		.of_match_table = s5pv210_audss_clk_of_match,
206	},
207	.probe = s5pv210_audss_clk_probe,
208};
209
210static int __init s5pv210_audss_clk_init(void)
211{
212	return platform_driver_register(&s5pv210_audss_clk_driver);
213}
214core_initcall(s5pv210_audss_clk_init);