clk-pll.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4 * Copyright (c) 2013 Linaro Ltd.
  5 *
  6 * Common Clock Framework support for all PLL's in Samsung platforms
  7*/
  8
  9#ifndef __SAMSUNG_CLK_PLL_H
 10#define __SAMSUNG_CLK_PLL_H
 11
 12enum samsung_pll_type {
 13	pll_2126,
 14	pll_3000,
 15	pll_35xx,
 16	pll_36xx,
 17	pll_2550,
 18	pll_2650,
 19	pll_4500,
 20	pll_4502,
 21	pll_4508,
 22	pll_4600,
 23	pll_4650,
 24	pll_4650c,
 25	pll_6552,
 26	pll_6552_s3c2416,
 27	pll_6553,
 28	pll_2550x,
 29	pll_2550xx,
 30	pll_2650x,
 31	pll_2650xx,
 32	pll_1417x,
 33	pll_1418x,
 34	pll_1450x,
 35	pll_1451x,
 36	pll_1452x,
 37	pll_1460x,
 38	pll_0818x,
 39	pll_0822x,
 40	pll_0831x,
 41	pll_142xx,
 42	pll_0516x,
 43	pll_0517x,
 44	pll_0518x,
 45	pll_531x,
 46	pll_1051x,
 47	pll_1052x,
 48	pll_0717x,
 49	pll_0718x,
 50	pll_0732x,
 51	pll_4311,
 52	pll_1017x,
 53	pll_1031x,
 54};
 55
 56#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
 57	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
 58#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
 59	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
 60
 61#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)			\
 62	{							\
 63		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 64				_m, _p, _s, 0, 16),		\
 65		.mdiv	=	(_m),				\
 66		.pdiv	=	(_p),				\
 67		.sdiv	=	(_s),				\
 68	}
 69
 70#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)		\
 71	{							\
 72		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 73				_m, _p, _s, _k, 16),		\
 74		.mdiv	=	(_m),				\
 75		.pdiv	=	(_p),				\
 76		.sdiv	=	(_s),				\
 77		.kdiv	=	(_k),				\
 78	}
 79
 80#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)		\
 81	{							\
 82		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 83				_m, _p, _s - 1, 0, 16),		\
 84		.mdiv	=	(_m),				\
 85		.pdiv	=	(_p),				\
 86		.sdiv	=	(_s),				\
 87		.afc	=	(_afc),				\
 88	}
 89
 90#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)	\
 91	{							\
 92		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 93				_m, _p, _s, _k, 16),		\
 94		.mdiv	=	(_m),				\
 95		.pdiv	=	(_p),				\
 96		.sdiv	=	(_s),				\
 97		.kdiv	=	(_k),				\
 98		.vsel	=	(_vsel),			\
 99	}
100
101#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
102	{							\
103		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
104				_m, _p, _s, _k, 10),		\
105		.mdiv	=	(_m),				\
106		.pdiv	=	(_p),				\
107		.sdiv	=	(_s),				\
108		.kdiv	=	(_k),				\
109		.mfr	=	(_mfr),				\
110		.mrr	=	(_mrr),				\
111		.vsel	=	(_vsel),			\
112	}
113
114/* NOTE: Rate table should be kept sorted in descending order. */
115
116struct samsung_pll_rate_table {
117	unsigned int rate;
118	unsigned int pdiv;
119	unsigned int mdiv;
120	unsigned int sdiv;
121	unsigned int kdiv;
122	unsigned int afc;
123	unsigned int mfr;
124	unsigned int mrr;
125	unsigned int vsel;
126};
127
128#endif /* __SAMSUNG_CLK_PLL_H */