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clk-exynosautov9.c
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linux-6.19.14/drivers/clk/samsung/clk-exynosautov9.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2022 Samsung Electronics Co., Ltd. 4 * Author: Chanho Park <chanho61.park@samsung.com> 5 * 6 * Common Clock Framework support for ExynosAuto V9 SoC. 7 */ 8 9#include <linux/clk-provider.h> 10#include <linux/mod_devicetable.h> 11#include <linux/of.h> 12#include <linux/platform_device.h> 13 14#include <dt-bindings/clock/samsung,exynosautov9.h> 15 16#include "clk.h" 17#include "clk-exynos-arm64.h" 18 19/* NOTE: Must be equal to the last clock ID increased by one */ 20#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1) 21#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1) 22#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1) 23#define CLKS_NR_DPUM (CLK_GOUT_DPUM_SYSMMU_D3_CLK + 1) 24#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1) 25#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1) 26#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1) 27#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1) 28#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1) 29#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1) 30 31/* ---- CMU_TOP ------------------------------------------------------------ */ 32 33/* Register Offset definitions for CMU_TOP (0x1b240000) */ 34#define PLL_LOCKTIME_PLL_SHARED0 0x0000 35#define PLL_LOCKTIME_PLL_SHARED1 0x0004 36#define PLL_LOCKTIME_PLL_SHARED2 0x0008 37#define PLL_LOCKTIME_PLL_SHARED3 0x000c 38#define PLL_LOCKTIME_PLL_SHARED4 0x0010 39#define PLL_CON0_PLL_SHARED0 0x0100 40#define PLL_CON3_PLL_SHARED0 0x010c 41#define PLL_CON0_PLL_SHARED1 0x0140 42#define PLL_CON3_PLL_SHARED1 0x014c 43#define PLL_CON0_PLL_SHARED2 0x0180 44#define PLL_CON3_PLL_SHARED2 0x018c 45#define PLL_CON0_PLL_SHARED3 0x01c0 46#define PLL_CON3_PLL_SHARED3 0x01cc 47#define PLL_CON0_PLL_SHARED4 0x0200 48#define PLL_CON3_PLL_SHARED4 0x020c 49 50/* MUX */ 51#define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0x1000 52#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004 53#define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0x1008 54#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x100c 55#define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x1010 56#define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0x1018 57#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x101c 58#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1020 59#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024 60#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c 61#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030 62#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034 63#define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0x1040 64#define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044 65#define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0x1048 66#define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0x104c 67#define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0x1050 68#define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1054 69#define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0x1058 70#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x105c 71#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1060 72#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064 73#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0x1068 74#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0x106c 75#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0x1070 76#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1074 77#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1078 78#define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c 79#define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080 80#define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0x1084 81#define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0x108c 82#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1090 83#define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x1094 84#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c 85#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1098 86#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c 87#define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10a0 88#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a4 89#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10a8 90#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10ac 91#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10b0 92#define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10b4 93#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10c0 94 95/* DIV */ 96#define CLK_CON_DIV_CLKCMU_ACC_BUS 0x1800 97#define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804 98#define CLK_CON_DIV_CLKCMU_AUD_BUS 0x1808 99#define CLK_CON_DIV_CLKCMU_AUD_CPU 0x180c 100#define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x1810 101#define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0x1818 102#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c 103#define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820 104#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828 105#define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c 106#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830 107#define CLK_CON_DIV_CLKCMU_DPTX_BUS 0x183c 108#define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840 109#define CLK_CON_DIV_CLKCMU_DPUM_BUS 0x1844 110#define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0x1848 111#define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0x184c 112#define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1850 113#define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0x1854 114#define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1858 115#define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0x185c 116#define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0x1860 117#define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0x1864 118#define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0x1868 119#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x186c 120#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1870 121#define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0x1874 122#define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0x1878 123#define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0x187c 124#define CLK_CON_DIV_CLKCMU_ISPB_BUS 0x1884 125#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1888 126#define CLK_CON_DIV_CLKCMU_MFC_WFD 0x188c 127#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1890 128#define CLK_CON_DIV_CLKCMU_NPU_BUS 0x1894 129#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x1898 130#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x189c 131#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18a0 132#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18a4 133#define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18a8 134#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18b4 135 136#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18b8 137#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18bc 138#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c0 139#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18c4 140#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18c8 141#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x18cc 142#define CLK_CON_DIV_PLL_SHARED2_DIV3 0x18d0 143#define CLK_CON_DIV_PLL_SHARED2_DIV4 0x18d4 144#define CLK_CON_DIV_PLL_SHARED4_DIV2 0x18d4 145#define CLK_CON_DIV_PLL_SHARED4_DIV4 0x18d8 146 147/* GATE */ 148#define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0x2000 149#define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0x2004 150#define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0x2008 151#define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010 152#define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018 153#define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0x2020 154#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2024 155#define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0x2028 156#define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0x202c 157#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2030 158#define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0x2034 159#define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2038 160#define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x203c 161#define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0x2044 162#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2048 163#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x204c 164#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0x2050 165#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2058 166#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0x205c 167#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2060 168#define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0x206c 169#define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0x2070 170#define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0x2060 171#define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0x2064 172#define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0x207c 173#define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x2080 174#define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0x2084 175#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2088 176#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0x208c 177#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0x2090 178#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0x2094 179#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0x2098 180#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x209c 181#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x20a0 182#define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0x20a4 183#define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0x20a8 184#define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac 185#define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0x20b4 186#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20b8 187#define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x20bc 188#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c0 189#define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c4 190#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20c8 191#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20cc 192#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d0 193#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d4 194#define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20d8 195 196static const unsigned long top_clk_regs[] __initconst = { 197 PLL_LOCKTIME_PLL_SHARED0, 198 PLL_LOCKTIME_PLL_SHARED1, 199 PLL_LOCKTIME_PLL_SHARED2, 200 PLL_LOCKTIME_PLL_SHARED3, 201 PLL_LOCKTIME_PLL_SHARED4, 202 PLL_CON0_PLL_SHARED0, 203 PLL_CON3_PLL_SHARED0, 204 PLL_CON0_PLL_SHARED1, 205 PLL_CON3_PLL_SHARED1, 206 PLL_CON0_PLL_SHARED2, 207 PLL_CON3_PLL_SHARED2, 208 PLL_CON0_PLL_SHARED3, 209 PLL_CON3_PLL_SHARED3, 210 PLL_CON0_PLL_SHARED4, 211 PLL_CON3_PLL_SHARED4, 212 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 213 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 214 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 215 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 216 CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 217 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 218 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 219 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 220 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 221 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 222 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 223 CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 224 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 225 CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 226 CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 227 CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 228 CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 229 CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 230 CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 231 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 232 CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD, 233 CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 234 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 235 CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD, 236 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 237 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 238 CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH, 239 CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH, 240 CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH, 241 CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 242 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 243 CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 244 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 245 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 246 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 247 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 248 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 249 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 250 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 251 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 252 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 253 CLK_CON_MUX_MUX_CMU_CMUREF, 254 CLK_CON_DIV_CLKCMU_ACC_BUS, 255 CLK_CON_DIV_CLKCMU_APM_BUS, 256 CLK_CON_DIV_CLKCMU_AUD_BUS, 257 CLK_CON_DIV_CLKCMU_AUD_CPU, 258 CLK_CON_DIV_CLKCMU_BUSC_BUS, 259 CLK_CON_DIV_CLKCMU_BUSMC_BUS, 260 CLK_CON_DIV_CLKCMU_CORE_BUS, 261 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 262 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 263 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 264 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 265 CLK_CON_DIV_CLKCMU_DPTX_BUS, 266 CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 267 CLK_CON_DIV_CLKCMU_DPUM_BUS, 268 CLK_CON_DIV_CLKCMU_DPUS0_BUS, 269 CLK_CON_DIV_CLKCMU_DPUS1_BUS, 270 CLK_CON_DIV_CLKCMU_FSYS0_BUS, 271 CLK_CON_DIV_CLKCMU_FSYS0_PCIE, 272 CLK_CON_DIV_CLKCMU_FSYS1_BUS, 273 CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 274 CLK_CON_DIV_CLKCMU_FSYS2_BUS, 275 CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET, 276 CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD, 277 CLK_CON_DIV_CLKCMU_G2D_G2D, 278 CLK_CON_DIV_CLKCMU_G2D_MSCL, 279 CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 280 CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 281 CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 282 CLK_CON_DIV_CLKCMU_ISPB_BUS, 283 CLK_CON_DIV_CLKCMU_MFC_MFC, 284 CLK_CON_DIV_CLKCMU_MFC_WFD, 285 CLK_CON_DIV_CLKCMU_MIF_BUSP, 286 CLK_CON_DIV_CLKCMU_NPU_BUS, 287 CLK_CON_DIV_CLKCMU_PERIC0_BUS, 288 CLK_CON_DIV_CLKCMU_PERIC0_IP, 289 CLK_CON_DIV_CLKCMU_PERIC1_BUS, 290 CLK_CON_DIV_CLKCMU_PERIC1_IP, 291 CLK_CON_DIV_CLKCMU_PERIS_BUS, 292 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 293 CLK_CON_DIV_PLL_SHARED0_DIV2, 294 CLK_CON_DIV_PLL_SHARED0_DIV3, 295 CLK_CON_DIV_PLL_SHARED1_DIV2, 296 CLK_CON_DIV_PLL_SHARED1_DIV3, 297 CLK_CON_DIV_PLL_SHARED1_DIV4, 298 CLK_CON_DIV_PLL_SHARED2_DIV2, 299 CLK_CON_DIV_PLL_SHARED2_DIV3, 300 CLK_CON_DIV_PLL_SHARED2_DIV4, 301 CLK_CON_DIV_PLL_SHARED4_DIV2, 302 CLK_CON_DIV_PLL_SHARED4_DIV4, 303 CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 304 CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 305 CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 306 CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 307 CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 308 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 309 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 310 CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH, 311 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 312 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 313 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 314 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 315 CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 316 CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 317 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 318 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 319 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 320 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 321 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 322 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 323 CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS, 324 CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC, 325 CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS, 326 CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS, 327 CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS, 328 CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS, 329 CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE, 330 CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS, 331 CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD, 332 CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS, 333 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 334 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 335 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 336 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 337 CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH, 338 CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH, 339 CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH, 340 CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS, 341 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 342 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 343 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 344 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 345 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 346 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 347 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 348 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 349 CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS, 350}; 351 352static const struct samsung_pll_clock top_pll_clks[] __initconst = { 353 /* CMU_TOP_PURECLKCOMP */ 354 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 355 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), 356 PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 357 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL), 358 PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", 359 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL), 360 PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", 361 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL), 362 PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk", 363 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL), 364}; 365 366/* List of parent clocks for Muxes in CMU_TOP */ 367PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 368PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 369PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" }; 370PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" }; 371PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" }; 372 373PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4", 374 "dout_shared2_div4", "dout_shared4_div4" }; 375PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" }; 376PNAME(mout_clkcmu_acc_bus_p) = { "dout_shared1_div3", "dout_shared2_div3", 377 "dout_shared1_div4", "dout_shared2_div4" }; 378PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared2_div3", "dout_shared1_div4", 379 "dout_shared2_div4", "dout_shared4_div4" }; 380PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2", 381 "dout_shared2_div2", "dout_shared0_div3", 382 "dout_shared4_div2", "dout_shared1_div3", 383 "fout_shared3_pll" }; 384PNAME(mout_clkcmu_aud_bus_p) = { "dout_shared4_div2", "dout_shared1_div3", 385 "dout_shared2_div3", "dout_shared1_div4" }; 386PNAME(mout_clkcmu_busc_bus_p) = { "dout_shared2_div3", "dout_shared1_div4", 387 "dout_shared2_div4", "dout_shared4_div4" }; 388PNAME(mout_clkcmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", 389 "dout_shared2_div2", "dout_shared0_div3", 390 "dout_shared4_div2", "dout_shared1_div3", 391 "dout_shared2_div3", "fout_shared3_pll" }; 392PNAME(mout_clkcmu_cpucl0_switch_p) = { 393 "dout_shared0_div2", "dout_shared1_div2", 394 "dout_shared2_div2", "dout_shared4_div2" }; 395PNAME(mout_clkcmu_cpucl0_cluster_p) = { 396 "fout_shared2_pll", "fout_shared4_pll", 397 "dout_shared0_div2", "dout_shared1_div2", 398 "dout_shared2_div2", "dout_shared4_div2", 399 "dout_shared2_div3", "fout_shared3_pll" }; 400PNAME(mout_clkcmu_dptx_bus_p) = { "dout_shared4_div2", "dout_shared2_div3", 401 "dout_shared1_div4", "dout_shared2_div4" }; 402PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3", 403 "dout_shared2_div4", "dout_shared4_div4" }; 404PNAME(mout_clkcmu_dpum_bus_p) = { "dout_shared1_div3", "dout_shared2_div3", 405 "dout_shared1_div4", "dout_shared2_div4", 406 "dout_shared4_div4", "fout_shared3_pll" }; 407PNAME(mout_clkcmu_fsys0_bus_p) = { 408 "dout_shared4_div2", "dout_shared2_div3", 409 "dout_shared1_div4", "dout_shared2_div4" }; 410PNAME(mout_clkcmu_fsys0_pcie_p) = { "oscclk", "dout_shared2_div4" }; 411PNAME(mout_clkcmu_fsys1_bus_p) = { "dout_shared2_div3", "dout_shared1_div4", 412 "dout_shared2_div4", "dout_shared4_div4" }; 413PNAME(mout_clkcmu_fsys1_usbdrd_p) = { 414 "oscclk", "dout_shared2_div3", 415 "dout_shared2_div4", "dout_shared4_div4" }; 416PNAME(mout_clkcmu_fsys1_mmc_card_p) = { 417 "oscclk", "dout_shared2_div2", 418 "dout_shared4_div2", "dout_shared2_div3" }; 419PNAME(mout_clkcmu_fsys2_ethernet_p) = { 420 "oscclk", "dout_shared2_div2", 421 "dout_shared0_div3", "dout_shared2_div3", 422 "dout_shared1_div4", "fout_shared3_pll" }; 423PNAME(mout_clkcmu_g2d_g2d_p) = { "dout_shared2_div2", "dout_shared0_div3", 424 "dout_shared4_div2", "dout_shared1_div3", 425 "dout_shared2_div3", "dout_shared1_div4", 426 "dout_shared2_div4", "dout_shared4_div4" }; 427PNAME(mout_clkcmu_g3d0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", 428 "dout_shared2_div2", "dout_shared4_div2" }; 429PNAME(mout_clkcmu_g3d1_switch_p) = { "dout_shared2_div2", "dout_shared4_div2", 430 "dout_shared2_div3", "dout_shared1_div4" }; 431PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", 432 "fout_shared2_pll", "fout_shared4_pll", 433 "dout_shared0_div2", "dout_shared1_div2", 434 "dout_shared2_div2", "fout_shared3_pll" }; 435PNAME(mout_clkcmu_npu_bus_p) = { "dout_shared1_div2", "dout_shared2_div2", 436 "dout_shared0_div3", "dout_shared4_div2", 437 "dout_shared1_div3", "dout_shared2_div3", 438 "dout_shared1_div4", "fout_shared3_pll" }; 439PNAME(mout_clkcmu_peric0_bus_p) = { "dout_shared2_div3", "dout_shared2_div4" }; 440 441static const struct samsung_mux_clock top_mux_clks[] __initconst = { 442 /* CMU_TOP_PURECLKCOMP */ 443 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 444 PLL_CON0_PLL_SHARED0, 4, 1), 445 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 446 PLL_CON0_PLL_SHARED1, 4, 1), 447 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p, 448 PLL_CON0_PLL_SHARED2, 4, 1), 449 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p, 450 PLL_CON0_PLL_SHARED3, 4, 1), 451 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p, 452 PLL_CON0_PLL_SHARED4, 4, 1), 453 454 /* BOOST */ 455 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost", 456 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), 457 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref", 458 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), 459 460 /* ACC */ 461 MUX(MOUT_CLKCMU_ACC_BUS, "mout_clkcmu_acc_bus", mout_clkcmu_acc_bus_p, 462 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2), 463 464 /* APM */ 465 MUX(MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", mout_clkcmu_apm_bus_p, 466 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2), 467 468 /* AUD */ 469 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", mout_clkcmu_aud_cpu_p, 470 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3), 471 MUX(MOUT_CLKCMU_AUD_BUS, "mout_clkcmu_aud_bus", mout_clkcmu_aud_bus_p, 472 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2), 473 474 /* BUSC */ 475 MUX(MOUT_CLKCMU_BUSC_BUS, "mout_clkcmu_busc_bus", 476 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2), 477 478 /* BUSMC */ 479 MUX(MOUT_CLKCMU_BUSMC_BUS, "mout_clkcmu_busmc_bus", 480 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2), 481 482 /* CORE */ 483 MUX(MOUT_CLKCMU_CORE_BUS, "mout_clkcmu_core_bus", 484 mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3), 485 486 /* CPUCL0 */ 487 MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch", 488 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 489 0, 2), 490 MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster", 491 mout_clkcmu_cpucl0_cluster_p, 492 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3), 493 494 /* CPUCL1 */ 495 MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch", 496 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 497 0, 2), 498 MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster", 499 mout_clkcmu_cpucl0_cluster_p, 500 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3), 501 502 /* DPTX */ 503 MUX(MOUT_CLKCMU_DPTX_BUS, "mout_clkcmu_dptx_bus", 504 mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2), 505 MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc", 506 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2), 507 508 /* DPUM */ 509 MUX(MOUT_CLKCMU_DPUM_BUS, "mout_clkcmu_dpum_bus", 510 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3), 511 512 /* DPUS */ 513 MUX(MOUT_CLKCMU_DPUS0_BUS, "mout_clkcmu_dpus0_bus", 514 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3), 515 MUX(MOUT_CLKCMU_DPUS1_BUS, "mout_clkcmu_dpus1_bus", 516 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3), 517 518 /* FSYS0 */ 519 MUX(MOUT_CLKCMU_FSYS0_BUS, "mout_clkcmu_fsys0_bus", 520 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2), 521 MUX(MOUT_CLKCMU_FSYS0_PCIE, "mout_clkcmu_fsys0_pcie", 522 mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1), 523 524 /* FSYS1 */ 525 MUX(MOUT_CLKCMU_FSYS1_BUS, "mout_clkcmu_fsys1_bus", 526 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2), 527 MUX(MOUT_CLKCMU_FSYS1_USBDRD, "mout_clkcmu_fsys1_usbdrd", 528 mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD, 529 0, 2), 530 MUX(MOUT_CLKCMU_FSYS1_MMC_CARD, "mout_clkcmu_fsys1_mmc_card", 531 mout_clkcmu_fsys1_mmc_card_p, 532 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2), 533 534 /* FSYS2 */ 535 MUX(MOUT_CLKCMU_FSYS2_BUS, "mout_clkcmu_fsys2_bus", 536 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2), 537 MUX(MOUT_CLKCMU_FSYS2_UFS_EMBD, "mout_clkcmu_fsys2_ufs_embd", 538 mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD, 539 0, 2), 540 MUX(MOUT_CLKCMU_FSYS2_ETHERNET, "mout_clkcmu_fsys2_ethernet", 541 mout_clkcmu_fsys2_ethernet_p, 542 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3), 543 544 /* G2D */ 545 MUX(MOUT_CLKCMU_G2D_G2D, "mout_clkcmu_g2d_g2d", mout_clkcmu_g2d_g2d_p, 546 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3), 547 MUX(MOUT_CLKCMU_G2D_MSCL, "mout_clkcmu_g2d_mscl", 548 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2), 549 550 /* G3D0 */ 551 MUX(MOUT_CLKCMU_G3D00_SWITCH, "mout_clkcmu_g3d00_switch", 552 mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH, 553 0, 2), 554 MUX(MOUT_CLKCMU_G3D01_SWITCH, "mout_clkcmu_g3d01_switch", 555 mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH, 556 0, 2), 557 558 /* G3D1 */ 559 MUX(MOUT_CLKCMU_G3D1_SWITCH, "mout_clkcmu_g3d1_switch", 560 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH, 561 0, 2), 562 563 /* ISPB */ 564 MUX(MOUT_CLKCMU_ISPB_BUS, "mout_clkcmu_ispb_bus", 565 mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2), 566 567 /* MFC */ 568 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc", 569 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2), 570 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd", 571 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2), 572 573 /* MIF */ 574 MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch", 575 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), 576 MUX(MOUT_CLKCMU_MIF_BUSP, "mout_clkcmu_mif_busp", 577 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), 578 579 /* NPU */ 580 MUX(MOUT_CLKCMU_NPU_BUS, "mout_clkcmu_npu_bus", mout_clkcmu_npu_bus_p, 581 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3), 582 583 /* PERIC0 */ 584 MUX(MOUT_CLKCMU_PERIC0_BUS, "mout_clkcmu_peric0_bus", 585 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1), 586 MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip", 587 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1), 588 589 /* PERIC1 */ 590 MUX(MOUT_CLKCMU_PERIC1_BUS, "mout_clkcmu_peric1_bus", 591 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1), 592 MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip", 593 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1), 594 595 /* PERIS */ 596 MUX(MOUT_CLKCMU_PERIS_BUS, "mout_clkcmu_peris_bus", 597 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1), 598}; 599 600static const struct samsung_div_clock top_div_clks[] __initconst = { 601 /* CMU_TOP_PURECLKCOMP */ 602 DIV(DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 603 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 604 DIV(DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 605 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 606 607 DIV(DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 608 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 609 DIV(DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 610 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 611 DIV(DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 612 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 613 614 DIV(DOUT_SHARED2_DIV3, "dout_shared2_div3", "mout_shared2_pll", 615 CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2), 616 DIV(DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll", 617 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), 618 DIV(DOUT_SHARED2_DIV4, "dout_shared2_div4", "dout_shared2_div2", 619 CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1), 620 621 DIV(DOUT_SHARED4_DIV2, "dout_shared4_div2", "mout_shared4_pll", 622 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1), 623 DIV(DOUT_SHARED4_DIV4, "dout_shared4_div4", "dout_shared4_div2", 624 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), 625 626 /* BOOST */ 627 DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost", 628 "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), 629 630 /* ACC */ 631 DIV(DOUT_CLKCMU_ACC_BUS, "dout_clkcmu_acc_bus", "gout_clkcmu_acc_bus", 632 CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4), 633 634 /* APM */ 635 DIV(DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", "gout_clkcmu_apm_bus", 636 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 637 638 /* AUD */ 639 DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", "gout_clkcmu_aud_cpu", 640 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3), 641 DIV(DOUT_CLKCMU_AUD_BUS, "dout_clkcmu_aud_bus", "gout_clkcmu_aud_bus", 642 CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4), 643 644 /* BUSC */ 645 DIV(DOUT_CLKCMU_BUSC_BUS, "dout_clkcmu_busc_bus", 646 "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4), 647 648 /* BUSMC */ 649 DIV(DOUT_CLKCMU_BUSMC_BUS, "dout_clkcmu_busmc_bus", 650 "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4), 651 652 /* CORE */ 653 DIV(DOUT_CLKCMU_CORE_BUS, "dout_clkcmu_core_bus", 654 "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 655 656 /* CPUCL0 */ 657 DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch", 658 "gout_clkcmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 659 0, 3), 660 DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster", 661 "gout_clkcmu_cpucl0_cluster", CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 662 0, 3), 663 664 /* CPUCL1 */ 665 DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch", 666 "gout_clkcmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 667 0, 3), 668 DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster", 669 "gout_clkcmu_cpucl1_cluster", CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 670 0, 3), 671 672 /* DPTX */ 673 DIV(DOUT_CLKCMU_DPTX_BUS, "dout_clkcmu_dptx_bus", 674 "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4), 675 DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc", 676 "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3), 677 678 /* DPUM */ 679 DIV(DOUT_CLKCMU_DPUM_BUS, "dout_clkcmu_dpum_bus", 680 "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4), 681 682 /* DPUS */ 683 DIV(DOUT_CLKCMU_DPUS0_BUS, "dout_clkcmu_dpus0_bus", 684 "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4), 685 DIV(DOUT_CLKCMU_DPUS1_BUS, "dout_clkcmu_dpus1_bus", 686 "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4), 687 688 /* FSYS0 */ 689 DIV(DOUT_CLKCMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus", 690 "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4), 691 692 /* FSYS1 */ 693 DIV(DOUT_CLKCMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus", 694 "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4), 695 DIV(DOUT_CLKCMU_FSYS1_USBDRD, "dout_clkcmu_fsys1_usbdrd", 696 "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4), 697 698 /* FSYS2 */ 699 DIV(DOUT_CLKCMU_FSYS2_BUS, "dout_clkcmu_fsys2_bus", 700 "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4), 701 DIV(DOUT_CLKCMU_FSYS2_UFS_EMBD, "dout_clkcmu_fsys2_ufs_embd", 702 "gout_clkcmu_fsys2_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD, 703 0, 3), 704 DIV(DOUT_CLKCMU_FSYS2_ETHERNET, "dout_clkcmu_fsys2_ethernet", 705 "gout_clkcmu_fsys2_ethernet", CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET, 706 0, 3), 707 708 /* G2D */ 709 DIV(DOUT_CLKCMU_G2D_G2D, "dout_clkcmu_g2d_g2d", "gout_clkcmu_g2d_g2d", 710 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), 711 DIV(DOUT_CLKCMU_G2D_MSCL, "dout_clkcmu_g2d_mscl", 712 "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), 713 714 /* G3D0 */ 715 DIV(DOUT_CLKCMU_G3D00_SWITCH, "dout_clkcmu_g3d00_switch", 716 "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3), 717 DIV(DOUT_CLKCMU_G3D01_SWITCH, "dout_clkcmu_g3d01_switch", 718 "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3), 719 720 /* G3D1 */ 721 DIV(DOUT_CLKCMU_G3D1_SWITCH, "dout_clkcmu_g3d1_switch", 722 "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3), 723 724 /* ISPB */ 725 DIV(DOUT_CLKCMU_ISPB_BUS, "dout_clkcmu_ispb_bus", 726 "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4), 727 728 /* MFC */ 729 DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", "gout_clkcmu_mfc_mfc", 730 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), 731 DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", "gout_clkcmu_mfc_wfd", 732 CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4), 733 734 /* MIF */ 735 DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp", 736 "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), 737 738 /* NPU */ 739 DIV(DOUT_CLKCMU_NPU_BUS, "dout_clkcmu_npu_bus", "gout_clkcmu_npu_bus", 740 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4), 741 742 /* PERIC0 */ 743 DIV(DOUT_CLKCMU_PERIC0_BUS, "dout_clkcmu_peric0_bus", 744 "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), 745 DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip", 746 "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), 747 748 /* PERIC1 */ 749 DIV(DOUT_CLKCMU_PERIC1_BUS, "dout_clkcmu_peric1_bus", 750 "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), 751 DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip", 752 "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), 753 754 /* PERIS */ 755 DIV(DOUT_CLKCMU_PERIS_BUS, "dout_clkcmu_peris_bus", 756 "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4), 757}; 758 759static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { 760 FFACTOR(DOUT_CLKCMU_FSYS0_PCIE, "dout_clkcmu_fsys0_pcie", 761 "gout_clkcmu_fsys0_pcie", 1, 4, 0), 762}; 763 764static const struct samsung_gate_clock top_gate_clks[] __initconst = { 765 /* BOOST */ 766 GATE(GOUT_CLKCMU_CMU_BOOST, "gout_clkcmu_cmu_boost", 767 "mout_clkcmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 768 21, 0, 0), 769 770 GATE(GOUT_CLKCMU_CPUCL0_BOOST, "gout_clkcmu_cpucl0_boost", 771 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0), 772 GATE(GOUT_CLKCMU_CPUCL1_BOOST, "gout_clkcmu_cpucl1_boost", 773 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0), 774 GATE(GOUT_CLKCMU_CORE_BOOST, "gout_clkcmu_core_boost", 775 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0), 776 GATE(GOUT_CLKCMU_BUSC_BOOST, "gout_clkcmu_busc_boost", 777 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0), 778 779 GATE(GOUT_CLKCMU_BUSMC_BOOST, "gout_clkcmu_busmc_boost", 780 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0), 781 GATE(GOUT_CLKCMU_MIF_BOOST, "gout_clkcmu_mif_boost", "dout_cmu_boost", 782 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0), 783 784 /* ACC */ 785 GATE(GOUT_CLKCMU_ACC_BUS, "gout_clkcmu_acc_bus", "mout_clkcmu_acc_bus", 786 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0), 787 788 /* APM */ 789 GATE(GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", "mout_clkcmu_apm_bus", 790 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0), 791 792 /* AUD */ 793 GATE(GOUT_CLKCMU_AUD_CPU, "gout_clkcmu_aud_cpu", "mout_clkcmu_aud_cpu", 794 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0), 795 GATE(GOUT_CLKCMU_AUD_BUS, "gout_clkcmu_aud_bus", "mout_clkcmu_aud_bus", 796 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0), 797 798 /* BUSC */ 799 GATE(GOUT_CLKCMU_BUSC_BUS, "gout_clkcmu_busc_bus", 800 "mout_clkcmu_busc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21, 801 CLK_IS_CRITICAL, 0), 802 803 /* BUSMC */ 804 GATE(GOUT_CLKCMU_BUSMC_BUS, "gout_clkcmu_busmc_bus", 805 "mout_clkcmu_busmc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21, 806 CLK_IS_CRITICAL, 0), 807 808 /* CORE */ 809 GATE(GOUT_CLKCMU_CORE_BUS, "gout_clkcmu_core_bus", 810 "mout_clkcmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 811 21, 0, 0), 812 813 /* CPUCL0 */ 814 GATE(GOUT_CLKCMU_CPUCL0_SWITCH, "gout_clkcmu_cpucl0_switch", 815 "mout_clkcmu_cpucl0_switch", 816 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0), 817 GATE(GOUT_CLKCMU_CPUCL0_CLUSTER, "gout_clkcmu_cpucl0_cluster", 818 "mout_clkcmu_cpucl0_cluster", 819 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0), 820 821 /* CPUCL1 */ 822 GATE(GOUT_CLKCMU_CPUCL1_SWITCH, "gout_clkcmu_cpucl1_switch", 823 "mout_clkcmu_cpucl1_switch", 824 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0), 825 GATE(GOUT_CLKCMU_CPUCL1_CLUSTER, "gout_clkcmu_cpucl1_cluster", 826 "mout_clkcmu_cpucl1_cluster", 827 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0), 828 829 /* DPTX */ 830 GATE(GOUT_CLKCMU_DPTX_BUS, "gout_clkcmu_dptx_bus", 831 "mout_clkcmu_dptx_bus", CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS, 832 21, 0, 0), 833 GATE(GOUT_CLKCMU_DPTX_DPGTC, "gout_clkcmu_dptx_dpgtc", 834 "mout_clkcmu_dptx_dpgtc", CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC, 835 21, 0, 0), 836 837 /* DPUM */ 838 GATE(GOUT_CLKCMU_DPUM_BUS, "gout_clkcmu_dpum_bus", 839 "mout_clkcmu_dpum_bus", CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS, 840 21, 0, 0), 841 842 /* DPUS */ 843 GATE(GOUT_CLKCMU_DPUS0_BUS, "gout_clkcmu_dpus0_bus", 844 "mout_clkcmu_dpus0_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS, 845 21, 0, 0), 846 GATE(GOUT_CLKCMU_DPUS1_BUS, "gout_clkcmu_dpus1_bus", 847 "mout_clkcmu_dpus1_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS, 848 21, 0, 0), 849 850 /* FSYS0 */ 851 GATE(GOUT_CLKCMU_FSYS0_BUS, "gout_clkcmu_fsys0_bus", 852 "mout_clkcmu_fsys0_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS, 853 21, 0, 0), 854 GATE(GOUT_CLKCMU_FSYS0_PCIE, "gout_clkcmu_fsys0_pcie", 855 "mout_clkcmu_fsys0_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE, 856 21, 0, 0), 857 858 /* FSYS1 */ 859 GATE(GOUT_CLKCMU_FSYS1_BUS, "gout_clkcmu_fsys1_bus", 860 "mout_clkcmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS, 861 21, 0, 0), 862 GATE(GOUT_CLKCMU_FSYS1_USBDRD, "gout_clkcmu_fsys1_usbdrd", 863 "mout_clkcmu_fsys1_usbdrd", CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD, 864 21, 0, 0), 865 GATE(GOUT_CLKCMU_FSYS1_MMC_CARD, "gout_clkcmu_fsys1_mmc_card", 866 "mout_clkcmu_fsys1_mmc_card", 867 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0), 868 869 /* FSYS2 */ 870 GATE(GOUT_CLKCMU_FSYS2_BUS, "gout_clkcmu_fsys2_bus", 871 "mout_clkcmu_fsys2_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS, 872 21, 0, 0), 873 GATE(GOUT_CLKCMU_FSYS2_UFS_EMBD, "gout_clkcmu_fsys2_ufs_embd", 874 "mout_clkcmu_fsys2_ufs_embd", 875 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0), 876 GATE(GOUT_CLKCMU_FSYS2_ETHERNET, "gout_clkcmu_fsys2_ethernet", 877 "mout_clkcmu_fsys2_ethernet", 878 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0), 879 880 /* G2D */ 881 GATE(GOUT_CLKCMU_G2D_G2D, "gout_clkcmu_g2d_g2d", 882 "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), 883 GATE(GOUT_CLKCMU_G2D_MSCL, "gout_clkcmu_g2d_mscl", 884 "mout_clkcmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 885 21, 0, 0), 886 887 /* G3D0 */ 888 GATE(GOUT_CLKCMU_G3D00_SWITCH, "gout_clkcmu_g3d00_switch", 889 "mout_clkcmu_g3d00_switch", CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH, 890 21, 0, 0), 891 GATE(GOUT_CLKCMU_G3D01_SWITCH, "gout_clkcmu_g3d01_switch", 892 "mout_clkcmu_g3d01_switch", CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH, 893 21, 0, 0), 894 895 /* G3D1 */ 896 GATE(GOUT_CLKCMU_G3D1_SWITCH, "gout_clkcmu_g3d1_switch", 897 "mout_clkcmu_g3d1_switch", CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH, 898 21, 0, 0), 899 900 /* ISPB */ 901 GATE(GOUT_CLKCMU_ISPB_BUS, "gout_clkcmu_ispb_bus", 902 "mout_clkcmu_ispb_bus", CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS, 903 21, 0, 0), 904 905 /* MFC */ 906 GATE(GOUT_CLKCMU_MFC_MFC, "gout_clkcmu_mfc_mfc", "mout_clkcmu_mfc_mfc", 907 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), 908 GATE(GOUT_CLKCMU_MFC_WFD, "gout_clkcmu_mfc_wfd", "mout_clkcmu_mfc_wfd", 909 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0), 910 911 /* MIF */ 912 GATE(GOUT_CLKCMU_MIF_SWITCH, "gout_clkcmu_mif_switch", 913 "mout_clkcmu_mif_switch", CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH, 914 21, CLK_IGNORE_UNUSED, 0), 915 GATE(GOUT_CLKCMU_MIF_BUSP, "gout_clkcmu_mif_busp", 916 "mout_clkcmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 917 21, CLK_IGNORE_UNUSED, 0), 918 919 /* NPU */ 920 GATE(GOUT_CLKCMU_NPU_BUS, "gout_clkcmu_npu_bus", "mout_clkcmu_npu_bus", 921 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0), 922 923 /* PERIC0 */ 924 GATE(GOUT_CLKCMU_PERIC0_BUS, "gout_clkcmu_peric0_bus", 925 "mout_clkcmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 926 21, 0, 0), 927 GATE(GOUT_CLKCMU_PERIC0_IP, "gout_clkcmu_peric0_ip", 928 "mout_clkcmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 929 21, 0, 0), 930 931 /* PERIC1 */ 932 GATE(GOUT_CLKCMU_PERIC1_BUS, "gout_clkcmu_peric1_bus", 933 "mout_clkcmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 934 21, 0, 0), 935 GATE(GOUT_CLKCMU_PERIC1_IP, "gout_clkcmu_peric1_ip", 936 "mout_clkcmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 937 21, 0, 0), 938 939 /* PERIS */ 940 GATE(GOUT_CLKCMU_PERIS_BUS, "gout_clkcmu_peris_bus", 941 "mout_clkcmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS, 942 21, CLK_IGNORE_UNUSED, 0), 943}; 944 945static const struct samsung_cmu_info top_cmu_info __initconst = { 946 .pll_clks = top_pll_clks, 947 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 948 .mux_clks = top_mux_clks, 949 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 950 .div_clks = top_div_clks, 951 .nr_div_clks = ARRAY_SIZE(top_div_clks), 952 .fixed_factor_clks = top_fixed_factor_clks, 953 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 954 .gate_clks = top_gate_clks, 955 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 956 .nr_clk_ids = CLKS_NR_TOP, 957 .clk_regs = top_clk_regs, 958 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 959}; 960 961static void __init exynosautov9_cmu_top_init(struct device_node *np) 962{ 963 exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 964} 965 966/* Register CMU_TOP early, as it's a dependency for other early domains */ 967CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top", 968 exynosautov9_cmu_top_init); 969 970/* ---- CMU_BUSMC ---------------------------------------------------------- */ 971 972/* Register Offset definitions for CMU_BUSMC (0x1b200000) */ 973#define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER 0x0600 974#define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP 0x1800 975#define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK 0x2078 976#define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2080 977 978static const unsigned long busmc_clk_regs[] __initconst = { 979 PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER, 980 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 981 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK, 982 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK, 983}; 984 985/* List of parent clocks for Muxes in CMU_BUSMC */ 986PNAME(mout_busmc_bus_user_p) = { "oscclk", "dout_clkcmu_busmc_bus" }; 987 988static const struct samsung_mux_clock busmc_mux_clks[] __initconst = { 989 MUX(CLK_MOUT_BUSMC_BUS_USER, "mout_busmc_bus_user", 990 mout_busmc_bus_user_p, PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER, 4, 1), 991}; 992 993static const struct samsung_div_clock busmc_div_clks[] __initconst = { 994 DIV(CLK_DOUT_BUSMC_BUSP, "dout_busmc_busp", "mout_busmc_bus_user", 995 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3), 996}; 997 998static const struct samsung_gate_clock busmc_gate_clks[] __initconst = { 999 GATE(CLK_GOUT_BUSMC_PDMA0_PCLK, "gout_busmc_pdma0_pclk", 1000 "dout_busmc_busp", 1001 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK, 21, 1002 0, 0), 1003 GATE(CLK_GOUT_BUSMC_SPDMA_PCLK, "gout_busmc_spdma_pclk", 1004 "dout_busmc_busp", 1005 CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK, 21, 1006 0, 0), 1007}; 1008 1009static const struct samsung_cmu_info busmc_cmu_info __initconst = { 1010 .mux_clks = busmc_mux_clks, 1011 .nr_mux_clks = ARRAY_SIZE(busmc_mux_clks), 1012 .div_clks = busmc_div_clks, 1013 .nr_div_clks = ARRAY_SIZE(busmc_div_clks), 1014 .gate_clks = busmc_gate_clks, 1015 .nr_gate_clks = ARRAY_SIZE(busmc_gate_clks), 1016 .nr_clk_ids = CLKS_NR_BUSMC, 1017 .clk_regs = busmc_clk_regs, 1018 .nr_clk_regs = ARRAY_SIZE(busmc_clk_regs), 1019 .clk_name = "dout_clkcmu_busmc_bus", 1020}; 1021 1022/* ---- CMU_CORE ----------------------------------------------------------- */ 1023 1024/* Register Offset definitions for CMU_CORE (0x1b030000) */ 1025#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 1026#define CLK_CON_MUX_MUX_CORE_CMUREF 0x1000 1027#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 1028#define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK 0x2000 1029#define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK 0x2004 1030#define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK 0x2008 1031 1032static const unsigned long core_clk_regs[] __initconst = { 1033 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 1034 CLK_CON_MUX_MUX_CORE_CMUREF, 1035 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 1036 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 1037 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 1038 CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 1039}; 1040 1041/* List of parent clocks for Muxes in CMU_CORE */ 1042PNAME(mout_core_bus_user_p) = { "oscclk", "dout_clkcmu_core_bus" }; 1043 1044static const struct samsung_mux_clock core_mux_clks[] __initconst = { 1045 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 1046 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 1047}; 1048 1049static const struct samsung_div_clock core_div_clks[] __initconst = { 1050 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 1051 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3), 1052}; 1053 1054static const struct samsung_gate_clock core_gate_clks[] __initconst = { 1055 GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_core_bus_user", 1056 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 21, 1057 CLK_IS_CRITICAL, 0), 1058 GATE(CLK_GOUT_CORE_CCI_PCLK, "gout_core_cci_pclk", "dout_core_busp", 1059 CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 21, 1060 CLK_IS_CRITICAL, 0), 1061 GATE(CLK_GOUT_CORE_CMU_CORE_PCLK, "gout_core_cmu_core_pclk", 1062 "dout_core_busp", 1063 CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 21, 1064 CLK_IS_CRITICAL, 0), 1065}; 1066 1067static const struct samsung_cmu_info core_cmu_info __initconst = { 1068 .mux_clks = core_mux_clks, 1069 .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 1070 .div_clks = core_div_clks, 1071 .nr_div_clks = ARRAY_SIZE(core_div_clks), 1072 .gate_clks = core_gate_clks, 1073 .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 1074 .nr_clk_ids = CLKS_NR_CORE, 1075 .clk_regs = core_clk_regs, 1076 .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 1077 .clk_name = "dout_clkcmu_core_bus", 1078}; 1079 1080/* ---- CMU_DPUM ---------------------------------------------------------- */ 1081 1082/* Register Offset definitions for CMU_DPUM (0x18c00000) */ 1083#define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER 0x0600 1084#define CLK_CON_DIV_DIV_CLK_DPUM_BUSP 0x1800 1085#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON 0x202c 1086#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA 0x2030 1087#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP 0x2034 1088#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1 0x207c 1089#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1 0x2084 1090#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1 0x208c 1091#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1 0x2094 1092 1093static const unsigned long dpum_clk_regs[] __initconst = { 1094 PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER, 1095 CLK_CON_DIV_DIV_CLK_DPUM_BUSP, 1096 CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON, 1097 CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA, 1098 CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP, 1099 CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1, 1100 CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1, 1101 CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1, 1102 CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1, 1103}; 1104 1105PNAME(mout_dpum_bus_user_p) = { "oscclk", "dout_clkcmu_dpum_bus" }; 1106 1107static const struct samsung_mux_clock dpum_mux_clks[] __initconst = { 1108 MUX(CLK_MOUT_DPUM_BUS_USER, "mout_dpum_bus_user", 1109 mout_dpum_bus_user_p, PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER, 4, 1), 1110}; 1111 1112static const struct samsung_div_clock dpum_div_clks[] __initconst = { 1113 DIV(CLK_DOUT_DPUM_BUSP, "dout_dpum_busp", "mout_dpum_bus_user", 1114 CLK_CON_DIV_DIV_CLK_DPUM_BUSP, 0, 3), 1115}; 1116 1117static const struct samsung_gate_clock dpum_gate_clks[] __initconst = { 1118 GATE(CLK_GOUT_DPUM_ACLK_DECON, "gout_dpum_decon_aclk", 1119 "mout_dpum_bus_user", 1120 CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON, 21, 1121 0, 0), 1122 GATE(CLK_GOUT_DPUM_ACLK_DMA, "gout_dpum_dma_aclk", "mout_dpum_bus_user", 1123 CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA, 21, 1124 0, 0), 1125 GATE(CLK_GOUT_DPUM_ACLK_DPP, "gout_dpum_dpp_aclk", "mout_dpum_bus_user", 1126 CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP, 21, 1127 0, 0), 1128 GATE(CLK_GOUT_DPUM_SYSMMU_D0_CLK, "gout_dpum_sysmmu_d0_clk", 1129 "mout_dpum_bus_user", 1130 CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1, 21, 1131 0, 0), 1132 GATE(CLK_GOUT_DPUM_SYSMMU_D1_CLK, "gout_dpum_sysmmu_d1_clk", 1133 "mout_dpum_bus_user", 1134 CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1, 21, 1135 0, 0), 1136 GATE(CLK_GOUT_DPUM_SYSMMU_D2_CLK, "gout_dpum_sysmmu_d2_clk", 1137 "mout_dpum_bus_user", 1138 CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1, 21, 1139 0, 0), 1140 GATE(CLK_GOUT_DPUM_SYSMMU_D3_CLK, "gout_dpum_sysmmu_d3_clk", 1141 "mout_dpum_bus_user", 1142 CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1, 21, 1143 0, 0), 1144}; 1145 1146static const struct samsung_cmu_info dpum_cmu_info __initconst = { 1147 .mux_clks = dpum_mux_clks, 1148 .nr_mux_clks = ARRAY_SIZE(dpum_mux_clks), 1149 .div_clks = dpum_div_clks, 1150 .nr_div_clks = ARRAY_SIZE(dpum_div_clks), 1151 .gate_clks = dpum_gate_clks, 1152 .nr_gate_clks = ARRAY_SIZE(dpum_gate_clks), 1153 .nr_clk_ids = CLKS_NR_DPUM, 1154 .clk_regs = dpum_clk_regs, 1155 .nr_clk_regs = ARRAY_SIZE(dpum_clk_regs), 1156 .clk_name = "bus", 1157}; 1158 1159/* ---- CMU_FSYS0 ---------------------------------------------------------- */ 1160 1161/* Register Offset definitions for CMU_FSYS2 (0x17700000) */ 1162#define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600 1163#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610 1164#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000 1165 1166#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004 1167#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008 1168#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c 1169#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010 1170#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014 1171#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018 1172 1173#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c 1174#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060 1175#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064 1176#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c 1177#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070 1178#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074 1179#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c 1180 1181#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084 1182#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088 1183#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c 1184#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094 1185#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098 1186#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c 1187#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4 1188 1189#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac 1190#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0 1191#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4 1192#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc 1193#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0 1194#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4 1195#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc 1196 1197#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4 1198#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8 1199#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc 1200#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0 1201#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4 1202#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8 1203 1204 1205static const unsigned long fsys0_clk_regs[] __initconst = { 1206 PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 1207 PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 1208 CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 1209 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN, 1210 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN, 1211 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN, 1212 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN, 1213 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN, 1214 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN, 1215 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK, 1216 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK, 1217 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK, 1218 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK, 1219 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK, 1220 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK, 1221 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK, 1222 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK, 1223 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK, 1224 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK, 1225 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK, 1226 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK, 1227 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK, 1228 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK, 1229 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK, 1230 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK, 1231 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK, 1232 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK, 1233 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK, 1234 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK, 1235 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK, 1236 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK, 1237 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK, 1238 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK, 1239 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK, 1240 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK, 1241 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK, 1242}; 1243 1244/* List of parent clocks for Muxes in CMU_FSYS0 */ 1245PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" }; 1246PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" }; 1247 1248static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { 1249 MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user", 1250 mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1), 1251 MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user", 1252 mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1), 1253}; 1254 1255static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { 1256 GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk", 1257 "mout_fsys0_bus_user", 1258 CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 1259 21, CLK_IGNORE_UNUSED, 0), 1260 1261 /* Gen3 2L0 */ 1262 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK, 1263 "gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user", 1264 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN, 1265 21, 0, 0), 1266 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK, 1267 "gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user", 1268 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN, 1269 21, 0, 0), 1270 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK, 1271 "gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user", 1272 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK, 1273 21, 0, 0), 1274 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK, 1275 "gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user", 1276 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK, 1277 21, 0, 0), 1278 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK, 1279 "gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user", 1280 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK, 1281 21, 0, 0), 1282 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK, 1283 "gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user", 1284 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK, 1285 21, 0, 0), 1286 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK, 1287 "gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user", 1288 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK, 1289 21, 0, 0), 1290 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK, 1291 "gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user", 1292 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK, 1293 21, 0, 0), 1294 GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK, 1295 "gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user", 1296 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK, 1297 21, 0, 0), 1298 GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK, 1299 "gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user", 1300 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK, 1301 21, 0, 0), 1302 1303 /* Gen3 2L1 */ 1304 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK, 1305 "gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user", 1306 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN, 1307 21, 0, 0), 1308 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK, 1309 "gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user", 1310 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN, 1311 21, 0, 0), 1312 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK, 1313 "gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user", 1314 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK, 1315 21, 0, 0), 1316 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK, 1317 "gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user", 1318 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK, 1319 21, 0, 0), 1320 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK, 1321 "gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user", 1322 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK, 1323 21, 0, 0), 1324 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK, 1325 "gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user", 1326 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK, 1327 21, 0, 0), 1328 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK, 1329 "gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user", 1330 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK, 1331 21, 0, 0), 1332 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK, 1333 "gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user", 1334 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK, 1335 21, 0, 0), 1336 GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK, 1337 "gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user", 1338 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK, 1339 21, 0, 0), 1340 GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK, 1341 "gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user", 1342 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK, 1343 21, 0, 0), 1344 1345 /* Gen3 4L */ 1346 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK, 1347 "gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user", 1348 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN, 1349 21, 0, 0), 1350 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK, 1351 "gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user", 1352 CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN, 1353 21, 0, 0), 1354 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK, 1355 "gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user", 1356 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK, 1357 21, 0, 0), 1358 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK, 1359 "gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user", 1360 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK, 1361 21, 0, 0), 1362 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK, 1363 "gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user", 1364 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK, 1365 21, 0, 0), 1366 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK, 1367 "gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user", 1368 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK, 1369 21, 0, 0), 1370 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK, 1371 "gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user", 1372 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK, 1373 21, 0, 0), 1374 GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK, 1375 "gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user", 1376 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK, 1377 21, 0, 0), 1378 GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK, 1379 "gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user", 1380 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK, 1381 21, 0, 0), 1382 GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK, 1383 "gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user", 1384 CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK, 1385 21, 0, 0), 1386}; 1387 1388static const struct samsung_cmu_info fsys0_cmu_info __initconst = { 1389 .mux_clks = fsys0_mux_clks, 1390 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 1391 .gate_clks = fsys0_gate_clks, 1392 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 1393 .nr_clk_ids = CLKS_NR_FSYS0, 1394 .clk_regs = fsys0_clk_regs, 1395 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 1396 .clk_name = "dout_clkcmu_fsys0_bus", 1397}; 1398 1399/* ---- CMU_FSYS1 ---------------------------------------------------------- */ 1400 1401/* Register Offset definitions for CMU_FSYS1 (0x17040000) */ 1402#define PLL_LOCKTIME_PLL_MMC 0x0000 1403#define PLL_CON0_PLL_MMC 0x0100 1404#define PLL_CON3_PLL_MMC 0x010c 1405#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600 1406#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610 1407#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620 1408 1409#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000 1410#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800 1411 1412#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018 1413#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c 1414#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028 1415 1416#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c 1417#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058 1418#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064 1419#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070 1420 1421#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074 1422#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078 1423#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c 1424#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080 1425 1426static const unsigned long fsys1_clk_regs[] __initconst = { 1427 PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 1428}; 1429 1430static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = { 1431 PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 1432 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 1433}; 1434 1435/* List of parent clocks for Muxes in CMU_FSYS1 */ 1436PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" }; 1437PNAME(mout_fsys1_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 1438PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" }; 1439PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" }; 1440PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user", 1441 "mout_fsys1_mmc_pll" }; 1442 1443static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { 1444 MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user", 1445 mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1), 1446 MUX(CLK_MOUT_FSYS1_MMC_PLL, "mout_fsys1_mmc_pll", mout_fsys1_mmc_pll_p, 1447 PLL_CON0_PLL_MMC, 4, 1), 1448 MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user", 1449 mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER, 1450 4, 1), 1451 MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user", 1452 mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER, 1453 4, 1), 1454 MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card", 1455 mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD, 1456 0, 1), 1457}; 1458 1459static const struct samsung_div_clock fsys1_div_clks[] __initconst = { 1460 DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card", 1461 "mout_fsys1_mmc_card", 1462 CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9), 1463}; 1464 1465static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { 1466 GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user", 1467 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 1468 21, CLK_IGNORE_UNUSED, 0), 1469 GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin", 1470 "dout_fsys1_mmc_card", 1471 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 1472 21, CLK_SET_RATE_PARENT, 0), 1473 GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk", 1474 "dout_fsys1_mmc_card", 1475 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK, 1476 21, 0, 0), 1477 GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk", 1478 "mout_fsys1_usbdrd_user", 1479 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40, 1480 21, 0, 0), 1481 GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk", 1482 "mout_fsys1_usbdrd_user", 1483 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40, 1484 21, 0, 0), 1485 GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk", 1486 "mout_fsys1_usbdrd_user", 1487 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40, 1488 21, 0, 0), 1489 GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk", 1490 "mout_fsys1_usbdrd_user", 1491 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40, 1492 21, 0, 0), 1493 GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk", 1494 "mout_fsys1_usbdrd_user", 1495 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK, 1496 21, 0, 0), 1497 GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk", 1498 "mout_fsys1_usbdrd_user", 1499 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK, 1500 21, 0, 0), 1501 GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk", 1502 "mout_fsys1_usbdrd_user", 1503 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK, 1504 21, 0, 0), 1505 GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk", 1506 "mout_fsys1_usbdrd_user", 1507 CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK, 1508 21, 0, 0), 1509}; 1510 1511static const struct samsung_cmu_info fsys1_cmu_info __initconst = { 1512 .pll_clks = fsys1_pll_clks, 1513 .nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks), 1514 .mux_clks = fsys1_mux_clks, 1515 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 1516 .div_clks = fsys1_div_clks, 1517 .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), 1518 .gate_clks = fsys1_gate_clks, 1519 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 1520 .nr_clk_ids = CLKS_NR_FSYS1, 1521 .clk_regs = fsys1_clk_regs, 1522 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 1523 .clk_name = "dout_clkcmu_fsys1_bus", 1524}; 1525 1526/* ---- CMU_FSYS2 ---------------------------------------------------------- */ 1527 1528/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */ 1529#define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0x0600 1530#define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620 1531#define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610 1532#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0x2098 1533#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c 1534#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0x20a4 1535#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8 1536 1537static const unsigned long fsys2_clk_regs[] __initconst = { 1538 PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 1539 PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 1540 PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 1541 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 1542 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO, 1543 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 1544 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO, 1545}; 1546 1547/* List of parent clocks for Muxes in CMU_FSYS2 */ 1548PNAME(mout_fsys2_bus_user_p) = { "oscclk", "dout_clkcmu_fsys2_bus" }; 1549PNAME(mout_fsys2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_fsys2_ufs_embd" }; 1550PNAME(mout_fsys2_ethernet_user_p) = { "oscclk", "dout_clkcmu_fsys2_ethernet" }; 1551 1552static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = { 1553 MUX(CLK_MOUT_FSYS2_BUS_USER, "mout_fsys2_bus_user", 1554 mout_fsys2_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 4, 1), 1555 MUX(CLK_MOUT_FSYS2_UFS_EMBD_USER, "mout_fsys2_ufs_embd_user", 1556 mout_fsys2_ufs_embd_user_p, 1557 PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 4, 1), 1558 MUX(CLK_MOUT_FSYS2_ETHERNET_USER, "mout_fsys2_ethernet_user", 1559 mout_fsys2_ethernet_user_p, 1560 PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 4, 1), 1561}; 1562 1563static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = { 1564 GATE(CLK_GOUT_FSYS2_UFS_EMBD0_ACLK, "gout_fsys2_ufs_embd0_aclk", 1565 "mout_fsys2_ufs_embd_user", 1566 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 21, 1567 0, 0), 1568 GATE(CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO, "gout_fsys2_ufs_embd0_unipro", 1569 "mout_fsys2_ufs_embd_user", 1570 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO, 1571 21, 0, 0), 1572 GATE(CLK_GOUT_FSYS2_UFS_EMBD1_ACLK, "gout_fsys2_ufs_embd1_aclk", 1573 "mout_fsys2_ufs_embd_user", 1574 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 21, 1575 0, 0), 1576 GATE(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO, "gout_fsys2_ufs_embd1_unipro", 1577 "mout_fsys2_ufs_embd_user", 1578 CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO, 1579 21, 0, 0), 1580}; 1581 1582static const struct samsung_cmu_info fsys2_cmu_info __initconst = { 1583 .mux_clks = fsys2_mux_clks, 1584 .nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks), 1585 .gate_clks = fsys2_gate_clks, 1586 .nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks), 1587 .nr_clk_ids = CLKS_NR_FSYS2, 1588 .clk_regs = fsys2_clk_regs, 1589 .nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs), 1590 .clk_name = "dout_clkcmu_fsys2_bus", 1591}; 1592 1593/* ---- CMU_PERIC0 --------------------------------------------------------- */ 1594 1595/* Register Offset definitions for CMU_PERIC0 (0x10200000) */ 1596#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 1597#define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610 1598#define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000 1599#define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004 1600#define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008 1601#define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c 1602#define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010 1603#define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014 1604#define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018 1605#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800 1606#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804 1607#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808 1608#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c 1609#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810 1610#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814 1611#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818 1612#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014 1613#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018 1614#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024 1615#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028 1616#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c 1617#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030 1618#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034 1619#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038 1620#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c 1621#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040 1622#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c 1623#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020 1624#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044 1625#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048 1626#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058 1627#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c 1628#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060 1629#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064 1630#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068 1631#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c 1632#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070 1633#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074 1634#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c 1635#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050 1636 1637static const unsigned long peric0_clk_regs[] __initconst = { 1638 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 1639 PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 1640 CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 1641 CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 1642 CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 1643 CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 1644 CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 1645 CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 1646 CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 1647 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 1648 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 1649 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 1650 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 1651 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 1652 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 1653 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 1654 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 1655 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 1656 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 1657 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 1658 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 1659 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 1660 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 1661 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 1662 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 1663 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 1664 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 1665 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 1666 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 1667 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 1668 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 1669 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 1670 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 1671 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 1672 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 1673 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 1674 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 1675 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 1676 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 1677 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 1678}; 1679 1680/* List of parent clocks for Muxes in CMU_PERIC0 */ 1681PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" }; 1682PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" }; 1683PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" }; 1684 1685static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { 1686 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", 1687 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), 1688 MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user", 1689 mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1), 1690 /* USI00 ~ USI05 */ 1691 MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi", 1692 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1), 1693 MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi", 1694 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1), 1695 MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi", 1696 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1), 1697 MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi", 1698 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1), 1699 MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi", 1700 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1), 1701 MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi", 1702 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1), 1703 /* USI_I2C */ 1704 MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c", 1705 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1), 1706}; 1707 1708static const struct samsung_div_clock peric0_div_clks[] __initconst = { 1709 /* USI00 ~ USI05 */ 1710 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi", 1711 "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 1712 0, 4), 1713 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi", 1714 "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 1715 0, 4), 1716 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi", 1717 "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 1718 0, 4), 1719 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi", 1720 "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 1721 0, 4), 1722 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi", 1723 "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 1724 0, 4), 1725 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi", 1726 "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 1727 0, 4), 1728 /* USI_I2C */ 1729 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c", 1730 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4), 1731}; 1732 1733static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { 1734 /* IPCLK */ 1735 GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0", 1736 "dout_peric0_usi00_usi", 1737 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 1738 21, 0, 0), 1739 GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1", 1740 "dout_peric0_usi_i2c", 1741 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 1742 21, 0, 0), 1743 GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2", 1744 "dout_peric0_usi01_usi", 1745 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 1746 21, 0, 0), 1747 GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3", 1748 "dout_peric0_usi_i2c", 1749 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 1750 21, 0, 0), 1751 GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4", 1752 "dout_peric0_usi02_usi", 1753 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 1754 21, 0, 0), 1755 GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5", 1756 "dout_peric0_usi_i2c", 1757 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 1758 21, 0, 0), 1759 GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6", 1760 "dout_peric0_usi03_usi", 1761 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 1762 21, 0, 0), 1763 GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7", 1764 "dout_peric0_usi_i2c", 1765 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 1766 21, 0, 0), 1767 GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8", 1768 "dout_peric0_usi04_usi", 1769 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 1770 21, 0, 0), 1771 GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9", 1772 "dout_peric0_usi_i2c", 1773 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 1774 21, 0, 0), 1775 GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10", 1776 "dout_peric0_usi05_usi", 1777 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 1778 21, 0, 0), 1779 GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11", 1780 "dout_peric0_usi_i2c", 1781 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 1782 21, 0, 0), 1783 1784 /* PCLK */ 1785 GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0", 1786 "mout_peric0_bus_user", 1787 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 1788 21, 0, 0), 1789 GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1", 1790 "mout_peric0_bus_user", 1791 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 1792 21, 0, 0), 1793 GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2", 1794 "mout_peric0_bus_user", 1795 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 1796 21, 0, 0), 1797 GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3", 1798 "mout_peric0_bus_user", 1799 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 1800 21, 0, 0), 1801 GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4", 1802 "mout_peric0_bus_user", 1803 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 1804 21, 0, 0), 1805 GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5", 1806 "mout_peric0_bus_user", 1807 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 1808 21, 0, 0), 1809 GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6", 1810 "mout_peric0_bus_user", 1811 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 1812 21, 0, 0), 1813 GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7", 1814 "mout_peric0_bus_user", 1815 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 1816 21, 0, 0), 1817 GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8", 1818 "mout_peric0_bus_user", 1819 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 1820 21, 0, 0), 1821 GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9", 1822 "mout_peric0_bus_user", 1823 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 1824 21, 0, 0), 1825 GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10", 1826 "mout_peric0_bus_user", 1827 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 1828 21, 0, 0), 1829 GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11", 1830 "mout_peric0_bus_user", 1831 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 1832 21, 0, 0), 1833}; 1834 1835static const struct samsung_cmu_info peric0_cmu_info __initconst = { 1836 .mux_clks = peric0_mux_clks, 1837 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 1838 .div_clks = peric0_div_clks, 1839 .nr_div_clks = ARRAY_SIZE(peric0_div_clks), 1840 .gate_clks = peric0_gate_clks, 1841 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 1842 .nr_clk_ids = CLKS_NR_PERIC0, 1843 .clk_regs = peric0_clk_regs, 1844 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 1845 .clk_name = "dout_clkcmu_peric0_bus", 1846}; 1847 1848/* ---- CMU_PERIC1 --------------------------------------------------------- */ 1849 1850/* Register Offset definitions for CMU_PERIC1 (0x10800000) */ 1851#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 1852#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x0610 1853#define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0x1000 1854#define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0x1004 1855#define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0x1008 1856#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x100c 1857#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1010 1858#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x1014 1859#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1018 1860#define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1800 1861#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1804 1862#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x1808 1863#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x180c 1864#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1810 1865#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1814 1866#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1818 1867#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0x2014 1868#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2018 1869#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024 1870#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028 1871#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c 1872#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030 1873#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034 1874#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0x2038 1875#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x203c 1876#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0x2040 1877#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x201c 1878#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020 1879#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044 1880#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048 1881#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054 1882#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058 1883#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c 1884#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060 1885#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064 1886#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068 1887#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c 1888#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070 1889#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c 1890#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050 1891 1892static const unsigned long peric1_clk_regs[] __initconst = { 1893 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 1894 PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 1895 CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 1896 CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 1897 CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 1898 CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 1899 CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 1900 CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 1901 CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 1902 CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, 1903 CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, 1904 CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, 1905 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 1906 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 1907 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 1908 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 1909 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0, 1910 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 1911 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 1912 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 1913 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 1914 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 1915 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 1916 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7, 1917 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 1918 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9, 1919 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10, 1920 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11, 1921 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0, 1922 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 1923 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 1924 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 1925 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 1926 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 1927 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 1928 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7, 1929 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 1930 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9, 1931 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10, 1932 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11, 1933}; 1934 1935/* List of parent clocks for Muxes in CMU_PERIC1 */ 1936PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_clkcmu_peric1_bus" }; 1937PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" }; 1938PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" }; 1939 1940static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { 1941 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", 1942 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), 1943 MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user", 1944 mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1), 1945 /* USI06 ~ USI11 */ 1946 MUX(CLK_MOUT_PERIC1_USI06_USI, "mout_peric1_usi06_usi", 1947 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1), 1948 MUX(CLK_MOUT_PERIC1_USI07_USI, "mout_peric1_usi07_usi", 1949 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1), 1950 MUX(CLK_MOUT_PERIC1_USI08_USI, "mout_peric1_usi08_usi", 1951 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1), 1952 MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi", 1953 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1), 1954 MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi", 1955 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1), 1956 MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi", 1957 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1), 1958 /* USI_I2C */ 1959 MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c", 1960 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1), 1961}; 1962 1963static const struct samsung_div_clock peric1_div_clks[] __initconst = { 1964 /* USI06 ~ USI11 */ 1965 DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi", 1966 "mout_peric1_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, 1967 0, 4), 1968 DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi", 1969 "mout_peric1_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, 1970 0, 4), 1971 DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi", 1972 "mout_peric1_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, 1973 0, 4), 1974 DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi", 1975 "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 1976 0, 4), 1977 DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi", 1978 "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 1979 0, 4), 1980 DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi", 1981 "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 1982 0, 4), 1983 /* USI_I2C */ 1984 DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c", 1985 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4), 1986}; 1987 1988static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { 1989 /* IPCLK */ 1990 GATE(CLK_GOUT_PERIC1_IPCLK_0, "gout_peric1_ipclk_0", 1991 "dout_peric1_usi06_usi", 1992 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0, 1993 21, 0, 0), 1994 GATE(CLK_GOUT_PERIC1_IPCLK_1, "gout_peric1_ipclk_1", 1995 "dout_peric1_usi_i2c", 1996 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 1997 21, 0, 0), 1998 GATE(CLK_GOUT_PERIC1_IPCLK_2, "gout_peric1_ipclk_2", 1999 "dout_peric1_usi07_usi", 2000 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 2001 21, 0, 0), 2002 GATE(CLK_GOUT_PERIC1_IPCLK_3, "gout_peric1_ipclk_3", 2003 "dout_peric1_usi_i2c", 2004 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 2005 21, 0, 0), 2006 GATE(CLK_GOUT_PERIC1_IPCLK_4, "gout_peric1_ipclk_4", 2007 "dout_peric1_usi08_usi", 2008 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 2009 21, 0, 0), 2010 GATE(CLK_GOUT_PERIC1_IPCLK_5, "gout_peric1_ipclk_5", 2011 "dout_peric1_usi_i2c", 2012 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 2013 21, 0, 0), 2014 GATE(CLK_GOUT_PERIC1_IPCLK_6, "gout_peric1_ipclk_6", 2015 "dout_peric1_usi09_usi", 2016 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 2017 21, 0, 0), 2018 GATE(CLK_GOUT_PERIC1_IPCLK_7, "gout_peric1_ipclk_7", 2019 "dout_peric1_usi_i2c", 2020 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7, 2021 21, 0, 0), 2022 GATE(CLK_GOUT_PERIC1_IPCLK_8, "gout_peric1_ipclk_8", 2023 "dout_peric1_usi10_usi", 2024 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 2025 21, 0, 0), 2026 GATE(CLK_GOUT_PERIC1_IPCLK_9, "gout_peric1_ipclk_9", 2027 "dout_peric1_usi_i2c", 2028 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9, 2029 21, 0, 0), 2030 GATE(CLK_GOUT_PERIC1_IPCLK_10, "gout_peric1_ipclk_10", 2031 "dout_peric1_usi11_usi", 2032 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10, 2033 21, 0, 0), 2034 GATE(CLK_GOUT_PERIC1_IPCLK_11, "gout_peric1_ipclk_11", 2035 "dout_peric1_usi_i2c", 2036 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11, 2037 21, 0, 0), 2038 2039 /* PCLK */ 2040 GATE(CLK_GOUT_PERIC1_PCLK_0, "gout_peric1_pclk_0", 2041 "mout_peric1_bus_user", 2042 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0, 2043 21, 0, 0), 2044 GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1", 2045 "mout_peric1_bus_user", 2046 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 2047 21, 0, 0), 2048 GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2", 2049 "mout_peric1_bus_user", 2050 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 2051 21, 0, 0), 2052 GATE(CLK_GOUT_PERIC1_PCLK_3, "gout_peric1_pclk_3", 2053 "mout_peric1_bus_user", 2054 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 2055 21, 0, 0), 2056 GATE(CLK_GOUT_PERIC1_PCLK_4, "gout_peric1_pclk_4", 2057 "mout_peric1_bus_user", 2058 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 2059 21, 0, 0), 2060 GATE(CLK_GOUT_PERIC1_PCLK_5, "gout_peric1_pclk_5", 2061 "mout_peric1_bus_user", 2062 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 2063 21, 0, 0), 2064 GATE(CLK_GOUT_PERIC1_PCLK_6, "gout_peric1_pclk_6", 2065 "mout_peric1_bus_user", 2066 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 2067 21, 0, 0), 2068 GATE(CLK_GOUT_PERIC1_PCLK_7, "gout_peric1_pclk_7", 2069 "mout_peric1_bus_user", 2070 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7, 2071 21, 0, 0), 2072 GATE(CLK_GOUT_PERIC1_PCLK_8, "gout_peric1_pclk_8", 2073 "mout_peric1_bus_user", 2074 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 2075 21, 0, 0), 2076 GATE(CLK_GOUT_PERIC1_PCLK_9, "gout_peric1_pclk_9", 2077 "mout_peric1_bus_user", 2078 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9, 2079 21, 0, 0), 2080 GATE(CLK_GOUT_PERIC1_PCLK_10, "gout_peric1_pclk_10", 2081 "mout_peric1_bus_user", 2082 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10, 2083 21, 0, 0), 2084 GATE(CLK_GOUT_PERIC1_PCLK_11, "gout_peric1_pclk_11", 2085 "mout_peric1_bus_user", 2086 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11, 2087 21, 0, 0), 2088}; 2089 2090static const struct samsung_cmu_info peric1_cmu_info __initconst = { 2091 .mux_clks = peric1_mux_clks, 2092 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 2093 .div_clks = peric1_div_clks, 2094 .nr_div_clks = ARRAY_SIZE(peric1_div_clks), 2095 .gate_clks = peric1_gate_clks, 2096 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 2097 .nr_clk_ids = CLKS_NR_PERIC1, 2098 .clk_regs = peric1_clk_regs, 2099 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 2100 .clk_name = "dout_clkcmu_peric1_bus", 2101}; 2102 2103/* ---- CMU_PERIS ---------------------------------------------------------- */ 2104 2105/* Register Offset definitions for CMU_PERIS (0x10020000) */ 2106#define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600 2107#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2058 2108#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x205c 2109#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x2060 2110 2111static const unsigned long peris_clk_regs[] __initconst = { 2112 PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 2113 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, 2114 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 2115 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 2116}; 2117 2118/* List of parent clocks for Muxes in CMU_PERIS */ 2119PNAME(mout_peris_bus_user_p) = { "oscclk", "dout_clkcmu_peris_bus" }; 2120 2121static const struct samsung_mux_clock peris_mux_clks[] __initconst = { 2122 MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user", 2123 mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 4, 1), 2124}; 2125 2126static const struct samsung_gate_clock peris_gate_clks[] __initconst = { 2127 GATE(CLK_GOUT_SYSREG_PERIS_PCLK, "gout_sysreg_peris_pclk", 2128 "mout_peris_bus_user", 2129 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, 2130 21, CLK_IGNORE_UNUSED, 0), 2131 GATE(CLK_GOUT_WDT_CLUSTER0, "gout_wdt_cluster0", "mout_peris_bus_user", 2132 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 2133 21, 0, 0), 2134 GATE(CLK_GOUT_WDT_CLUSTER1, "gout_wdt_cluster1", "mout_peris_bus_user", 2135 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 2136 21, 0, 0), 2137}; 2138 2139static const struct samsung_cmu_info peris_cmu_info __initconst = { 2140 .mux_clks = peris_mux_clks, 2141 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 2142 .gate_clks = peris_gate_clks, 2143 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 2144 .nr_clk_ids = CLKS_NR_PERIS, 2145 .clk_regs = peris_clk_regs, 2146 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 2147 .clk_name = "dout_clkcmu_peris_bus", 2148}; 2149 2150static int __init exynosautov9_cmu_probe(struct platform_device *pdev) 2151{ 2152 const struct samsung_cmu_info *info; 2153 struct device *dev = &pdev->dev; 2154 2155 info = of_device_get_match_data(dev); 2156 exynos_arm64_register_cmu(dev, dev->of_node, info); 2157 2158 return 0; 2159} 2160 2161static const struct of_device_id exynosautov9_cmu_of_match[] = { 2162 { 2163 .compatible = "samsung,exynosautov9-cmu-busmc", 2164 .data = &busmc_cmu_info, 2165 }, { 2166 .compatible = "samsung,exynosautov9-cmu-core", 2167 .data = &core_cmu_info, 2168 }, { 2169 .compatible = "samsung,exynosautov9-cmu-dpum", 2170 .data = &dpum_cmu_info, 2171 }, { 2172 .compatible = "samsung,exynosautov9-cmu-fsys0", 2173 .data = &fsys0_cmu_info, 2174 }, { 2175 .compatible = "samsung,exynosautov9-cmu-fsys1", 2176 .data = &fsys1_cmu_info, 2177 }, { 2178 .compatible = "samsung,exynosautov9-cmu-fsys2", 2179 .data = &fsys2_cmu_info, 2180 }, { 2181 .compatible = "samsung,exynosautov9-cmu-peric0", 2182 .data = &peric0_cmu_info, 2183 }, { 2184 .compatible = "samsung,exynosautov9-cmu-peric1", 2185 .data = &peric1_cmu_info, 2186 }, { 2187 .compatible = "samsung,exynosautov9-cmu-peris", 2188 .data = &peris_cmu_info, 2189 }, { 2190 }, 2191}; 2192 2193static struct platform_driver exynosautov9_cmu_driver __refdata = { 2194 .driver = { 2195 .name = "exynosautov9-cmu", 2196 .of_match_table = exynosautov9_cmu_of_match, 2197 .suppress_bind_attrs = true, 2198 }, 2199 .probe = exynosautov9_cmu_probe, 2200}; 2201 2202static int __init exynosautov9_cmu_init(void) 2203{ 2204 return platform_driver_register(&exynosautov9_cmu_driver); 2205} 2206core_initcall(exynosautov9_cmu_init);
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