clk-exynos7885.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
  4 * Author: Dávid Virág <virag.david003@gmail.com>
  5 *
  6 * Common Clock Framework support for Exynos7885 SoC.
  7 */
  8
  9#include <linux/clk-provider.h>
 10#include <linux/mod_devicetable.h>
 11#include <linux/of.h>
 12#include <linux/platform_device.h>
 13
 14#include <dt-bindings/clock/exynos7885.h>
 15
 16#include "clk.h"
 17#include "clk-exynos-arm64.h"
 18
 19/* NOTE: Must be equal to the last clock ID increased by one */
 20#define CLKS_NR_TOP			(CLK_MOUT_SHARED1_PLL + 1)
 21#define CLKS_NR_CORE			(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
 22#define CLKS_NR_PERI			(CLK_GOUT_WDT1_PCLK + 1)
 23#define CLKS_NR_FSYS			(CLK_FSYS_USB30DRD_REF_CLK + 1)
 24
 25/* ---- CMU_TOP ------------------------------------------------------------- */
 26
 27/* Register Offset definitions for CMU_TOP (0x12060000) */
 28#define PLL_LOCKTIME_PLL_SHARED0		0x0000
 29#define PLL_LOCKTIME_PLL_SHARED1		0x0004
 30#define PLL_CON0_PLL_SHARED0			0x0100
 31#define PLL_CON0_PLL_SHARED1			0x0120
 32#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS		0x1014
 33#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI		0x1018
 34#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D		0x101c
 35#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS		0x1028
 36#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD	0x102c
 37#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD	0x1030
 38#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO	0x1034
 39#define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD	0x1038
 40#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS		0x1058
 41#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0	0x105c
 42#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1	0x1060
 43#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0	0x1064
 44#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1	0x1068
 45#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2	0x106c
 46#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0	0x1070
 47#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1	0x1074
 48#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2	0x1078
 49#define CLK_CON_DIV_CLKCMU_CORE_BUS		0x181c
 50#define CLK_CON_DIV_CLKCMU_CORE_CCI		0x1820
 51#define CLK_CON_DIV_CLKCMU_CORE_G3D		0x1824
 52#define CLK_CON_DIV_CLKCMU_FSYS_BUS		0x1844
 53#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD	0x1848
 54#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD	0x184c
 55#define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO	0x1850
 56#define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD	0x1854
 57#define CLK_CON_DIV_CLKCMU_PERI_BUS		0x1874
 58#define CLK_CON_DIV_CLKCMU_PERI_SPI0		0x1878
 59#define CLK_CON_DIV_CLKCMU_PERI_SPI1		0x187c
 60#define CLK_CON_DIV_CLKCMU_PERI_UART0		0x1880
 61#define CLK_CON_DIV_CLKCMU_PERI_UART1		0x1884
 62#define CLK_CON_DIV_CLKCMU_PERI_UART2		0x1888
 63#define CLK_CON_DIV_CLKCMU_PERI_USI0		0x188c
 64#define CLK_CON_DIV_CLKCMU_PERI_USI1		0x1890
 65#define CLK_CON_DIV_CLKCMU_PERI_USI2		0x1894
 66#define CLK_CON_DIV_PLL_SHARED0_DIV2		0x189c
 67#define CLK_CON_DIV_PLL_SHARED0_DIV3		0x18a0
 68#define CLK_CON_DIV_PLL_SHARED0_DIV4		0x18a4
 69#define CLK_CON_DIV_PLL_SHARED0_DIV5		0x18a8
 70#define CLK_CON_DIV_PLL_SHARED1_DIV2		0x18ac
 71#define CLK_CON_DIV_PLL_SHARED1_DIV3		0x18b0
 72#define CLK_CON_DIV_PLL_SHARED1_DIV4		0x18b4
 73#define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1	0x2004
 74#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS	0x201c
 75#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI	0x2020
 76#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D	0x2024
 77#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS	0x2044
 78#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD	0x2048
 79#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD	0x204c
 80#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO	0x2050
 81#define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD	0x2054
 82#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS	0x207c
 83#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0	0x2080
 84#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1	0x2084
 85#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0	0x2088
 86#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2	0x208c
 87#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0	0x2090
 88#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1	0x2094
 89#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2	0x2098
 90
 91static const unsigned long top_clk_regs[] __initconst = {
 92	PLL_LOCKTIME_PLL_SHARED0,
 93	PLL_LOCKTIME_PLL_SHARED1,
 94	PLL_CON0_PLL_SHARED0,
 95	PLL_CON0_PLL_SHARED1,
 96	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
 97	CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
 98	CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
 99	CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS,
100	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD,
101	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD,
102	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO,
103	CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD,
104	CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
105	CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
106	CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
107	CLK_CON_MUX_MUX_CLKCMU_PERI_UART0,
108	CLK_CON_MUX_MUX_CLKCMU_PERI_UART1,
109	CLK_CON_MUX_MUX_CLKCMU_PERI_UART2,
110	CLK_CON_MUX_MUX_CLKCMU_PERI_USI0,
111	CLK_CON_MUX_MUX_CLKCMU_PERI_USI1,
112	CLK_CON_MUX_MUX_CLKCMU_PERI_USI2,
113	CLK_CON_DIV_CLKCMU_CORE_BUS,
114	CLK_CON_DIV_CLKCMU_CORE_CCI,
115	CLK_CON_DIV_CLKCMU_CORE_G3D,
116	CLK_CON_DIV_CLKCMU_FSYS_BUS,
117	CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD,
118	CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD,
119	CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO,
120	CLK_CON_DIV_CLKCMU_FSYS_USB30DRD,
121	CLK_CON_DIV_CLKCMU_PERI_BUS,
122	CLK_CON_DIV_CLKCMU_PERI_SPI0,
123	CLK_CON_DIV_CLKCMU_PERI_SPI1,
124	CLK_CON_DIV_CLKCMU_PERI_UART0,
125	CLK_CON_DIV_CLKCMU_PERI_UART1,
126	CLK_CON_DIV_CLKCMU_PERI_UART2,
127	CLK_CON_DIV_CLKCMU_PERI_USI0,
128	CLK_CON_DIV_CLKCMU_PERI_USI1,
129	CLK_CON_DIV_CLKCMU_PERI_USI2,
130	CLK_CON_DIV_PLL_SHARED0_DIV2,
131	CLK_CON_DIV_PLL_SHARED0_DIV3,
132	CLK_CON_DIV_PLL_SHARED0_DIV4,
133	CLK_CON_DIV_PLL_SHARED0_DIV5,
134	CLK_CON_DIV_PLL_SHARED1_DIV2,
135	CLK_CON_DIV_PLL_SHARED1_DIV3,
136	CLK_CON_DIV_PLL_SHARED1_DIV4,
137	CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1,
138	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
139	CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
140	CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
141	CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS,
142	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD,
143	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD,
144	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO,
145	CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD,
146	CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
147	CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
148	CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
149	CLK_CON_GAT_GATE_CLKCMU_PERI_UART0,
150	CLK_CON_GAT_GATE_CLKCMU_PERI_UART2,
151	CLK_CON_GAT_GATE_CLKCMU_PERI_USI0,
152	CLK_CON_GAT_GATE_CLKCMU_PERI_USI1,
153	CLK_CON_GAT_GATE_CLKCMU_PERI_USI2,
154};
155
156static const struct samsung_pll_clock top_pll_clks[] __initconst = {
157	PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
158	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
159	    NULL),
160	PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
161	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1,
162	    NULL),
163};
164
165/* List of parent clocks for Muxes in CMU_TOP */
166PNAME(mout_shared0_pll_p)	= { "oscclk", "fout_shared0_pll" };
167PNAME(mout_shared1_pll_p)	= { "oscclk", "fout_shared1_pll" };
168
169/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
170PNAME(mout_core_bus_p)		= { "dout_shared0_div2", "dout_shared1_div2",
171				    "dout_shared0_div3", "dout_shared0_div3" };
172PNAME(mout_core_cci_p)		= { "dout_shared0_div2", "dout_shared1_div2",
173				    "dout_shared0_div3", "dout_shared0_div3" };
174PNAME(mout_core_g3d_p)		= { "dout_shared0_div2", "dout_shared1_div2",
175				    "dout_shared0_div3", "dout_shared0_div3" };
176
177/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
178PNAME(mout_peri_bus_p)		= { "dout_shared0_div4", "dout_shared1_div4" };
179PNAME(mout_peri_spi0_p)		= { "oscclk", "dout_shared0_div4" };
180PNAME(mout_peri_spi1_p)		= { "oscclk", "dout_shared0_div4" };
181PNAME(mout_peri_uart0_p)	= { "oscclk", "dout_shared0_div4" };
182PNAME(mout_peri_uart1_p)	= { "oscclk", "dout_shared0_div4" };
183PNAME(mout_peri_uart2_p)	= { "oscclk", "dout_shared0_div4" };
184PNAME(mout_peri_usi0_p)		= { "oscclk", "dout_shared0_div4" };
185PNAME(mout_peri_usi1_p)		= { "oscclk", "dout_shared0_div4" };
186PNAME(mout_peri_usi2_p)		= { "oscclk", "dout_shared0_div4" };
187
188/* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */
189PNAME(mout_fsys_bus_p)		= { "dout_shared0_div2", "dout_shared1_div2" };
190PNAME(mout_fsys_mmc_card_p)	= { "dout_shared0_div2", "dout_shared1_div2" };
191PNAME(mout_fsys_mmc_embd_p)	= { "dout_shared0_div2", "dout_shared1_div2" };
192PNAME(mout_fsys_mmc_sdio_p)	= { "dout_shared0_div2", "dout_shared1_div2" };
193PNAME(mout_fsys_usb30drd_p)	= { "dout_shared0_div4", "dout_shared1_div4" };
194
195static const struct samsung_mux_clock top_mux_clks[] __initconst = {
196	/* TOP */
197	MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
198	    PLL_CON0_PLL_SHARED0, 4, 1),
199	MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
200	    PLL_CON0_PLL_SHARED1, 4, 1),
201
202	/* CORE */
203	MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
204	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
205	MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
206	    CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
207	MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
208	    CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
209
210	/* PERI */
211	MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
212	    CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
213	MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p,
214	    CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1),
215	MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p,
216	    CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1),
217	MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p,
218	    CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1),
219	MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p,
220	    CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1),
221	MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p,
222	    CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1),
223	MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p,
224	    CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1),
225	MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p,
226	    CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
227	MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
228	    CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
229
230	/* FSYS */
231	MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p,
232	    CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1),
233	MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p,
234	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1),
235	MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p,
236	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1),
237	MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p,
238	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1),
239	MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p,
240	    CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1),
241};
242
243static const struct samsung_div_clock top_div_clks[] __initconst = {
244	/* TOP */
245	DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
246	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
247	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
248	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
249	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
250	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
251	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
252	    CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
253	DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
254	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
255	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
256	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
257	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
258	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
259
260	/* CORE */
261	DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
262	    CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3),
263	DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
264	    CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3),
265	DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d",
266	    CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3),
267
268	/* PERI */
269	DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
270	    CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
271	DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0",
272	    CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6),
273	DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1",
274	    CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6),
275	DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0",
276	    CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4),
277	DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1",
278	    CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4),
279	DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2",
280	    CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4),
281	DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0",
282	    CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4),
283	DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1",
284	    CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
285	DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
286	    CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
287
288	/* FSYS */
289	DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus",
290	    CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
291	DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card",
292	    CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9),
293	DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd",
294	    CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9),
295	DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio",
296	    CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9),
297	DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd",
298	    CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4),
299};
300
301static const struct samsung_gate_clock top_gate_clks[] __initconst = {
302	/* CORE */
303	GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
304	     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
305	GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
306	     CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
307	GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d",
308	     CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0),
309
310	/* PERI */
311	GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
312	     CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
313	GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0",
314	     CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0),
315	GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1",
316	     CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0),
317	GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0",
318	     CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0),
319	GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1",
320	     CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0),
321	GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2",
322	     CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0),
323	GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0",
324	     CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0),
325	GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1",
326	     CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
327	GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
328	     CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
329
330	/* FSYS */
331	GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus",
332	     CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0),
333	GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card",
334	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0),
335	GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd",
336	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0),
337	GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio",
338	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0),
339	GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd",
340	     CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0),
341};
342
343static const struct samsung_cmu_info top_cmu_info __initconst = {
344	.pll_clks		= top_pll_clks,
345	.nr_pll_clks		= ARRAY_SIZE(top_pll_clks),
346	.mux_clks		= top_mux_clks,
347	.nr_mux_clks		= ARRAY_SIZE(top_mux_clks),
348	.div_clks		= top_div_clks,
349	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
350	.gate_clks		= top_gate_clks,
351	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
352	.nr_clk_ids		= CLKS_NR_TOP,
353	.clk_regs		= top_clk_regs,
354	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
355};
356
357static void __init exynos7885_cmu_top_init(struct device_node *np)
358{
359	exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
360}
361
362/* Register CMU_TOP early, as it's a dependency for other early domains */
363CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top",
364	       exynos7885_cmu_top_init);
365
366/* ---- CMU_PERI ------------------------------------------------------------ */
367
368/* Register Offset definitions for CMU_PERI (0x10010000) */
369#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER	0x0100
370#define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER	0x0120
371#define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER	0x0140
372#define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER	0x0160
373#define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER	0x0180
374#define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER	0x01a0
375#define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER	0x01c0
376#define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER	0x01e0
377#define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER	0x0200
378#define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK	0x2024
379#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK	0x2028
380#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK	0x202c
381#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK	0x2030
382#define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK	0x2034
383#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK	0x2038
384#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK	0x203c
385#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK	0x2040
386#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK	0x2044
387#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK	0x2048
388#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK	0x204c
389#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK	0x2050
390#define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK	0x2054
391#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK	0x2058
392#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK	0x205c
393#define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK	0x2060
394#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK	0x2064
395#define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK	0x2068
396#define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK	0x206c
397#define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK	0x2070
398#define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK	0x2074
399#define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK	0x2078
400#define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK	0x207c
401#define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK	0x2080
402#define CLK_CON_GAT_GOUT_PERI_USI0_PCLK		0x2084
403#define CLK_CON_GAT_GOUT_PERI_USI0_SCLK		0x2088
404#define CLK_CON_GAT_GOUT_PERI_USI1_PCLK		0x208c
405#define CLK_CON_GAT_GOUT_PERI_USI1_SCLK		0x2090
406#define CLK_CON_GAT_GOUT_PERI_USI2_PCLK		0x2094
407#define CLK_CON_GAT_GOUT_PERI_USI2_SCLK		0x2098
408#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK		0x20a0
409#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK	0x20b0
410#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK	0x20b4
411#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK	0x20b8
412
413static const unsigned long peri_clk_regs[] __initconst = {
414	PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
415	PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER,
416	PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER,
417	PLL_CON0_MUX_CLKCMU_PERI_UART0_USER,
418	PLL_CON0_MUX_CLKCMU_PERI_UART1_USER,
419	PLL_CON0_MUX_CLKCMU_PERI_UART2_USER,
420	PLL_CON0_MUX_CLKCMU_PERI_USI0_USER,
421	PLL_CON0_MUX_CLKCMU_PERI_USI1_USER,
422	PLL_CON0_MUX_CLKCMU_PERI_USI2_USER,
423	CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK,
424	CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
425	CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
426	CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
427	CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK,
428	CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
429	CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
430	CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
431	CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
432	CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
433	CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
434	CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
435	CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK,
436	CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
437	CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
438	CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK,
439	CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK,
440	CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK,
441	CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK,
442	CLK_CON_GAT_GOUT_PERI_UART_0_PCLK,
443	CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK,
444	CLK_CON_GAT_GOUT_PERI_UART_1_PCLK,
445	CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK,
446	CLK_CON_GAT_GOUT_PERI_UART_2_PCLK,
447	CLK_CON_GAT_GOUT_PERI_USI0_PCLK,
448	CLK_CON_GAT_GOUT_PERI_USI0_SCLK,
449	CLK_CON_GAT_GOUT_PERI_USI1_PCLK,
450	CLK_CON_GAT_GOUT_PERI_USI1_SCLK,
451	CLK_CON_GAT_GOUT_PERI_USI2_PCLK,
452	CLK_CON_GAT_GOUT_PERI_USI2_SCLK,
453	CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
454	CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
455	CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
456	CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
457};
458
459/* List of parent clocks for Muxes in CMU_PERI */
460PNAME(mout_peri_bus_user_p)	= { "oscclk", "dout_peri_bus" };
461PNAME(mout_peri_spi0_user_p)	= { "oscclk", "dout_peri_spi0" };
462PNAME(mout_peri_spi1_user_p)	= { "oscclk", "dout_peri_spi1" };
463PNAME(mout_peri_uart0_user_p)	= { "oscclk", "dout_peri_uart0" };
464PNAME(mout_peri_uart1_user_p)	= { "oscclk", "dout_peri_uart1" };
465PNAME(mout_peri_uart2_user_p)	= { "oscclk", "dout_peri_uart2" };
466PNAME(mout_peri_usi0_user_p)	= { "oscclk", "dout_peri_usi0" };
467PNAME(mout_peri_usi1_user_p)	= { "oscclk", "dout_peri_usi1" };
468PNAME(mout_peri_usi2_user_p)	= { "oscclk", "dout_peri_usi2" };
469
470static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
471	MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
472	    PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
473	MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p,
474	    PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1),
475	MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p,
476	    PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1),
477	MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user",
478	    mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1),
479	MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user",
480	    mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1),
481	MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user",
482	    mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1),
483	MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user",
484	    mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1),
485	MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user",
486	    mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1),
487	MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user",
488	    mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1),
489};
490
491static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
492	/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
493	GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk",
494	     "mout_peri_bus_user",
495	     CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
496	GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
497	     CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
498	GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
499	     CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
500	GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
501	     CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
502	GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user",
503	     CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0),
504	GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
505	     CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
506	GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
507	     CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
508	GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
509	     CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
510	GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
511	     CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
512	GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
513	     CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
514	GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
515	     CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
516	GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
517	     CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
518	GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user",
519	     CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0),
520	GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
521	     "mout_peri_bus_user",
522	     CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
523	GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
524	     CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
525	GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user",
526	     CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0),
527	GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user",
528	     CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0),
529	GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user",
530	     CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0),
531	GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user",
532	     CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0),
533	GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user",
534	     CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0),
535	GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user",
536	     CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0),
537	GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user",
538	     CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0),
539	GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user",
540	     CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0),
541	GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user",
542	     CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0),
543	GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user",
544	     CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0),
545	GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user",
546	     CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0),
547	GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user",
548	     CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0),
549	GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user",
550	     CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0),
551	GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user",
552	     CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0),
553	GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user",
554	     CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0),
555	GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
556	     CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
557	GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
558	     "mout_peri_bus_user",
559	     CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
560	GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
561	     CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0),
562	GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
563	     CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0),
564};
565
566static const struct samsung_cmu_info peri_cmu_info __initconst = {
567	.mux_clks		= peri_mux_clks,
568	.nr_mux_clks		= ARRAY_SIZE(peri_mux_clks),
569	.gate_clks		= peri_gate_clks,
570	.nr_gate_clks		= ARRAY_SIZE(peri_gate_clks),
571	.nr_clk_ids		= CLKS_NR_PERI,
572	.clk_regs		= peri_clk_regs,
573	.nr_clk_regs		= ARRAY_SIZE(peri_clk_regs),
574	.clk_name		= "dout_peri_bus",
575};
576
577static void __init exynos7885_cmu_peri_init(struct device_node *np)
578{
579	exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
580}
581
582/* Register CMU_PERI early, as it's needed for MCT timer */
583CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
584	       exynos7885_cmu_peri_init);
585
586/* ---- CMU_CORE ------------------------------------------------------------ */
587
588/* Register Offset definitions for CMU_CORE (0x12000000) */
589#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER		0x0100
590#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER		0x0120
591#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER		0x0140
592#define CLK_CON_MUX_MUX_CLK_CORE_GIC			0x1000
593#define CLK_CON_DIV_DIV_CLK_CORE_BUSP			0x1800
594#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK		0x2054
595#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK		0x2058
596#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK		0x215c
597#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK		0x2160
598#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK		0x2164
599#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE	0x2168
600#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE	0x216c
601#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK		0x2170
602#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE	0x2174
603
604static const unsigned long core_clk_regs[] __initconst = {
605	PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
606	PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
607	PLL_CON0_MUX_CLKCMU_CORE_G3D_USER,
608	CLK_CON_MUX_MUX_CLK_CORE_GIC,
609	CLK_CON_DIV_DIV_CLK_CORE_BUSP,
610	CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
611	CLK_CON_GAT_GOUT_CORE_GIC400_CLK,
612	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK,
613	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK,
614	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK,
615	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE,
616	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE,
617	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK,
618	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE,
619};
620
621/* List of parent clocks for Muxes in CMU_CORE */
622PNAME(mout_core_bus_user_p)		= { "oscclk", "dout_core_bus" };
623PNAME(mout_core_cci_user_p)		= { "oscclk", "dout_core_cci" };
624PNAME(mout_core_g3d_user_p)		= { "oscclk", "dout_core_g3d" };
625PNAME(mout_core_gic_p)			= { "dout_core_busp", "oscclk" };
626
627static const struct samsung_mux_clock core_mux_clks[] __initconst = {
628	MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
629	    PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
630	MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
631	    PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
632	MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p,
633	    PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1),
634	MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
635	    CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
636};
637
638static const struct samsung_div_clock core_div_clks[] __initconst = {
639	DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
640	    CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
641};
642
643static const struct samsung_gate_clock core_gate_clks[] __initconst = {
644	/* CCI (interconnect) clock must be always running */
645	GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
646	     CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
647	/* GIC (interrupt controller) clock must be always running */
648	GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",
649	     CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
650	/*
651	 * TREX D and P Core (seems to be related to "bus traffic shaper")
652	 * clocks must always be running
653	 */
654	GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk", "mout_core_bus_user",
655	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0),
656	GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk", "mout_core_g3d_user",
657	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0),
658	GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk", "dout_core_busp",
659	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
660	GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core",
661	     "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21,
662	     CLK_IS_CRITICAL, 0),
663	GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core",
664	     "mout_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21,
665	     CLK_IS_CRITICAL, 0),
666	GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk", "dout_core_busp",
667	     CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
668	GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core",
669	     "dout_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21,
670	     CLK_IS_CRITICAL, 0),
671};
672
673static const struct samsung_cmu_info core_cmu_info __initconst = {
674	.mux_clks		= core_mux_clks,
675	.nr_mux_clks		= ARRAY_SIZE(core_mux_clks),
676	.div_clks		= core_div_clks,
677	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
678	.gate_clks		= core_gate_clks,
679	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
680	.nr_clk_ids		= CLKS_NR_CORE,
681	.clk_regs		= core_clk_regs,
682	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
683	.clk_name		= "dout_core_bus",
684};
685
686/* ---- CMU_FSYS ------------------------------------------------------------ */
687
688/* Register Offset definitions for CMU_FSYS (0x13400000) */
689#define PLL_LOCKTIME_PLL_USB				0x0000
690#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER		0x0100
691#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER		0x0120
692#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER		0x0140
693#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER		0x0160
694#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER		0x0180
695#define PLL_CON0_PLL_USB				0x01a0
696#define CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE		0x200c
697#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK		0x2030
698#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN		0x2034
699#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK		0x2038
700#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN		0x203c
701#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK		0x2040
702#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN		0x2044
703#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL	0x2068
704#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0	0x206c
705#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1	0x2070
706#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY	0x2074
707#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK		0x2078
708
709static const unsigned long fsys_clk_regs[] __initconst = {
710	PLL_LOCKTIME_PLL_USB,
711	PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
712	PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
713	PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
714	PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
715	PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
716	PLL_CON0_PLL_USB,
717	CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE,
718	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
719	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
720	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
721	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
722	CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
723	CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
724	CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL,
725	CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0,
726	CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1,
727	CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY,
728	CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK,
729};
730
731static const struct samsung_pll_rate_table pll_usb_rate_table[] __initconst = {
732	PLL_35XX_RATE(26 * MHZ, 50000000U, 400, 13, 4),
733};
734
735static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
736	PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
737	    PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
738	    pll_usb_rate_table),
739};
740
741/* List of parent clocks for Muxes in CMU_FSYS */
742PNAME(mout_fsys_bus_user_p)		= { "oscclk", "dout_fsys_bus" };
743PNAME(mout_fsys_mmc_card_user_p)	= { "oscclk", "dout_fsys_mmc_card" };
744PNAME(mout_fsys_mmc_embd_user_p)	= { "oscclk", "dout_fsys_mmc_embd" };
745PNAME(mout_fsys_mmc_sdio_user_p)	= { "oscclk", "dout_fsys_mmc_sdio" };
746PNAME(mout_fsys_usb30drd_user_p)	= { "oscclk", "dout_fsys_usb30drd" };
747PNAME(mout_usb_pll_p)			= { "oscclk", "fout_usb_pll" };
748
749static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
750	MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
751	    PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1),
752	MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user",
753	      mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
754	      4, 1, CLK_SET_RATE_PARENT, 0),
755	MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user",
756	      mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
757	      4, 1, CLK_SET_RATE_PARENT, 0),
758	MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
759	      mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
760	      4, 1, CLK_SET_RATE_PARENT, 0),
761	MUX(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
762	      mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
763	      4, 1),
764	nMUX_F(CLK_MOUT_USB_PLL, "mout_usb_pll", mout_usb_pll_p,
765	    PLL_CON0_PLL_USB, 4, 1, CLK_SET_RATE_PARENT, 0),
766};
767
768static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
769	GATE(CLK_FSYS_USB20PHY_CLKCORE, "clk_fsys_usb20phy_clkcore", "mout_usb_pll",
770	     CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE, 21, CLK_SET_RATE_PARENT, 0),
771	GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
772	     CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
773	GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
774	     "mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
775	     21, CLK_SET_RATE_PARENT, 0),
776	GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user",
777	     CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0),
778	GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
779	     "mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
780	     21, CLK_SET_RATE_PARENT, 0),
781	GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user",
782	     CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0),
783	GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
784	     "mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
785	     21, CLK_SET_RATE_PARENT, 0),
786	GATE(CLK_FSYS_USB30DRD_ACLK_20PHYCTRL, "clk_fsys_usb30drd_aclk_20phyctrl",
787	     "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL, 21, 0, 0),
788	GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0, "clk_fsys_usb30drd_aclk_30phyctrl_0",
789	     "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0, 21, 0, 0),
790	GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1, "clk_fsys_usb30drd_aclk_30phyctrl_1",
791	     "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1, 21, 0, 0),
792	GATE(CLK_FSYS_USB30DRD_BUS_CLK_EARLY, "clk_fsys_usb30drd_bus_clk_early",
793	     "mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY, 21, 0, 0),
794	GATE(CLK_FSYS_USB30DRD_REF_CLK, "clk_fsys_usb30drd_ref_clk", "mout_fsys_usb30drd_user",
795	     CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK, 21, 0, 0),
796};
797
798static const struct samsung_cmu_info fsys_cmu_info __initconst = {
799	.pll_clks		= fsys_pll_clks,
800	.nr_pll_clks		= ARRAY_SIZE(fsys_pll_clks),
801	.mux_clks		= fsys_mux_clks,
802	.nr_mux_clks		= ARRAY_SIZE(fsys_mux_clks),
803	.gate_clks		= fsys_gate_clks,
804	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),
805	.nr_clk_ids		= CLKS_NR_FSYS,
806	.clk_regs		= fsys_clk_regs,
807	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),
808	.clk_name		= "dout_fsys_bus",
809};
810
811/* ---- platform_driver ----------------------------------------------------- */
812
813static int __init exynos7885_cmu_probe(struct platform_device *pdev)
814{
815	const struct samsung_cmu_info *info;
816	struct device *dev = &pdev->dev;
817
818	info = of_device_get_match_data(dev);
819	exynos_arm64_register_cmu(dev, dev->of_node, info);
820
821	return 0;
822}
823
824static const struct of_device_id exynos7885_cmu_of_match[] = {
825	{
826		.compatible = "samsung,exynos7885-cmu-core",
827		.data = &core_cmu_info,
828	}, {
829		.compatible = "samsung,exynos7885-cmu-fsys",
830		.data = &fsys_cmu_info,
831	}, {
832	},
833};
834
835static struct platform_driver exynos7885_cmu_driver __refdata = {
836	.driver	= {
837		.name = "exynos7885-cmu",
838		.of_match_table = exynos7885_cmu_of_match,
839		.suppress_bind_attrs = true,
840	},
841	.probe = exynos7885_cmu_probe,
842};
843
844static int __init exynos7885_cmu_init(void)
845{
846	return platform_driver_register(&exynos7885_cmu_driver);
847}
848core_initcall(exynos7885_cmu_init);