clk-exynos5433.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   4 * Author: Chanwoo Choi <cw00.choi@samsung.com>
   5 *
   6 * Common Clock Framework support for Exynos5433 SoC.
   7 */
   8
   9#include <linux/clk-provider.h>
  10#include <linux/mod_devicetable.h>
  11#include <linux/platform_device.h>
  12#include <linux/pm_runtime.h>
  13#include <linux/slab.h>
  14
  15#include <dt-bindings/clock/exynos5433.h>
  16
  17#include "clk.h"
  18#include "clk-cpu.h"
  19#include "clk-exynos-arm64.h"
  20#include "clk-pll.h"
  21
  22/* NOTE: Must be equal to the last clock ID increased by one */
  23#define CLKS_NR_TOP			(CLK_SCLK_HDMI_SPDIF_DISP + 1)
  24#define CLKS_NR_CPIF			(CLK_SCLK_UFS_MPHY + 1)
  25#define CLKS_NR_MIF			(CLK_SCLK_BUS_PLL_ATLAS + 1)
  26#define CLKS_NR_PERIC			(CLK_DIV_SCLK_SC_IN + 1)
  27#define CLKS_NR_PERIS			(CLK_SCLK_OTP_CON + 1)
  28#define CLKS_NR_FSYS			(CLK_PCIE + 1)
  29#define CLKS_NR_G2D			(CLK_PCLK_SMMU_G2D + 1)
  30#define CLKS_NR_DISP			(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1)
  31#define CLKS_NR_AUD			(CLK_SCLK_AUD_I2S + 1)
  32#define CLKS_NR_BUSX			(CLK_ACLK_BUS2RTND_400 + 1)
  33#define CLKS_NR_G3D			(CLK_SCLK_HPM_G3D + 1)
  34#define CLKS_NR_GSCL			(CLK_PCLK_SMMU_GSCL2 + 1)
  35#define CLKS_NR_APOLLO			(CLK_SCLK_APOLLO + 1)
  36#define CLKS_NR_ATLAS			(CLK_SCLK_ATLAS + 1)
  37#define CLKS_NR_MSCL			(CLK_SCLK_JPEG + 1)
  38#define CLKS_NR_MFC			(CLK_PCLK_SMMU_MFC_0 + 1)
  39#define CLKS_NR_HEVC			(CLK_PCLK_SMMU_HEVC_0 + 1)
  40#define CLKS_NR_ISP			(CLK_SCLK_PIXELASYNCM_ISPC + 1)
  41#define CLKS_NR_CAM0			(CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1)
  42#define CLKS_NR_CAM1			(CLK_SCLK_ISP_CA5 + 1)
  43#define CLKS_NR_IMEM			(CLK_PCLK_SLIMSSS + 1)
  44
  45/*
  46 * Register offset definitions for CMU_TOP
  47 */
  48#define ISP_PLL_LOCK			0x0000
  49#define AUD_PLL_LOCK			0x0004
  50#define ISP_PLL_CON0			0x0100
  51#define ISP_PLL_CON1			0x0104
  52#define ISP_PLL_FREQ_DET		0x0108
  53#define AUD_PLL_CON0			0x0110
  54#define AUD_PLL_CON1			0x0114
  55#define AUD_PLL_CON2			0x0118
  56#define AUD_PLL_FREQ_DET		0x011c
  57#define MUX_SEL_TOP0			0x0200
  58#define MUX_SEL_TOP1			0x0204
  59#define MUX_SEL_TOP2			0x0208
  60#define MUX_SEL_TOP3			0x020c
  61#define MUX_SEL_TOP4			0x0210
  62#define MUX_SEL_TOP_MSCL		0x0220
  63#define MUX_SEL_TOP_CAM1		0x0224
  64#define MUX_SEL_TOP_DISP		0x0228
  65#define MUX_SEL_TOP_FSYS0		0x0230
  66#define MUX_SEL_TOP_FSYS1		0x0234
  67#define MUX_SEL_TOP_PERIC0		0x0238
  68#define MUX_SEL_TOP_PERIC1		0x023c
  69#define MUX_ENABLE_TOP0			0x0300
  70#define MUX_ENABLE_TOP1			0x0304
  71#define MUX_ENABLE_TOP2			0x0308
  72#define MUX_ENABLE_TOP3			0x030c
  73#define MUX_ENABLE_TOP4			0x0310
  74#define MUX_ENABLE_TOP_MSCL		0x0320
  75#define MUX_ENABLE_TOP_CAM1		0x0324
  76#define MUX_ENABLE_TOP_DISP		0x0328
  77#define MUX_ENABLE_TOP_FSYS0		0x0330
  78#define MUX_ENABLE_TOP_FSYS1		0x0334
  79#define MUX_ENABLE_TOP_PERIC0		0x0338
  80#define MUX_ENABLE_TOP_PERIC1		0x033c
  81#define MUX_STAT_TOP0			0x0400
  82#define MUX_STAT_TOP1			0x0404
  83#define MUX_STAT_TOP2			0x0408
  84#define MUX_STAT_TOP3			0x040c
  85#define MUX_STAT_TOP4			0x0410
  86#define MUX_STAT_TOP_MSCL		0x0420
  87#define MUX_STAT_TOP_CAM1		0x0424
  88#define MUX_STAT_TOP_FSYS0		0x0430
  89#define MUX_STAT_TOP_FSYS1		0x0434
  90#define MUX_STAT_TOP_PERIC0		0x0438
  91#define MUX_STAT_TOP_PERIC1		0x043c
  92#define DIV_TOP0			0x0600
  93#define DIV_TOP1			0x0604
  94#define DIV_TOP2			0x0608
  95#define DIV_TOP3			0x060c
  96#define DIV_TOP4			0x0610
  97#define DIV_TOP_MSCL			0x0618
  98#define DIV_TOP_CAM10			0x061c
  99#define DIV_TOP_CAM11			0x0620
 100#define DIV_TOP_FSYS0			0x062c
 101#define DIV_TOP_FSYS1			0x0630
 102#define DIV_TOP_FSYS2			0x0634
 103#define DIV_TOP_PERIC0			0x0638
 104#define DIV_TOP_PERIC1			0x063c
 105#define DIV_TOP_PERIC2			0x0640
 106#define DIV_TOP_PERIC3			0x0644
 107#define DIV_TOP_PERIC4			0x0648
 108#define DIV_TOP_PLL_FREQ_DET		0x064c
 109#define DIV_STAT_TOP0			0x0700
 110#define DIV_STAT_TOP1			0x0704
 111#define DIV_STAT_TOP2			0x0708
 112#define DIV_STAT_TOP3			0x070c
 113#define DIV_STAT_TOP4			0x0710
 114#define DIV_STAT_TOP_MSCL		0x0718
 115#define DIV_STAT_TOP_CAM10		0x071c
 116#define DIV_STAT_TOP_CAM11		0x0720
 117#define DIV_STAT_TOP_FSYS0		0x072c
 118#define DIV_STAT_TOP_FSYS1		0x0730
 119#define DIV_STAT_TOP_FSYS2		0x0734
 120#define DIV_STAT_TOP_PERIC0		0x0738
 121#define DIV_STAT_TOP_PERIC1		0x073c
 122#define DIV_STAT_TOP_PERIC2		0x0740
 123#define DIV_STAT_TOP_PERIC3		0x0744
 124#define DIV_STAT_TOP_PLL_FREQ_DET	0x074c
 125#define ENABLE_ACLK_TOP			0x0800
 126#define ENABLE_SCLK_TOP			0x0a00
 127#define ENABLE_SCLK_TOP_MSCL		0x0a04
 128#define ENABLE_SCLK_TOP_CAM1		0x0a08
 129#define ENABLE_SCLK_TOP_DISP		0x0a0c
 130#define ENABLE_SCLK_TOP_FSYS		0x0a10
 131#define ENABLE_SCLK_TOP_PERIC		0x0a14
 132#define ENABLE_IP_TOP			0x0b00
 133#define ENABLE_CMU_TOP			0x0c00
 134#define ENABLE_CMU_TOP_DIV_STAT		0x0c04
 135
 136static const unsigned long top_clk_regs[] __initconst = {
 137	ISP_PLL_LOCK,
 138	AUD_PLL_LOCK,
 139	ISP_PLL_CON0,
 140	ISP_PLL_CON1,
 141	ISP_PLL_FREQ_DET,
 142	AUD_PLL_CON0,
 143	AUD_PLL_CON1,
 144	AUD_PLL_CON2,
 145	AUD_PLL_FREQ_DET,
 146	MUX_SEL_TOP0,
 147	MUX_SEL_TOP1,
 148	MUX_SEL_TOP2,
 149	MUX_SEL_TOP3,
 150	MUX_SEL_TOP4,
 151	MUX_SEL_TOP_MSCL,
 152	MUX_SEL_TOP_CAM1,
 153	MUX_SEL_TOP_DISP,
 154	MUX_SEL_TOP_FSYS0,
 155	MUX_SEL_TOP_FSYS1,
 156	MUX_SEL_TOP_PERIC0,
 157	MUX_SEL_TOP_PERIC1,
 158	MUX_ENABLE_TOP0,
 159	MUX_ENABLE_TOP1,
 160	MUX_ENABLE_TOP2,
 161	MUX_ENABLE_TOP3,
 162	MUX_ENABLE_TOP4,
 163	MUX_ENABLE_TOP_MSCL,
 164	MUX_ENABLE_TOP_CAM1,
 165	MUX_ENABLE_TOP_DISP,
 166	MUX_ENABLE_TOP_FSYS0,
 167	MUX_ENABLE_TOP_FSYS1,
 168	MUX_ENABLE_TOP_PERIC0,
 169	MUX_ENABLE_TOP_PERIC1,
 170	DIV_TOP0,
 171	DIV_TOP1,
 172	DIV_TOP2,
 173	DIV_TOP3,
 174	DIV_TOP4,
 175	DIV_TOP_MSCL,
 176	DIV_TOP_CAM10,
 177	DIV_TOP_CAM11,
 178	DIV_TOP_FSYS0,
 179	DIV_TOP_FSYS1,
 180	DIV_TOP_FSYS2,
 181	DIV_TOP_PERIC0,
 182	DIV_TOP_PERIC1,
 183	DIV_TOP_PERIC2,
 184	DIV_TOP_PERIC3,
 185	DIV_TOP_PERIC4,
 186	DIV_TOP_PLL_FREQ_DET,
 187	ENABLE_ACLK_TOP,
 188	ENABLE_SCLK_TOP,
 189	ENABLE_SCLK_TOP_MSCL,
 190	ENABLE_SCLK_TOP_CAM1,
 191	ENABLE_SCLK_TOP_DISP,
 192	ENABLE_SCLK_TOP_FSYS,
 193	ENABLE_SCLK_TOP_PERIC,
 194	ENABLE_IP_TOP,
 195	ENABLE_CMU_TOP,
 196	ENABLE_CMU_TOP_DIV_STAT,
 197};
 198
 199static const struct samsung_clk_reg_dump top_suspend_regs[] = {
 200	/* force all aclk clocks enabled */
 201	{ ENABLE_ACLK_TOP, 0x67ecffed },
 202	/* force all sclk_uart clocks enabled */
 203	{ ENABLE_SCLK_TOP_PERIC, 0x38 },
 204	/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
 205	{ ISP_PLL_CON0, 0x85cc0502 },
 206	/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
 207	{ AUD_PLL_CON0, 0x84830202 },
 208};
 209
 210/* list of all parent clock list */
 211PNAME(mout_aud_pll_p)		= { "oscclk", "fout_aud_pll", };
 212PNAME(mout_isp_pll_p)		= { "oscclk", "fout_isp_pll", };
 213PNAME(mout_aud_pll_user_p)	= { "oscclk", "mout_aud_pll", };
 214PNAME(mout_mphy_pll_user_p)	= { "oscclk", "sclk_mphy_pll", };
 215PNAME(mout_mfc_pll_user_p)	= { "oscclk", "sclk_mfc_pll", };
 216PNAME(mout_bus_pll_user_p)	= { "oscclk", "sclk_bus_pll", };
 217PNAME(mout_bus_pll_user_t_p)	= { "oscclk", "mout_bus_pll_user", };
 218PNAME(mout_mphy_pll_user_t_p)	= { "oscclk", "mout_mphy_pll_user", };
 219
 220PNAME(mout_bus_mfc_pll_user_p)	= { "mout_bus_pll_user", "mout_mfc_pll_user",};
 221PNAME(mout_mfc_bus_pll_user_p)	= { "mout_mfc_pll_user", "mout_bus_pll_user",};
 222PNAME(mout_aclk_cam1_552_b_p)	= { "mout_aclk_cam1_552_a",
 223				    "mout_mfc_pll_user", };
 224PNAME(mout_aclk_cam1_552_a_p)	= { "mout_isp_pll", "mout_bus_pll_user", };
 225
 226PNAME(mout_aclk_mfc_400_c_p)	= { "mout_aclk_mfc_400_b",
 227				    "mout_mphy_pll_user", };
 228PNAME(mout_aclk_mfc_400_b_p)	= { "mout_aclk_mfc_400_a",
 229				    "mout_bus_pll_user", };
 230PNAME(mout_aclk_mfc_400_a_p)	= { "mout_mfc_pll_user", "mout_isp_pll", };
 231
 232PNAME(mout_bus_mphy_pll_user_p)	= { "mout_bus_pll_user",
 233				    "mout_mphy_pll_user", };
 234PNAME(mout_aclk_mscl_b_p)	= { "mout_aclk_mscl_400_a",
 235				    "mout_mphy_pll_user", };
 236PNAME(mout_aclk_g2d_400_b_p)	= { "mout_aclk_g2d_400_a",
 237				    "mout_mphy_pll_user", };
 238
 239PNAME(mout_sclk_jpeg_c_p)	= { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
 240PNAME(mout_sclk_jpeg_b_p)	= { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
 241
 242PNAME(mout_sclk_mmc2_b_p)	= { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
 243PNAME(mout_sclk_mmc1_b_p)	= { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
 244PNAME(mout_sclk_mmc0_d_p)	= { "mout_sclk_mmc0_c", "mout_isp_pll", };
 245PNAME(mout_sclk_mmc0_c_p)	= { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
 246PNAME(mout_sclk_mmc0_b_p)	= { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
 247
 248PNAME(mout_sclk_spdif_p)	= { "sclk_audio0", "sclk_audio1",
 249				    "oscclk", "ioclk_spdif_extclk", };
 250PNAME(mout_sclk_audio1_p)	= { "ioclk_audiocdclk1", "oscclk",
 251				    "mout_aud_pll_user_t",};
 252PNAME(mout_sclk_audio0_p)	= { "ioclk_audiocdclk0", "oscclk",
 253				    "mout_aud_pll_user_t",};
 254
 255PNAME(mout_sclk_hdmi_spdif_p)	= { "sclk_audio1", "ioclk_spdif_extclk", };
 256
 257static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
 258	FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
 259};
 260
 261static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
 262	/* Xi2s{0|1}CDCLK input clock for I2S/PCM */
 263	FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
 264	FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
 265	/* Xi2s1SDI input clock for SPDIF */
 266	FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
 267	/* XspiCLK[4:0] input clock for SPI */
 268	FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
 269	FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
 270	FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
 271	FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
 272	FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
 273	/* Xi2s1SCLK input clock for I2S1_BCLK */
 274	FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
 275};
 276
 277static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 278	/* MUX_SEL_TOP0 */
 279	MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
 280			4, 1),
 281	MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
 282			0, 1),
 283
 284	/* MUX_SEL_TOP1 */
 285	MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
 286			mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
 287	MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
 288			MUX_SEL_TOP1, 8, 1),
 289	MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
 290			MUX_SEL_TOP1, 4, 1),
 291	MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
 292			MUX_SEL_TOP1, 0, 1),
 293
 294	/* MUX_SEL_TOP2 */
 295	MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
 296			mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
 297	MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
 298			mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
 299	MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
 300			mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
 301	MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
 302			mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
 303	MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
 304			mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
 305	MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
 306			mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
 307
 308	/* MUX_SEL_TOP3 */
 309	MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
 310			mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
 311	MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
 312			mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
 313	MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
 314			mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
 315	MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
 316			mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
 317	MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
 318			mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
 319	MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
 320			mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
 321
 322	/* MUX_SEL_TOP4 */
 323	MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
 324			mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
 325	MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
 326			mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
 327	MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
 328			mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
 329
 330	/* MUX_SEL_TOP_MSCL */
 331	MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
 332			MUX_SEL_TOP_MSCL, 8, 1),
 333	MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
 334			MUX_SEL_TOP_MSCL, 4, 1),
 335	MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
 336			MUX_SEL_TOP_MSCL, 0, 1),
 337
 338	/* MUX_SEL_TOP_CAM1 */
 339	MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
 340			mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
 341	MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
 342			mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
 343	MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
 344			mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
 345	MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
 346			mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
 347	MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
 348			mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
 349	MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
 350			mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
 351
 352	/* MUX_SEL_TOP_FSYS0 */
 353	MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
 354			MUX_SEL_TOP_FSYS0, 28, 1),
 355	MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
 356			MUX_SEL_TOP_FSYS0, 24, 1),
 357	MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
 358			MUX_SEL_TOP_FSYS0, 20, 1),
 359	MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
 360			MUX_SEL_TOP_FSYS0, 16, 1),
 361	MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
 362			MUX_SEL_TOP_FSYS0, 12, 1),
 363	MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
 364			MUX_SEL_TOP_FSYS0, 8, 1),
 365	MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
 366			MUX_SEL_TOP_FSYS0, 4, 1),
 367	MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
 368			MUX_SEL_TOP_FSYS0, 0, 1),
 369
 370	/* MUX_SEL_TOP_FSYS1 */
 371	MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
 372			MUX_SEL_TOP_FSYS1, 12, 1),
 373	MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
 374			mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
 375	MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
 376			mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
 377	MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
 378			mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
 379
 380	/* MUX_SEL_TOP_PERIC0 */
 381	MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
 382			MUX_SEL_TOP_PERIC0, 28, 1),
 383	MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
 384			MUX_SEL_TOP_PERIC0, 24, 1),
 385	MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
 386			MUX_SEL_TOP_PERIC0, 20, 1),
 387	MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
 388			MUX_SEL_TOP_PERIC0, 16, 1),
 389	MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
 390			MUX_SEL_TOP_PERIC0, 12, 1),
 391	MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
 392			MUX_SEL_TOP_PERIC0, 8, 1),
 393	MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
 394			MUX_SEL_TOP_PERIC0, 4, 1),
 395	MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
 396			MUX_SEL_TOP_PERIC0, 0, 1),
 397
 398	/* MUX_SEL_TOP_PERIC1 */
 399	MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
 400			MUX_SEL_TOP_PERIC1, 16, 1),
 401	MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
 402			MUX_SEL_TOP_PERIC1, 12, 2),
 403	MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
 404			MUX_SEL_TOP_PERIC1, 4, 2),
 405	MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
 406			MUX_SEL_TOP_PERIC1, 0, 2),
 407
 408	/* MUX_SEL_TOP_DISP */
 409	MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
 410			mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
 411};
 412
 413static const struct samsung_div_clock top_div_clks[] __initconst = {
 414	/* DIV_TOP0 */
 415	DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
 416			DIV_TOP0, 28, 3),
 417	DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
 418			DIV_TOP0, 24, 3),
 419	DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
 420			DIV_TOP0, 20, 3),
 421	DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
 422			DIV_TOP0, 16, 3),
 423	DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
 424			DIV_TOP0, 12, 3),
 425	DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
 426			DIV_TOP0, 8, 3),
 427	DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
 428			"mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
 429	DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
 430			"mout_aclk_isp_400", DIV_TOP0, 0, 4),
 431
 432	/* DIV_TOP1 */
 433	DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
 434			DIV_TOP1, 28, 3),
 435	DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
 436			DIV_TOP1, 24, 3),
 437	DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
 438			DIV_TOP1, 20, 3),
 439	DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
 440			DIV_TOP1, 12, 3),
 441	DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
 442			DIV_TOP1, 8, 3),
 443	DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
 444			DIV_TOP1, 0, 3),
 445
 446	/* DIV_TOP2 */
 447	DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
 448			DIV_TOP2, 4, 3),
 449	DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
 450			DIV_TOP2, 0, 3),
 451
 452	/* DIV_TOP3 */
 453	DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
 454			"mout_bus_pll_user", DIV_TOP3, 24, 3),
 455	DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
 456			"mout_bus_pll_user", DIV_TOP3, 20, 3),
 457	DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
 458			"mout_bus_pll_user", DIV_TOP3, 16, 3),
 459	DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
 460			"div_aclk_peric_66_a", DIV_TOP3, 12, 3),
 461	DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
 462			"mout_bus_pll_user", DIV_TOP3, 8, 3),
 463	DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
 464			"div_aclk_peris_66_a", DIV_TOP3, 4, 3),
 465	DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
 466			"mout_bus_pll_user", DIV_TOP3, 0, 3),
 467
 468	/* DIV_TOP4 */
 469	DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
 470			DIV_TOP4, 8, 3),
 471	DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
 472			DIV_TOP4, 4, 3),
 473	DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
 474			DIV_TOP4, 0, 3),
 475
 476	/* DIV_TOP_MSCL */
 477	DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
 478			DIV_TOP_MSCL, 0, 4),
 479
 480	/* DIV_TOP_CAM10 */
 481	DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
 482			DIV_TOP_CAM10, 24, 5),
 483	DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
 484			"div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
 485	DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
 486			"mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
 487	DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
 488			"div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
 489	DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
 490			"mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
 491
 492	/* DIV_TOP_CAM11 */
 493	DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
 494			"div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
 495	DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
 496			"mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
 497	DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
 498			"div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
 499	DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
 500			"mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
 501	DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
 502			"div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
 503	DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
 504			"mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
 505
 506	/* DIV_TOP_FSYS0 */
 507	DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
 508			DIV_TOP_FSYS0, 16, 8),
 509	DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
 510			DIV_TOP_FSYS0, 12, 4),
 511	DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
 512			DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
 513	DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
 514			DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
 515
 516	/* DIV_TOP_FSYS1 */
 517	DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
 518			DIV_TOP_FSYS1, 4, 8),
 519	DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
 520			DIV_TOP_FSYS1, 0, 4),
 521
 522	/* DIV_TOP_FSYS2 */
 523	DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
 524			DIV_TOP_FSYS2, 12, 3),
 525	DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
 526			"mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
 527	DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
 528			"mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
 529	DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
 530			DIV_TOP_FSYS2, 0, 4),
 531
 532	/* DIV_TOP_PERIC0 */
 533	DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
 534			DIV_TOP_PERIC0, 16, 8),
 535	DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
 536			DIV_TOP_PERIC0, 12, 4),
 537	DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
 538			DIV_TOP_PERIC0, 4, 8),
 539	DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
 540			DIV_TOP_PERIC0, 0, 4),
 541
 542	/* DIV_TOP_PERIC1 */
 543	DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
 544			DIV_TOP_PERIC1, 4, 8),
 545	DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
 546			DIV_TOP_PERIC1, 0, 4),
 547
 548	/* DIV_TOP_PERIC2 */
 549	DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
 550			DIV_TOP_PERIC2, 8, 4),
 551	DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
 552			DIV_TOP_PERIC2, 4, 4),
 553	DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
 554			DIV_TOP_PERIC2, 0, 4),
 555
 556	/* DIV_TOP_PERIC3 */
 557	DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
 558			DIV_TOP_PERIC3, 16, 6),
 559	DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
 560			DIV_TOP_PERIC3, 8, 8),
 561	DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
 562			DIV_TOP_PERIC3, 4, 4),
 563	DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
 564			DIV_TOP_PERIC3, 0, 4),
 565
 566	/* DIV_TOP_PERIC4 */
 567	DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
 568			DIV_TOP_PERIC4, 16, 8),
 569	DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
 570			DIV_TOP_PERIC4, 12, 4),
 571	DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
 572			DIV_TOP_PERIC4, 4, 8),
 573	DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
 574			DIV_TOP_PERIC4, 0, 4),
 575};
 576
 577static const struct samsung_gate_clock top_gate_clks[] __initconst = {
 578	/* ENABLE_ACLK_TOP */
 579	GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
 580			ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
 581	GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
 582			"div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
 583			29, CLK_IGNORE_UNUSED, 0),
 584	GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
 585			ENABLE_ACLK_TOP, 26,
 586			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
 587	GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
 588			ENABLE_ACLK_TOP, 25,
 589			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
 590	GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
 591			ENABLE_ACLK_TOP, 24,
 592			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
 593	GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
 594			ENABLE_ACLK_TOP, 23,
 595			CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 596	GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
 597			ENABLE_ACLK_TOP, 22,
 598			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 599	GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
 600			ENABLE_ACLK_TOP, 21,
 601			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 602	GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
 603			ENABLE_ACLK_TOP, 19,
 604			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 605	GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
 606			ENABLE_ACLK_TOP, 18,
 607			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 608	GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
 609			ENABLE_ACLK_TOP, 15,
 610			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 611	GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
 612			ENABLE_ACLK_TOP, 14,
 613			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 614	GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
 615			ENABLE_ACLK_TOP, 13,
 616			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 617	GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
 618			ENABLE_ACLK_TOP, 12,
 619			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 620	GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
 621			ENABLE_ACLK_TOP, 11,
 622			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 623	GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
 624			ENABLE_ACLK_TOP, 10,
 625			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 626	GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
 627			ENABLE_ACLK_TOP, 9,
 628			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 629	GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
 630			ENABLE_ACLK_TOP, 8,
 631			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 632	GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
 633			ENABLE_ACLK_TOP, 7,
 634			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 635	GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
 636			ENABLE_ACLK_TOP, 6,
 637			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 638	GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
 639			ENABLE_ACLK_TOP, 5,
 640			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 641	GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
 642			ENABLE_ACLK_TOP, 3,
 643			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 644	GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
 645			ENABLE_ACLK_TOP, 2,
 646			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 647	GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
 648			ENABLE_ACLK_TOP, 0,
 649			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 650
 651	/* ENABLE_SCLK_TOP_MSCL */
 652	GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
 653			ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
 654
 655	/* ENABLE_SCLK_TOP_CAM1 */
 656	GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
 657			ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
 658	GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
 659			ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
 660	GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
 661			ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
 662	GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
 663			ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
 664	GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
 665			ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
 666	GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
 667			ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
 668	GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
 669			ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
 670
 671	/* ENABLE_SCLK_TOP_DISP */
 672	GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
 673			"mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
 674			CLK_IGNORE_UNUSED, 0),
 675
 676	/* ENABLE_SCLK_TOP_FSYS */
 677	GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
 678			ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
 679	GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
 680			ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
 681	GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
 682			ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
 683	GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
 684			ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
 685	GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
 686			"div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
 687			3, CLK_SET_RATE_PARENT, 0),
 688	GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
 689			"div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
 690			1, CLK_SET_RATE_PARENT, 0),
 691	GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
 692			"div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
 693			0, CLK_SET_RATE_PARENT, 0),
 694
 695	/* ENABLE_SCLK_TOP_PERIC */
 696	GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
 697			ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
 698	GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
 699			ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 700	GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
 701			ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 702	GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
 703			ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 704	GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
 705			ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 706	GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
 707			ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
 708			CLK_IGNORE_UNUSED, 0),
 709	GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
 710			ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
 711			CLK_IGNORE_UNUSED, 0),
 712	GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
 713			ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
 714			CLK_IGNORE_UNUSED, 0),
 715	GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
 716			ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 717	GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
 718			ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 719	GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
 720			ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 721
 722	/* MUX_ENABLE_TOP_PERIC1 */
 723	GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
 724			MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
 725	GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
 726			MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
 727	GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
 728			MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
 729};
 730
 731/*
 732 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
 733 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
 734 */
 735static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
 736	PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6,  0),
 737	PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5,  0),
 738	PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6,  0),
 739	PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6,  0),
 740	PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4,  0),
 741	PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6,  0),
 742	PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6,  0),
 743	PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5,  0),
 744	PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6,  0),
 745	PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6,  0),
 746	PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4,  0),
 747	PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6,  0),
 748	PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4,  0),
 749	PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6,  0),
 750	PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5,  1),
 751	PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6,  1),
 752	PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4,  1),
 753	PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6,  1),
 754	PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6,  1),
 755	PLL_35XX_RATE(24 * MHZ, 933000000U,  311, 4,  1),
 756	PLL_35XX_RATE(24 * MHZ, 921000000U,  307, 4,  1),
 757	PLL_35XX_RATE(24 * MHZ, 900000000U,  375, 5,  1),
 758	PLL_35XX_RATE(24 * MHZ, 825000000U,  275, 4,  1),
 759	PLL_35XX_RATE(24 * MHZ, 800000000U,  400, 6,  1),
 760	PLL_35XX_RATE(24 * MHZ, 733000000U,  733, 12, 1),
 761	PLL_35XX_RATE(24 * MHZ, 700000000U,  175, 3,  1),
 762	PLL_35XX_RATE(24 * MHZ, 666000000U,  222, 4,  1),
 763	PLL_35XX_RATE(24 * MHZ, 633000000U,  211, 4,  1),
 764	PLL_35XX_RATE(24 * MHZ, 600000000U,  500, 5,  2),
 765	PLL_35XX_RATE(24 * MHZ, 552000000U,  460, 5,  2),
 766	PLL_35XX_RATE(24 * MHZ, 550000000U,  550, 6,  2),
 767	PLL_35XX_RATE(24 * MHZ, 543000000U,  362, 4,  2),
 768	PLL_35XX_RATE(24 * MHZ, 533000000U,  533, 6,  2),
 769	PLL_35XX_RATE(24 * MHZ, 500000000U,  500, 6,  2),
 770	PLL_35XX_RATE(24 * MHZ, 444000000U,  370, 5,  2),
 771	PLL_35XX_RATE(24 * MHZ, 420000000U,  350, 5,  2),
 772	PLL_35XX_RATE(24 * MHZ, 400000000U,  400, 6,  2),
 773	PLL_35XX_RATE(24 * MHZ, 350000000U,  350, 6,  2),
 774	PLL_35XX_RATE(24 * MHZ, 333000000U,  222, 4,  2),
 775	PLL_35XX_RATE(24 * MHZ, 300000000U,  500, 5,  3),
 776	PLL_35XX_RATE(24 * MHZ, 278000000U,  556, 6,  3),
 777	PLL_35XX_RATE(24 * MHZ, 266000000U,  532, 6,  3),
 778	PLL_35XX_RATE(24 * MHZ, 250000000U,  500, 6,  3),
 779	PLL_35XX_RATE(24 * MHZ, 200000000U,  400, 6,  3),
 780	PLL_35XX_RATE(24 * MHZ, 166000000U,  332, 6,  3),
 781	PLL_35XX_RATE(24 * MHZ, 160000000U,  320, 6,  3),
 782	PLL_35XX_RATE(24 * MHZ, 133000000U,  532, 6,  4),
 783	PLL_35XX_RATE(24 * MHZ, 100000000U,  400, 6,  4),
 784	{ /* sentinel */ }
 785};
 786
 787/* AUD_PLL */
 788static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
 789	PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2,      0),
 790	PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
 791	PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2,      0),
 792	PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
 793	PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
 794	PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2,  -6816),
 795	PLL_36XX_RATE(24 * MHZ, 294912002U,  98, 1, 3,  19923),
 796	PLL_36XX_RATE(24 * MHZ, 288000000U,  96, 1, 3,      0),
 797	PLL_36XX_RATE(24 * MHZ, 252000000U,  84, 1, 3,      0),
 798	PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
 799	{ /* sentinel */ }
 800};
 801
 802static const struct samsung_pll_clock top_pll_clks[] __initconst = {
 803	PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
 804		ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates),
 805	PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
 806		AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates),
 807};
 808
 809static const struct samsung_cmu_info top_cmu_info __initconst = {
 810	.pll_clks		= top_pll_clks,
 811	.nr_pll_clks		= ARRAY_SIZE(top_pll_clks),
 812	.mux_clks		= top_mux_clks,
 813	.nr_mux_clks		= ARRAY_SIZE(top_mux_clks),
 814	.div_clks		= top_div_clks,
 815	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
 816	.gate_clks		= top_gate_clks,
 817	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
 818	.fixed_clks		= top_fixed_clks,
 819	.nr_fixed_clks		= ARRAY_SIZE(top_fixed_clks),
 820	.fixed_factor_clks	= top_fixed_factor_clks,
 821	.nr_fixed_factor_clks	= ARRAY_SIZE(top_fixed_factor_clks),
 822	.nr_clk_ids		= CLKS_NR_TOP,
 823	.clk_regs		= top_clk_regs,
 824	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
 825	.suspend_regs		= top_suspend_regs,
 826	.nr_suspend_regs	= ARRAY_SIZE(top_suspend_regs),
 827};
 828
 829static void __init exynos5433_cmu_top_init(struct device_node *np)
 830{
 831	samsung_cmu_register_one(np, &top_cmu_info);
 832}
 833CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
 834		exynos5433_cmu_top_init);
 835
 836/*
 837 * Register offset definitions for CMU_CPIF
 838 */
 839#define MPHY_PLL_LOCK		0x0000
 840#define MPHY_PLL_CON0		0x0100
 841#define MPHY_PLL_CON1		0x0104
 842#define MPHY_PLL_FREQ_DET	0x010c
 843#define MUX_SEL_CPIF0		0x0200
 844#define DIV_CPIF		0x0600
 845#define ENABLE_SCLK_CPIF	0x0a00
 846
 847static const unsigned long cpif_clk_regs[] __initconst = {
 848	MPHY_PLL_LOCK,
 849	MPHY_PLL_CON0,
 850	MPHY_PLL_CON1,
 851	MPHY_PLL_FREQ_DET,
 852	MUX_SEL_CPIF0,
 853	DIV_CPIF,
 854	ENABLE_SCLK_CPIF,
 855};
 856
 857static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
 858	/* force all sclk clocks enabled */
 859	{ ENABLE_SCLK_CPIF, 0x3ff },
 860	/* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
 861	{ MPHY_PLL_CON0, 0x81c70601 },
 862};
 863
 864/* list of all parent clock list */
 865PNAME(mout_mphy_pll_p)		= { "oscclk", "fout_mphy_pll", };
 866
 867static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
 868	PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
 869		MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates),
 870};
 871
 872static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
 873	/* MUX_SEL_CPIF0 */
 874	MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
 875			0, 1),
 876};
 877
 878static const struct samsung_div_clock cpif_div_clks[] __initconst = {
 879	/* DIV_CPIF */
 880	DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
 881			0, 6),
 882};
 883
 884static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
 885	/* ENABLE_SCLK_CPIF */
 886	GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
 887			ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
 888	GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
 889			ENABLE_SCLK_CPIF, 4, 0, 0),
 890};
 891
 892static const struct samsung_cmu_info cpif_cmu_info __initconst = {
 893	.pll_clks		= cpif_pll_clks,
 894	.nr_pll_clks		= ARRAY_SIZE(cpif_pll_clks),
 895	.mux_clks		= cpif_mux_clks,
 896	.nr_mux_clks		= ARRAY_SIZE(cpif_mux_clks),
 897	.div_clks		= cpif_div_clks,
 898	.nr_div_clks		= ARRAY_SIZE(cpif_div_clks),
 899	.gate_clks		= cpif_gate_clks,
 900	.nr_gate_clks		= ARRAY_SIZE(cpif_gate_clks),
 901	.nr_clk_ids		= CLKS_NR_CPIF,
 902	.clk_regs		= cpif_clk_regs,
 903	.nr_clk_regs		= ARRAY_SIZE(cpif_clk_regs),
 904	.suspend_regs		= cpif_suspend_regs,
 905	.nr_suspend_regs	= ARRAY_SIZE(cpif_suspend_regs),
 906};
 907
 908static void __init exynos5433_cmu_cpif_init(struct device_node *np)
 909{
 910	samsung_cmu_register_one(np, &cpif_cmu_info);
 911}
 912CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
 913		exynos5433_cmu_cpif_init);
 914
 915/*
 916 * Register offset definitions for CMU_MIF
 917 */
 918#define MEM0_PLL_LOCK			0x0000
 919#define MEM1_PLL_LOCK			0x0004
 920#define BUS_PLL_LOCK			0x0008
 921#define MFC_PLL_LOCK			0x000c
 922#define MEM0_PLL_CON0			0x0100
 923#define MEM0_PLL_CON1			0x0104
 924#define MEM0_PLL_FREQ_DET		0x010c
 925#define MEM1_PLL_CON0			0x0110
 926#define MEM1_PLL_CON1			0x0114
 927#define MEM1_PLL_FREQ_DET		0x011c
 928#define BUS_PLL_CON0			0x0120
 929#define BUS_PLL_CON1			0x0124
 930#define BUS_PLL_FREQ_DET		0x012c
 931#define MFC_PLL_CON0			0x0130
 932#define MFC_PLL_CON1			0x0134
 933#define MFC_PLL_FREQ_DET		0x013c
 934#define MUX_SEL_MIF0			0x0200
 935#define MUX_SEL_MIF1			0x0204
 936#define MUX_SEL_MIF2			0x0208
 937#define MUX_SEL_MIF3			0x020c
 938#define MUX_SEL_MIF4			0x0210
 939#define MUX_SEL_MIF5			0x0214
 940#define MUX_SEL_MIF6			0x0218
 941#define MUX_SEL_MIF7			0x021c
 942#define MUX_ENABLE_MIF0			0x0300
 943#define MUX_ENABLE_MIF1			0x0304
 944#define MUX_ENABLE_MIF2			0x0308
 945#define MUX_ENABLE_MIF3			0x030c
 946#define MUX_ENABLE_MIF4			0x0310
 947#define MUX_ENABLE_MIF5			0x0314
 948#define MUX_ENABLE_MIF6			0x0318
 949#define MUX_ENABLE_MIF7			0x031c
 950#define MUX_STAT_MIF0			0x0400
 951#define MUX_STAT_MIF1			0x0404
 952#define MUX_STAT_MIF2			0x0408
 953#define MUX_STAT_MIF3			0x040c
 954#define MUX_STAT_MIF4			0x0410
 955#define MUX_STAT_MIF5			0x0414
 956#define MUX_STAT_MIF6			0x0418
 957#define MUX_STAT_MIF7			0x041c
 958#define DIV_MIF1			0x0604
 959#define DIV_MIF2			0x0608
 960#define DIV_MIF3			0x060c
 961#define DIV_MIF4			0x0610
 962#define DIV_MIF5			0x0614
 963#define DIV_MIF_PLL_FREQ_DET		0x0618
 964#define DIV_STAT_MIF1			0x0704
 965#define DIV_STAT_MIF2			0x0708
 966#define DIV_STAT_MIF3			0x070c
 967#define DIV_STAT_MIF4			0x0710
 968#define DIV_STAT_MIF5			0x0714
 969#define DIV_STAT_MIF_PLL_FREQ_DET	0x0718
 970#define ENABLE_ACLK_MIF0		0x0800
 971#define ENABLE_ACLK_MIF1		0x0804
 972#define ENABLE_ACLK_MIF2		0x0808
 973#define ENABLE_ACLK_MIF3		0x080c
 974#define ENABLE_PCLK_MIF			0x0900
 975#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ	0x0904
 976#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ	0x0908
 977#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT	0x090c
 978#define ENABLE_PCLK_MIF_SECURE_RTC	0x0910
 979#define ENABLE_SCLK_MIF			0x0a00
 980#define ENABLE_IP_MIF0			0x0b00
 981#define ENABLE_IP_MIF1			0x0b04
 982#define ENABLE_IP_MIF2			0x0b08
 983#define ENABLE_IP_MIF3			0x0b0c
 984#define ENABLE_IP_MIF_SECURE_DREX0_TZ	0x0b10
 985#define ENABLE_IP_MIF_SECURE_DREX1_TZ	0x0b14
 986#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT	0x0b18
 987#define ENABLE_IP_MIF_SECURE_RTC	0x0b1c
 988#define CLKOUT_CMU_MIF			0x0c00
 989#define CLKOUT_CMU_MIF_DIV_STAT		0x0c04
 990#define DREX_FREQ_CTRL0			0x1000
 991#define DREX_FREQ_CTRL1			0x1004
 992#define PAUSE				0x1008
 993#define DDRPHY_LOCK_CTRL		0x100c
 994
 995static const unsigned long mif_clk_regs[] __initconst = {
 996	MEM0_PLL_LOCK,
 997	MEM1_PLL_LOCK,
 998	BUS_PLL_LOCK,
 999	MFC_PLL_LOCK,
1000	MEM0_PLL_CON0,
1001	MEM0_PLL_CON1,
1002	MEM0_PLL_FREQ_DET,
1003	MEM1_PLL_CON0,
1004	MEM1_PLL_CON1,
1005	MEM1_PLL_FREQ_DET,
1006	BUS_PLL_CON0,
1007	BUS_PLL_CON1,
1008	BUS_PLL_FREQ_DET,
1009	MFC_PLL_CON0,
1010	MFC_PLL_CON1,
1011	MFC_PLL_FREQ_DET,
1012	MUX_SEL_MIF0,
1013	MUX_SEL_MIF1,
1014	MUX_SEL_MIF2,
1015	MUX_SEL_MIF3,
1016	MUX_SEL_MIF4,
1017	MUX_SEL_MIF5,
1018	MUX_SEL_MIF6,
1019	MUX_SEL_MIF7,
1020	MUX_ENABLE_MIF0,
1021	MUX_ENABLE_MIF1,
1022	MUX_ENABLE_MIF2,
1023	MUX_ENABLE_MIF3,
1024	MUX_ENABLE_MIF4,
1025	MUX_ENABLE_MIF5,
1026	MUX_ENABLE_MIF6,
1027	MUX_ENABLE_MIF7,
1028	DIV_MIF1,
1029	DIV_MIF2,
1030	DIV_MIF3,
1031	DIV_MIF4,
1032	DIV_MIF5,
1033	DIV_MIF_PLL_FREQ_DET,
1034	ENABLE_ACLK_MIF0,
1035	ENABLE_ACLK_MIF1,
1036	ENABLE_ACLK_MIF2,
1037	ENABLE_ACLK_MIF3,
1038	ENABLE_PCLK_MIF,
1039	ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1040	ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1041	ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1042	ENABLE_PCLK_MIF_SECURE_RTC,
1043	ENABLE_SCLK_MIF,
1044	ENABLE_IP_MIF0,
1045	ENABLE_IP_MIF1,
1046	ENABLE_IP_MIF2,
1047	ENABLE_IP_MIF3,
1048	ENABLE_IP_MIF_SECURE_DREX0_TZ,
1049	ENABLE_IP_MIF_SECURE_DREX1_TZ,
1050	ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1051	ENABLE_IP_MIF_SECURE_RTC,
1052	CLKOUT_CMU_MIF,
1053	CLKOUT_CMU_MIF_DIV_STAT,
1054	DREX_FREQ_CTRL0,
1055	DREX_FREQ_CTRL1,
1056	PAUSE,
1057	DDRPHY_LOCK_CTRL,
1058};
1059
1060static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1061	PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1062		MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates),
1063	PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1064		MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates),
1065	PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1066		BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates),
1067	PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1068		MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates),
1069};
1070
1071/* list of all parent clock list */
1072PNAME(mout_mfc_pll_div2_p)	= { "mout_mfc_pll", "dout_mfc_pll", };
1073PNAME(mout_bus_pll_div2_p)	= { "mout_bus_pll", "dout_bus_pll", };
1074PNAME(mout_mem1_pll_div2_p)	= { "mout_mem1_pll", "dout_mem1_pll", };
1075PNAME(mout_mem0_pll_div2_p)	= { "mout_mem0_pll", "dout_mem0_pll", };
1076PNAME(mout_mfc_pll_p)		= { "oscclk", "fout_mfc_pll", };
1077PNAME(mout_bus_pll_p)		= { "oscclk", "fout_bus_pll", };
1078PNAME(mout_mem1_pll_p)		= { "oscclk", "fout_mem1_pll", };
1079PNAME(mout_mem0_pll_p)		= { "oscclk", "fout_mem0_pll", };
1080
1081PNAME(mout_clk2x_phy_c_p)	= { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1082PNAME(mout_clk2x_phy_b_p)	= { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1083PNAME(mout_clk2x_phy_a_p)	= { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1084PNAME(mout_clkm_phy_b_p)	= { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1085
1086PNAME(mout_aclk_mifnm_200_p)	= { "mout_mem0_pll_div2", "div_mif_pre", };
1087PNAME(mout_aclk_mifnm_400_p)	= { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1088
1089PNAME(mout_aclk_disp_333_b_p)	= { "mout_aclk_disp_333_a",
1090				    "mout_bus_pll_div2", };
1091PNAME(mout_aclk_disp_333_a_p)	= { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1092
1093PNAME(mout_sclk_decon_vclk_c_p)	= { "mout_sclk_decon_vclk_b",
1094				    "sclk_mphy_pll", };
1095PNAME(mout_sclk_decon_vclk_b_p)	= { "mout_sclk_decon_vclk_a",
1096				    "mout_mfc_pll_div2", };
1097PNAME(mout_sclk_decon_p)	= { "oscclk", "mout_bus_pll_div2", };
1098PNAME(mout_sclk_decon_eclk_c_p)	= { "mout_sclk_decon_eclk_b",
1099				    "sclk_mphy_pll", };
1100PNAME(mout_sclk_decon_eclk_b_p)	= { "mout_sclk_decon_eclk_a",
1101				    "mout_mfc_pll_div2", };
1102
1103PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1104				       "sclk_mphy_pll", };
1105PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1106				       "mout_mfc_pll_div2", };
1107PNAME(mout_sclk_dsd_c_p)	= { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1108PNAME(mout_sclk_dsd_b_p)	= { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1109PNAME(mout_sclk_dsd_a_p)	= { "oscclk", "mout_mfc_pll_div2", };
1110
1111PNAME(mout_sclk_dsim0_c_p)	= { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1112PNAME(mout_sclk_dsim0_b_p)	= { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1113
1114PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1115				       "sclk_mphy_pll", };
1116PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1117				       "mout_mfc_pll_div2", };
1118PNAME(mout_sclk_dsim1_c_p)	= { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1119PNAME(mout_sclk_dsim1_b_p)	= { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1120
1121static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1122	/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1123	FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1124	FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1125	FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1126	FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1127};
1128
1129static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1130	/* MUX_SEL_MIF0 */
1131	MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1132			MUX_SEL_MIF0, 28, 1),
1133	MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1134			MUX_SEL_MIF0, 24, 1),
1135	MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1136			MUX_SEL_MIF0, 20, 1),
1137	MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1138			MUX_SEL_MIF0, 16, 1),
1139	MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1140			12, 1),
1141	MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1142			8, 1),
1143	MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1144			4, 1),
1145	MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1146			0, 1),
1147
1148	/* MUX_SEL_MIF1 */
1149	MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1150			MUX_SEL_MIF1, 24, 1),
1151	MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1152			MUX_SEL_MIF1, 20, 1),
1153	MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1154			MUX_SEL_MIF1, 16, 1),
1155	MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1156			MUX_SEL_MIF1, 12, 1),
1157	MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1158			MUX_SEL_MIF1, 8, 1),
1159	MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1160			MUX_SEL_MIF1, 4, 1),
1161
1162	/* MUX_SEL_MIF2 */
1163	MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1164			mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1165	MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1166			mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1167
1168	/* MUX_SEL_MIF3 */
1169	MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1170			mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1171	MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1172			mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1173
1174	/* MUX_SEL_MIF4 */
1175	MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1176			mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1177	MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1178			mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1179	MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1180			mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1181	MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1182			mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1183	MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1184			mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1185	MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1186			mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1187
1188	/* MUX_SEL_MIF5 */
1189	MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1190			mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1191	MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1192			mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1193	MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1194			mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1195	MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1196			MUX_SEL_MIF5, 8, 1),
1197	MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1198			MUX_SEL_MIF5, 4, 1),
1199	MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1200			MUX_SEL_MIF5, 0, 1),
1201
1202	/* MUX_SEL_MIF6 */
1203	MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1204			MUX_SEL_MIF6, 8, 1),
1205	MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1206			MUX_SEL_MIF6, 4, 1),
1207	MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1208			MUX_SEL_MIF6, 0, 1),
1209
1210	/* MUX_SEL_MIF7 */
1211	MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1212			mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1213	MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1214			mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1215	MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1216			mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1217	MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1218			MUX_SEL_MIF7, 8, 1),
1219	MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1220			MUX_SEL_MIF7, 4, 1),
1221	MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1222			MUX_SEL_MIF7, 0, 1),
1223};
1224
1225static const struct samsung_div_clock mif_div_clks[] __initconst = {
1226	/* DIV_MIF1 */
1227	DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1228			DIV_MIF1, 16, 2),
1229	DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1230			12, 2),
1231	DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1232			8, 2),
1233	DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1234			4, 4),
1235
1236	/* DIV_MIF2 */
1237	DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1238			DIV_MIF2, 20, 3),
1239	DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1240			DIV_MIF2, 16, 4),
1241	DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1242			DIV_MIF2, 12, 4),
1243	DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1244			"mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1245	DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1246			DIV_MIF2, 4, 2),
1247	DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1248			DIV_MIF2, 0, 3),
1249
1250	/* DIV_MIF3 */
1251	DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1252			DIV_MIF3, 16, 4),
1253	DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1254			DIV_MIF3, 4, 3),
1255	DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1256			DIV_MIF3, 0, 3),
1257
1258	/* DIV_MIF4 */
1259	DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1260			DIV_MIF4, 24, 4),
1261	DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1262			"mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1263	DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1264			DIV_MIF4, 16, 4),
1265	DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1266			DIV_MIF4, 12, 4),
1267	DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1268			"mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1269	DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1270			"mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1271	DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1272			"mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1273
1274	/* DIV_MIF5 */
1275	DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1276			0, 3),
1277};
1278
1279static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1280	/* ENABLE_ACLK_MIF0 */
1281	GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1282			19, CLK_IGNORE_UNUSED, 0),
1283	GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1284			18, CLK_IGNORE_UNUSED, 0),
1285	GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1286			17, CLK_IGNORE_UNUSED, 0),
1287	GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1288			16, CLK_IGNORE_UNUSED, 0),
1289	GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1290			15, CLK_IGNORE_UNUSED, 0),
1291	GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1292			14, CLK_IGNORE_UNUSED, 0),
1293	GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1294			ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1295	GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1296			ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1297	GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1298			ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1299	GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1300			ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1301	GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1302			ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1303	GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1304			ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1305	GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1306			ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1307	GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1308			ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1309	GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1310			ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1311	GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1312			ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1313	GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1314			ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1315	GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1316			ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1317	GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1318			ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1319	GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1320			ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1321
1322	/* ENABLE_ACLK_MIF1 */
1323	GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1324			"div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1325			CLK_IGNORE_UNUSED, 0),
1326	GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1327			"div_aclk_mif_200", ENABLE_ACLK_MIF1,
1328			27, CLK_IGNORE_UNUSED, 0),
1329	GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1330			"div_aclk_mif_133", ENABLE_ACLK_MIF1,
1331			26, CLK_IGNORE_UNUSED, 0),
1332	GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1333			"div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1334			25, CLK_IGNORE_UNUSED, 0),
1335	GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1336			"div_aclk_drex1", ENABLE_ACLK_MIF1,
1337			24, CLK_IGNORE_UNUSED, 0),
1338	GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1339			"div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1340			23, CLK_IGNORE_UNUSED, 0),
1341	GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1342			"div_aclk_drex0", ENABLE_ACLK_MIF1,
1343			22, CLK_IGNORE_UNUSED, 0),
1344	GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1345			"div_aclk_mif_133", ENABLE_ACLK_MIF1,
1346			21, CLK_IGNORE_UNUSED, 0),
1347	GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1348			"div_aclk_drex1", ENABLE_ACLK_MIF1,
1349			20, CLK_IGNORE_UNUSED, 0),
1350	GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1351			"div_aclk_mif_133", ENABLE_ACLK_MIF1,
1352			19, CLK_IGNORE_UNUSED, 0),
1353	GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1354			"div_aclk_drex1", ENABLE_ACLK_MIF1,
1355			18, CLK_IGNORE_UNUSED, 0),
1356	GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1357			"div_aclk_mif_133", ENABLE_ACLK_MIF1,
1358			17, CLK_IGNORE_UNUSED, 0),
1359	GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1360			"div_aclk_drex1", ENABLE_ACLK_MIF1,
1361			16, CLK_IGNORE_UNUSED, 0),
1362	GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1363			"div_aclk_mif_133", ENABLE_ACLK_MIF1,
1364			15, CLK_IGNORE_UNUSED, 0),
1365	GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1366			"div_aclk_drex0", ENABLE_ACLK_MIF1,
1367			14, CLK_IGNORE_UNUSED, 0),
1368	GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1369			"div_aclk_mif_133", ENABLE_ACLK_MIF1,
1370			13, CLK_IGNORE_UNUSED, 0),
1371	GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1372			"div_aclk_drex0", ENABLE_ACLK_MIF1,
1373			12, CLK_IGNORE_UNUSED, 0),
1374	GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1375			"div_aclk_mif_133", ENABLE_ACLK_MIF1,
1376			11, CLK_IGNORE_UNUSED, 0),
1377	GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1378			"div_aclk_drex0", ENABLE_ACLK_MIF1,
1379			10, CLK_IGNORE_UNUSED, 0),
1380	GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1381			ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1382	GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1383			ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1384	GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1385			ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1386	GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1387			ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1388	GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1389			ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1390	GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1391			ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1392	GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1393			ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1394	GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1395			ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1396	GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1397			ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1398	GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1399			0, CLK_IGNORE_UNUSED, 0),
1400
1401	/* ENABLE_ACLK_MIF2 */
1402	GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1403			ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1404	GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1405			ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1406	GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1407			ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1408	GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1409			ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1410	GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1411			ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1412	GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1413			ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1414	GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1415			ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1416	GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1417			"div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1418			CLK_IGNORE_UNUSED, 0),
1419	GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1420			"div_aclk_mif_400", ENABLE_ACLK_MIF2,
1421			5, CLK_IGNORE_UNUSED, 0),
1422	GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1423			ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1424	GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1425			"div_aclk_mif_200", ENABLE_ACLK_MIF2,
1426			3, CLK_IGNORE_UNUSED, 0),
1427	GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1428			"div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1429
1430	/* ENABLE_ACLK_MIF3 */
1431	GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1432			ENABLE_ACLK_MIF3, 4,
1433			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1434	GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1435			ENABLE_ACLK_MIF3, 1,
1436			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1437	GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1438			ENABLE_ACLK_MIF3, 0,
1439			CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1440
1441	/* ENABLE_PCLK_MIF */
1442	GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1443			ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1444	GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1445			ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1446	GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1447			ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1448	GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1449			ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1450	GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1451			ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1452	GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1453			ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1454	GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1455			"div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1456			CLK_IGNORE_UNUSED, 0),
1457	GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1458			ENABLE_PCLK_MIF, 19, 0, 0),
1459	GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1460			ENABLE_PCLK_MIF, 18, 0, 0),
1461	GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1462			"div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1463	GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1464			"div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1465	GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1466			"div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1467	GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1468			"div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1469	GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1470			"div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1471	GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1472			"div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1473	GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1474			ENABLE_PCLK_MIF, 11, 0, 0),
1475	GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1476			ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1477	GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1478			ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1479	GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1480			ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1481	GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1482			ENABLE_PCLK_MIF, 7, 0, 0),
1483	GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1484			ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1485	GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1486			ENABLE_PCLK_MIF, 5, 0, 0),
1487	GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1488			ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1489	GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1490			ENABLE_PCLK_MIF, 2, 0, 0),
1491	GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1492			ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1493
1494	/* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1495	GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1496			ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1497			CLK_IGNORE_UNUSED, 0),
1498
1499	/* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1500	GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1501			ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1502			CLK_IGNORE_UNUSED, 0),
1503
1504	/* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1505	GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1506			ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1507
1508	/* ENABLE_PCLK_MIF_SECURE_RTC */
1509	GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1510			ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1511
1512	/* ENABLE_SCLK_MIF */
1513	GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1514			ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1515	GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1516			"div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1517			14, CLK_IGNORE_UNUSED, 0),
1518	GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1519			ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1520	GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1521			ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1522	GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1523			"div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1524			7, CLK_IGNORE_UNUSED, 0),
1525	GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1526			"div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1527			6, CLK_IGNORE_UNUSED, 0),
1528	GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1529			"div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1530			5, CLK_IGNORE_UNUSED, 0),
1531	GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1532			ENABLE_SCLK_MIF, 4,
1533			CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1534	GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1535			ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1536	GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1537			ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1538	GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1539			ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1540	GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1541			ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1542};
1543
1544static const struct samsung_cmu_info mif_cmu_info __initconst = {
1545	.pll_clks		= mif_pll_clks,
1546	.nr_pll_clks		= ARRAY_SIZE(mif_pll_clks),
1547	.mux_clks		= mif_mux_clks,
1548	.nr_mux_clks		= ARRAY_SIZE(mif_mux_clks),
1549	.div_clks		= mif_div_clks,
1550	.nr_div_clks		= ARRAY_SIZE(mif_div_clks),
1551	.gate_clks		= mif_gate_clks,
1552	.nr_gate_clks		= ARRAY_SIZE(mif_gate_clks),
1553	.fixed_factor_clks	= mif_fixed_factor_clks,
1554	.nr_fixed_factor_clks	= ARRAY_SIZE(mif_fixed_factor_clks),
1555	.nr_clk_ids		= CLKS_NR_MIF,
1556	.clk_regs		= mif_clk_regs,
1557	.nr_clk_regs		= ARRAY_SIZE(mif_clk_regs),
1558};
1559
1560static void __init exynos5433_cmu_mif_init(struct device_node *np)
1561{
1562	samsung_cmu_register_one(np, &mif_cmu_info);
1563}
1564CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1565		exynos5433_cmu_mif_init);
1566
1567/*
1568 * Register offset definitions for CMU_PERIC
1569 */
1570#define DIV_PERIC			0x0600
1571#define DIV_STAT_PERIC			0x0700
1572#define ENABLE_ACLK_PERIC		0x0800
1573#define ENABLE_PCLK_PERIC0		0x0900
1574#define ENABLE_PCLK_PERIC1		0x0904
1575#define ENABLE_SCLK_PERIC		0x0A00
1576#define ENABLE_IP_PERIC0		0x0B00
1577#define ENABLE_IP_PERIC1		0x0B04
1578#define ENABLE_IP_PERIC2		0x0B08
1579
1580static const unsigned long peric_clk_regs[] __initconst = {
1581	DIV_PERIC,
1582	ENABLE_ACLK_PERIC,
1583	ENABLE_PCLK_PERIC0,
1584	ENABLE_PCLK_PERIC1,
1585	ENABLE_SCLK_PERIC,
1586	ENABLE_IP_PERIC0,
1587	ENABLE_IP_PERIC1,
1588	ENABLE_IP_PERIC2,
1589};
1590
1591static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
1592	/* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1593	{ ENABLE_PCLK_PERIC0, 0xe00ff000 },
1594	/* sclk: uart2-0 */
1595	{ ENABLE_SCLK_PERIC, 0x7 },
1596};
1597
1598static const struct samsung_div_clock peric_div_clks[] __initconst = {
1599	/* DIV_PERIC */
1600	DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1601	DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1602};
1603
1604static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1605	/* ENABLE_ACLK_PERIC */
1606	GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1607			ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1608	GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1609			ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1610	GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1611			ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1612	GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1613			ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1614
1615	/* ENABLE_PCLK_PERIC0 */
1616	GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1617			31, CLK_SET_RATE_PARENT, 0),
1618	GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1619			ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1620	GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1621			ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1622	GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1623			28, CLK_SET_RATE_PARENT, 0),
1624	GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1625			26, CLK_SET_RATE_PARENT, 0),
1626	GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1627			25, CLK_SET_RATE_PARENT, 0),
1628	GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1629			24, CLK_SET_RATE_PARENT, 0),
1630	GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1631			23, CLK_SET_RATE_PARENT, 0),
1632	GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1633			22, CLK_SET_RATE_PARENT, 0),
1634	GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1635			21, CLK_SET_RATE_PARENT, 0),
1636	GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1637			20, CLK_SET_RATE_PARENT, 0),
1638	GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1639			ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1640	GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1641			ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1642	GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1643			ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1644	GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1645			ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1646	GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1647			ENABLE_PCLK_PERIC0, 15,
1648			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1649	GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1650			14, CLK_SET_RATE_PARENT, 0),
1651	GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1652			13, CLK_SET_RATE_PARENT, 0),
1653	GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1654			12, CLK_SET_RATE_PARENT, 0),
1655	GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1656			ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1657	GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1658			ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1659	GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1660			ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1661	GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1662			ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1663	GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1664			7, CLK_SET_RATE_PARENT, 0),
1665	GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1666			6, CLK_SET_RATE_PARENT, 0),
1667	GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1668			5, CLK_SET_RATE_PARENT, 0),
1669	GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1670			4, CLK_SET_RATE_PARENT, 0),
1671	GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1672			3, CLK_SET_RATE_PARENT, 0),
1673	GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1674			2, CLK_SET_RATE_PARENT, 0),
1675	GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1676			1, CLK_SET_RATE_PARENT, 0),
1677	GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1678			0, CLK_SET_RATE_PARENT, 0),
1679
1680	/* ENABLE_PCLK_PERIC1 */
1681	GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1682			9, CLK_SET_RATE_PARENT, 0),
1683	GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1684			8, CLK_SET_RATE_PARENT, 0),
1685	GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1686			ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1687	GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1688			ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1689	GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1690			ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1691	GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1692			ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1693	GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1694			ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1695	GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1696			ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1697	GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1698			ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1699	GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1700			ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1701
1702	/* ENABLE_SCLK_PERIC */
1703	GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1704			ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1705	GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1706			ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1707	GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1708			19, CLK_SET_RATE_PARENT, 0),
1709	GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1710			18, CLK_SET_RATE_PARENT, 0),
1711	GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1712			17, 0, 0),
1713	GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1714			16, 0, 0),
1715	GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1716	GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1717			ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1718	GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1719			ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1720	GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1721			ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1722	GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1723			"ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1724			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1725	GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1726			ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1727	GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1728			ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1729	GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1730			ENABLE_SCLK_PERIC, 6,
1731			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1732	GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1733			5, CLK_SET_RATE_PARENT, 0),
1734	GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1735			4, CLK_SET_RATE_PARENT, 0),
1736	GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1737			3, CLK_SET_RATE_PARENT, 0),
1738	GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1739			ENABLE_SCLK_PERIC, 2,
1740			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1741	GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1742			ENABLE_SCLK_PERIC, 1,
1743			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1744	GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1745			ENABLE_SCLK_PERIC, 0,
1746			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1747};
1748
1749static const struct samsung_cmu_info peric_cmu_info __initconst = {
1750	.div_clks		= peric_div_clks,
1751	.nr_div_clks		= ARRAY_SIZE(peric_div_clks),
1752	.gate_clks		= peric_gate_clks,
1753	.nr_gate_clks		= ARRAY_SIZE(peric_gate_clks),
1754	.nr_clk_ids		= CLKS_NR_PERIC,
1755	.clk_regs		= peric_clk_regs,
1756	.nr_clk_regs		= ARRAY_SIZE(peric_clk_regs),
1757	.suspend_regs		= peric_suspend_regs,
1758	.nr_suspend_regs	= ARRAY_SIZE(peric_suspend_regs),
1759};
1760
1761static void __init exynos5433_cmu_peric_init(struct device_node *np)
1762{
1763	samsung_cmu_register_one(np, &peric_cmu_info);
1764}
1765
1766CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1767		exynos5433_cmu_peric_init);
1768
1769/*
1770 * Register offset definitions for CMU_PERIS
1771 */
1772#define ENABLE_ACLK_PERIS				0x0800
1773#define ENABLE_PCLK_PERIS				0x0900
1774#define ENABLE_PCLK_PERIS_SECURE_TZPC			0x0904
1775#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF		0x0908
1776#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF		0x090c
1777#define ENABLE_PCLK_PERIS_SECURE_TOPRTC			0x0910
1778#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF	0x0914
1779#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF	0x0918
1780#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF		0x091c
1781#define ENABLE_SCLK_PERIS				0x0a00
1782#define ENABLE_SCLK_PERIS_SECURE_SECKEY			0x0a04
1783#define ENABLE_SCLK_PERIS_SECURE_CHIPID			0x0a08
1784#define ENABLE_SCLK_PERIS_SECURE_TOPRTC			0x0a0c
1785#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE		0x0a10
1786#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT		0x0a14
1787#define ENABLE_SCLK_PERIS_SECURE_OTP_CON		0x0a18
1788#define ENABLE_IP_PERIS0				0x0b00
1789#define ENABLE_IP_PERIS1				0x0b04
1790#define ENABLE_IP_PERIS_SECURE_TZPC			0x0b08
1791#define ENABLE_IP_PERIS_SECURE_SECKEY			0x0b0c
1792#define ENABLE_IP_PERIS_SECURE_CHIPID			0x0b10
1793#define ENABLE_IP_PERIS_SECURE_TOPRTC			0x0b14
1794#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE		0x0b18
1795#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT		0x0b1c
1796#define ENABLE_IP_PERIS_SECURE_OTP_CON			0x0b20
1797
1798static const unsigned long peris_clk_regs[] __initconst = {
1799	ENABLE_ACLK_PERIS,
1800	ENABLE_PCLK_PERIS,
1801	ENABLE_PCLK_PERIS_SECURE_TZPC,
1802	ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1803	ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1804	ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1805	ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1806	ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1807	ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1808	ENABLE_SCLK_PERIS,
1809	ENABLE_SCLK_PERIS_SECURE_SECKEY,
1810	ENABLE_SCLK_PERIS_SECURE_CHIPID,
1811	ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1812	ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1813	ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1814	ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1815	ENABLE_IP_PERIS0,
1816	ENABLE_IP_PERIS1,
1817	ENABLE_IP_PERIS_SECURE_TZPC,
1818	ENABLE_IP_PERIS_SECURE_SECKEY,
1819	ENABLE_IP_PERIS_SECURE_CHIPID,
1820	ENABLE_IP_PERIS_SECURE_TOPRTC,
1821	ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1822	ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1823	ENABLE_IP_PERIS_SECURE_OTP_CON,
1824};
1825
1826static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1827	/* ENABLE_ACLK_PERIS */
1828	GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1829			ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1830	GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1831			ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1832	GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1833			ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1834
1835	/* ENABLE_PCLK_PERIS */
1836	GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1837			ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1838	GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1839			ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1840	GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1841			ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1842	GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1843			ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1844	GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1845			ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1846	GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1847			ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1848	GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1849			ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1850	GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1851			ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1852	GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1853			ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1854	GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1855			ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1856
1857	/* ENABLE_PCLK_PERIS_SECURE_TZPC */
1858	GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1859			ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1860	GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1861			ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1862	GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1863			ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1864	GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1865			ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1866	GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1867			ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1868	GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1869			ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1870	GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1871			ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1872	GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1873			ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1874	GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1875			ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1876	GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1877			ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1878	GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1879			ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1880	GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1881			ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1882	GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1883			ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1884
1885	/* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1886	GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1887			ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1888
1889	/* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1890	GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1891			ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1892
1893	/* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1894	GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1895			ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1896
1897	/* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1898	GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1899			"aclk_peris_66",
1900			ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1901
1902	/* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1903	GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1904			"aclk_peris_66",
1905			ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1906
1907	/* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1908	GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1909			"aclk_peris_66",
1910			ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1911
1912	/* ENABLE_SCLK_PERIS */
1913	GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1914			ENABLE_SCLK_PERIS, 10, 0, 0),
1915	GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1916			ENABLE_SCLK_PERIS, 4, 0, 0),
1917	GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1918			ENABLE_SCLK_PERIS, 3, 0, 0),
1919
1920	/* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1921	GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1922			ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1923
1924	/* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1925	GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1926			ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1927
1928	/* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1929	GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1930			ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1931
1932	/* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1933	GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1934			ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1935
1936	/* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1937	GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1938			ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1939
1940	/* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1941	GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1942			ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1943};
1944
1945static const struct samsung_cmu_info peris_cmu_info __initconst = {
1946	.gate_clks		= peris_gate_clks,
1947	.nr_gate_clks		= ARRAY_SIZE(peris_gate_clks),
1948	.nr_clk_ids		= CLKS_NR_PERIS,
1949	.clk_regs		= peris_clk_regs,
1950	.nr_clk_regs		= ARRAY_SIZE(peris_clk_regs),
1951};
1952
1953static void __init exynos5433_cmu_peris_init(struct device_node *np)
1954{
1955	samsung_cmu_register_one(np, &peris_cmu_info);
1956}
1957
1958CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1959		exynos5433_cmu_peris_init);
1960
1961/*
1962 * Register offset definitions for CMU_FSYS
1963 */
1964#define MUX_SEL_FSYS0			0x0200
1965#define MUX_SEL_FSYS1			0x0204
1966#define MUX_SEL_FSYS2			0x0208
1967#define MUX_SEL_FSYS3			0x020c
1968#define MUX_SEL_FSYS4			0x0210
1969#define MUX_ENABLE_FSYS0		0x0300
1970#define MUX_ENABLE_FSYS1		0x0304
1971#define MUX_ENABLE_FSYS2		0x0308
1972#define MUX_ENABLE_FSYS3		0x030c
1973#define MUX_ENABLE_FSYS4		0x0310
1974#define MUX_STAT_FSYS0			0x0400
1975#define MUX_STAT_FSYS1			0x0404
1976#define MUX_STAT_FSYS2			0x0408
1977#define MUX_STAT_FSYS3			0x040c
1978#define MUX_STAT_FSYS4			0x0410
1979#define MUX_IGNORE_FSYS2		0x0508
1980#define MUX_IGNORE_FSYS3		0x050c
1981#define ENABLE_ACLK_FSYS0		0x0800
1982#define ENABLE_ACLK_FSYS1		0x0804
1983#define ENABLE_PCLK_FSYS		0x0900
1984#define ENABLE_SCLK_FSYS		0x0a00
1985#define ENABLE_IP_FSYS0			0x0b00
1986#define ENABLE_IP_FSYS1			0x0b04
1987
1988/* list of all parent clock list */
1989PNAME(mout_sclk_ufs_mphy_user_p)	= { "oscclk", "sclk_ufs_mphy", };
1990PNAME(mout_aclk_fsys_200_user_p)	= { "oscclk", "aclk_fsys_200", };
1991PNAME(mout_sclk_pcie_100_user_p)	= { "oscclk", "sclk_pcie_100_fsys",};
1992PNAME(mout_sclk_ufsunipro_user_p)	= { "oscclk", "sclk_ufsunipro_fsys",};
1993PNAME(mout_sclk_mmc2_user_p)		= { "oscclk", "sclk_mmc2_fsys", };
1994PNAME(mout_sclk_mmc1_user_p)		= { "oscclk", "sclk_mmc1_fsys", };
1995PNAME(mout_sclk_mmc0_user_p)		= { "oscclk", "sclk_mmc0_fsys", };
1996PNAME(mout_sclk_usbhost30_user_p)	= { "oscclk", "sclk_usbhost30_fsys",};
1997PNAME(mout_sclk_usbdrd30_user_p)	= { "oscclk", "sclk_usbdrd30_fsys", };
1998
1999PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
2000		= { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
2001PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
2002		= { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
2003PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
2004		= { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
2005PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
2006		= { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
2007PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
2008		= { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
2009PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
2010		= { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
2011PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
2012		= { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
2013PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
2014		= { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
2015PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
2016		= { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
2017PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
2018		= { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
2019PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
2020		= { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
2021PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
2022		= { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
2023PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
2024		= { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2025PNAME(mout_sclk_mphy_p)
2026		= { "mout_sclk_ufs_mphy_user",
2027			    "mout_phyclk_lli_mphy_to_ufs_user", };
2028
2029static const unsigned long fsys_clk_regs[] __initconst = {
2030	MUX_SEL_FSYS0,
2031	MUX_SEL_FSYS1,
2032	MUX_SEL_FSYS2,
2033	MUX_SEL_FSYS3,
2034	MUX_SEL_FSYS4,
2035	MUX_ENABLE_FSYS0,
2036	MUX_ENABLE_FSYS1,
2037	MUX_ENABLE_FSYS2,
2038	MUX_ENABLE_FSYS3,
2039	MUX_ENABLE_FSYS4,
2040	MUX_IGNORE_FSYS2,
2041	MUX_IGNORE_FSYS3,
2042	ENABLE_ACLK_FSYS0,
2043	ENABLE_ACLK_FSYS1,
2044	ENABLE_PCLK_FSYS,
2045	ENABLE_SCLK_FSYS,
2046	ENABLE_IP_FSYS0,
2047	ENABLE_IP_FSYS1,
2048};
2049
2050static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
2051	{ MUX_SEL_FSYS0, 0 },
2052	{ MUX_SEL_FSYS1, 0 },
2053	{ MUX_SEL_FSYS2, 0 },
2054	{ MUX_SEL_FSYS3, 0 },
2055	{ MUX_SEL_FSYS4, 0 },
2056};
2057
2058static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
2059	/* PHY clocks from USBDRD30_PHY */
2060	FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2061			"phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2062			0, 60000000),
2063	FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2064			"phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2065			0, 125000000),
2066	/* PHY clocks from USBHOST30_PHY */
2067	FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2068			"phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2069			0, 60000000),
2070	FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2071			"phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2072			0, 125000000),
2073	/* PHY clocks from USBHOST20_PHY */
2074	FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2075			"phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2076	FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2077			"phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2078	FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2079			"phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2080			0, 48000000),
2081	FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2082			"phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2083			60000000),
2084	/* PHY clocks from UFS_PHY */
2085	FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2086			NULL, 0, 300000000),
2087	FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2088			NULL, 0, 300000000),
2089	FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2090			NULL, 0, 300000000),
2091	FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2092			NULL, 0, 300000000),
2093	/* PHY clocks from LLI_PHY */
2094	FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2095			NULL, 0, 26000000),
2096};
2097
2098static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2099	/* MUX_SEL_FSYS0 */
2100	MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2101			mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2102	MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2103			mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2104
2105	/* MUX_SEL_FSYS1 */
2106	MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2107			mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2108	MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2109			mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2110	MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2111			mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2112	MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2113			mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2114	MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2115			mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2116	MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2117			mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2118	MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2119			mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2120
2121	/* MUX_SEL_FSYS2 */
2122	MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2123			"mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2124			mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2125			MUX_SEL_FSYS2, 28, 1),
2126	MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2127			"mout_phyclk_usbhost30_uhost30_phyclock_user",
2128			mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2129			MUX_SEL_FSYS2, 24, 1),
2130	MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2131			"mout_phyclk_usbhost20_phy_hsic1",
2132			mout_phyclk_usbhost20_phy_hsic1_p,
2133			MUX_SEL_FSYS2, 20, 1),
2134	MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2135			"mout_phyclk_usbhost20_phy_clk48mohci_user",
2136			mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2137			MUX_SEL_FSYS2, 16, 1),
2138	MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2139			"mout_phyclk_usbhost20_phy_phyclock_user",
2140			mout_phyclk_usbhost20_phy_phyclock_user_p,
2141			MUX_SEL_FSYS2, 12, 1),
2142	MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2143			"mout_phyclk_usbhost20_phy_freeclk_user",
2144			mout_phyclk_usbhost20_phy_freeclk_user_p,
2145			MUX_SEL_FSYS2, 8, 1),
2146	MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2147			"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2148			mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2149			MUX_SEL_FSYS2, 4, 1),
2150	MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2151			"mout_phyclk_usbdrd30_udrd30_phyclock_user",
2152			mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2153			MUX_SEL_FSYS2, 0, 1),
2154
2155	/* MUX_SEL_FSYS3 */
2156	MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2157			"mout_phyclk_ufs_rx1_symbol_user",
2158			mout_phyclk_ufs_rx1_symbol_user_p,
2159			MUX_SEL_FSYS3, 16, 1),
2160	MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2161			"mout_phyclk_ufs_rx0_symbol_user",
2162			mout_phyclk_ufs_rx0_symbol_user_p,
2163			MUX_SEL_FSYS3, 12, 1),
2164	MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2165			"mout_phyclk_ufs_tx1_symbol_user",
2166			mout_phyclk_ufs_tx1_symbol_user_p,
2167			MUX_SEL_FSYS3, 8, 1),
2168	MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2169			"mout_phyclk_ufs_tx0_symbol_user",
2170			mout_phyclk_ufs_tx0_symbol_user_p,
2171			MUX_SEL_FSYS3, 4, 1),
2172	MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2173			"mout_phyclk_lli_mphy_to_ufs_user",
2174			mout_phyclk_lli_mphy_to_ufs_user_p,
2175			MUX_SEL_FSYS3, 0, 1),
2176
2177	/* MUX_SEL_FSYS4 */
2178	MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2179			MUX_SEL_FSYS4, 0, 1),
2180};
2181
2182static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2183	/* ENABLE_ACLK_FSYS0 */
2184	GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2185			ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2186	GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2187			ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2188	GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2189			ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2190	GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2191			ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2192	GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2193			ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2194	GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2195			ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2196	GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2197			ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2198	GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2199			ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2200	GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2201			ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2202	GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2203			ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2204	GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2205			ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2206
2207	/* ENABLE_ACLK_FSYS1 */
2208	GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2209			ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2210	GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2211			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2212			26, CLK_IGNORE_UNUSED, 0),
2213	GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2214			ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2215	GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2216			ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2217	GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2218			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2219			22, CLK_IGNORE_UNUSED, 0),
2220	GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2221			ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2222	GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2223			ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2224	GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2225			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2226			13, 0, 0),
2227	GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2228			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2229			12, 0, 0),
2230	GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2231			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2232			11, CLK_IGNORE_UNUSED, 0),
2233	GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2234			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2235			10, CLK_IGNORE_UNUSED, 0),
2236	GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2237			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2238			9, CLK_IGNORE_UNUSED, 0),
2239	GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2240			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2241			8, CLK_IGNORE_UNUSED, 0),
2242	GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2243			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2244			7, CLK_IGNORE_UNUSED, 0),
2245	GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2246			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2247			6, CLK_IGNORE_UNUSED, 0),
2248	GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2249			ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2250	GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2251			ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2252	GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2253			ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2254	GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2255			ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2256	GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2257			ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2258	GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2259			ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2260
2261	/* ENABLE_PCLK_FSYS */
2262	GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2263			ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2264	GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2265			ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2266	GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2267			ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2268	GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2269			ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2270	GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2271			ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2272	GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2273			ENABLE_PCLK_FSYS, 5, 0, 0),
2274	GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2275			"mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2276	GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2277			"mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2278	GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2279			ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2280	GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2281			ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2282	GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2283			"mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2284			0, CLK_IGNORE_UNUSED, 0),
2285
2286	/* ENABLE_SCLK_FSYS */
2287	GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2288			ENABLE_SCLK_FSYS, 21, 0, 0),
2289	GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2290			"phyclk_usbhost30_uhost30_pipe_pclk",
2291			"mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2292			ENABLE_SCLK_FSYS, 18, 0, 0),
2293	GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2294			"phyclk_usbhost30_uhost30_phyclock",
2295			"mout_phyclk_usbhost30_uhost30_phyclock_user",
2296			ENABLE_SCLK_FSYS, 17, 0, 0),
2297	GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2298			"mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2299			16, 0, 0),
2300	GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2301			"mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2302			15, 0, 0),
2303	GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2304			"mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2305			14, 0, 0),
2306	GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2307			"mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2308			13, 0, 0),
2309	GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2310			"mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2311			12, 0, 0),
2312	GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2313			"phyclk_usbhost20_phy_clk48mohci",
2314			"mout_phyclk_usbhost20_phy_clk48mohci_user",
2315			ENABLE_SCLK_FSYS, 11, 0, 0),
2316	GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2317			"phyclk_usbhost20_phy_phyclock",
2318			"mout_phyclk_usbhost20_phy_phyclock_user",
2319			ENABLE_SCLK_FSYS, 10, 0, 0),
2320	GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2321			"phyclk_usbhost20_phy_freeclk",
2322			"mout_phyclk_usbhost20_phy_freeclk_user",
2323			ENABLE_SCLK_FSYS, 9, 0, 0),
2324	GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2325			"phyclk_usbdrd30_udrd30_pipe_pclk",
2326			"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2327			ENABLE_SCLK_FSYS, 8, 0, 0),
2328	GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2329			"phyclk_usbdrd30_udrd30_phyclock",
2330			"mout_phyclk_usbdrd30_udrd30_phyclock_user",
2331			ENABLE_SCLK_FSYS, 7, 0, 0),
2332	GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2333			ENABLE_SCLK_FSYS, 6, 0, 0),
2334	GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2335			ENABLE_SCLK_FSYS, 5, 0, 0),
2336	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2337			ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2338	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2339			ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2340	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2341			ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2342	GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2343			ENABLE_SCLK_FSYS, 1, 0, 0),
2344	GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2345			ENABLE_SCLK_FSYS, 0, 0, 0),
2346
2347	/* ENABLE_IP_FSYS0 */
2348	GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2349	GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2350	GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2351};
2352
2353static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2354	.mux_clks		= fsys_mux_clks,
2355	.nr_mux_clks		= ARRAY_SIZE(fsys_mux_clks),
2356	.gate_clks		= fsys_gate_clks,
2357	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),
2358	.fixed_clks		= fsys_fixed_clks,
2359	.nr_fixed_clks		= ARRAY_SIZE(fsys_fixed_clks),
2360	.nr_clk_ids		= CLKS_NR_FSYS,
2361	.clk_regs		= fsys_clk_regs,
2362	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),
2363	.suspend_regs		= fsys_suspend_regs,
2364	.nr_suspend_regs	= ARRAY_SIZE(fsys_suspend_regs),
2365	.clk_name		= "aclk_fsys_200",
2366};
2367
2368/*
2369 * Register offset definitions for CMU_G2D
2370 */
2371#define MUX_SEL_G2D0				0x0200
2372#define MUX_SEL_ENABLE_G2D0			0x0300
2373#define MUX_SEL_STAT_G2D0			0x0400
2374#define DIV_G2D					0x0600
2375#define DIV_STAT_G2D				0x0700
2376#define DIV_ENABLE_ACLK_G2D			0x0800
2377#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D	0x0804
2378#define DIV_ENABLE_PCLK_G2D			0x0900
2379#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D	0x0904
2380#define DIV_ENABLE_IP_G2D0			0x0b00
2381#define DIV_ENABLE_IP_G2D1			0x0b04
2382#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D	0x0b08
2383
2384static const unsigned long g2d_clk_regs[] __initconst = {
2385	MUX_SEL_G2D0,
2386	MUX_SEL_ENABLE_G2D0,
2387	DIV_G2D,
2388	DIV_ENABLE_ACLK_G2D,
2389	DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2390	DIV_ENABLE_PCLK_G2D,
2391	DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2392	DIV_ENABLE_IP_G2D0,
2393	DIV_ENABLE_IP_G2D1,
2394	DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2395};
2396
2397static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
2398	{ MUX_SEL_G2D0, 0 },
2399};
2400
2401/* list of all parent clock list */
2402PNAME(mout_aclk_g2d_266_user_p)		= { "oscclk", "aclk_g2d_266", };
2403PNAME(mout_aclk_g2d_400_user_p)		= { "oscclk", "aclk_g2d_400", };
2404
2405static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2406	/* MUX_SEL_G2D0 */
2407	MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2408			mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2409	MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2410			mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2411};
2412
2413static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2414	/* DIV_G2D */
2415	DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2416			DIV_G2D, 0, 2),
2417};
2418
2419static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2420	/* DIV_ENABLE_ACLK_G2D */
2421	GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2422			DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2423	GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2424			DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2425	GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2426			DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2427	GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2428			DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2429	GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2430			DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2431	GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2432			"mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2433			7, 0, 0),
2434	GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2435			DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2436	GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2437			DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2438	GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2439			DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2440	GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2441			DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2442	GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2443			DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2444	GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2445			DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2446	GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2447			DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2448
2449	/* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2450	GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2451		DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2452
2453	/* DIV_ENABLE_PCLK_G2D */
2454	GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2455			DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2456	GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2457			DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2458	GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2459			DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2460	GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2461			DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2462	GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2463			DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2464	GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2465			DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2466	GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2467			DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2468	GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2469			0, 0, 0),
2470
2471	/* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2472	GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2473		DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2474};
2475
2476static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2477	.mux_clks		= g2d_mux_clks,
2478	.nr_mux_clks		= ARRAY_SIZE(g2d_mux_clks),
2479	.div_clks		= g2d_div_clks,
2480	.nr_div_clks		= ARRAY_SIZE(g2d_div_clks),
2481	.gate_clks		= g2d_gate_clks,
2482	.nr_gate_clks		= ARRAY_SIZE(g2d_gate_clks),
2483	.nr_clk_ids		= CLKS_NR_G2D,
2484	.clk_regs		= g2d_clk_regs,
2485	.nr_clk_regs		= ARRAY_SIZE(g2d_clk_regs),
2486	.suspend_regs		= g2d_suspend_regs,
2487	.nr_suspend_regs	= ARRAY_SIZE(g2d_suspend_regs),
2488	.clk_name		= "aclk_g2d_400",
2489};
2490
2491/*
2492 * Register offset definitions for CMU_DISP
2493 */
2494#define DISP_PLL_LOCK			0x0000
2495#define DISP_PLL_CON0			0x0100
2496#define DISP_PLL_CON1			0x0104
2497#define DISP_PLL_FREQ_DET		0x0108
2498#define MUX_SEL_DISP0			0x0200
2499#define MUX_SEL_DISP1			0x0204
2500#define MUX_SEL_DISP2			0x0208
2501#define MUX_SEL_DISP3			0x020c
2502#define MUX_SEL_DISP4			0x0210
2503#define MUX_ENABLE_DISP0		0x0300
2504#define MUX_ENABLE_DISP1		0x0304
2505#define MUX_ENABLE_DISP2		0x0308
2506#define MUX_ENABLE_DISP3		0x030c
2507#define MUX_ENABLE_DISP4		0x0310
2508#define MUX_STAT_DISP0			0x0400
2509#define MUX_STAT_DISP1			0x0404
2510#define MUX_STAT_DISP2			0x0408
2511#define MUX_STAT_DISP3			0x040c
2512#define MUX_STAT_DISP4			0x0410
2513#define MUX_IGNORE_DISP2		0x0508
2514#define DIV_DISP			0x0600
2515#define DIV_DISP_PLL_FREQ_DET		0x0604
2516#define DIV_STAT_DISP			0x0700
2517#define DIV_STAT_DISP_PLL_FREQ_DET	0x0704
2518#define ENABLE_ACLK_DISP0		0x0800
2519#define ENABLE_ACLK_DISP1		0x0804
2520#define ENABLE_PCLK_DISP		0x0900
2521#define ENABLE_SCLK_DISP		0x0a00
2522#define ENABLE_IP_DISP0			0x0b00
2523#define ENABLE_IP_DISP1			0x0b04
2524#define CLKOUT_CMU_DISP			0x0c00
2525#define CLKOUT_CMU_DISP_DIV_STAT	0x0c04
2526
2527static const unsigned long disp_clk_regs[] __initconst = {
2528	DISP_PLL_LOCK,
2529	DISP_PLL_CON0,
2530	DISP_PLL_CON1,
2531	DISP_PLL_FREQ_DET,
2532	MUX_SEL_DISP0,
2533	MUX_SEL_DISP1,
2534	MUX_SEL_DISP2,
2535	MUX_SEL_DISP3,
2536	MUX_SEL_DISP4,
2537	MUX_ENABLE_DISP0,
2538	MUX_ENABLE_DISP1,
2539	MUX_ENABLE_DISP2,
2540	MUX_ENABLE_DISP3,
2541	MUX_ENABLE_DISP4,
2542	MUX_IGNORE_DISP2,
2543	DIV_DISP,
2544	DIV_DISP_PLL_FREQ_DET,
2545	ENABLE_ACLK_DISP0,
2546	ENABLE_ACLK_DISP1,
2547	ENABLE_PCLK_DISP,
2548	ENABLE_SCLK_DISP,
2549	ENABLE_IP_DISP0,
2550	ENABLE_IP_DISP1,
2551	CLKOUT_CMU_DISP,
2552	CLKOUT_CMU_DISP_DIV_STAT,
2553};
2554
2555static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
2556	/* PLL has to be enabled for suspend */
2557	{ DISP_PLL_CON0, 0x85f40502 },
2558	/* ignore status of external PHY muxes during suspend to avoid hangs */
2559	{ MUX_IGNORE_DISP2, 0x00111111 },
2560	{ MUX_SEL_DISP0, 0 },
2561	{ MUX_SEL_DISP1, 0 },
2562	{ MUX_SEL_DISP2, 0 },
2563	{ MUX_SEL_DISP3, 0 },
2564	{ MUX_SEL_DISP4, 0 },
2565};
2566
2567/* list of all parent clock list */
2568PNAME(mout_disp_pll_p)			= { "oscclk", "fout_disp_pll", };
2569PNAME(mout_sclk_dsim1_user_p)		= { "oscclk", "sclk_dsim1_disp", };
2570PNAME(mout_sclk_dsim0_user_p)		= { "oscclk", "sclk_dsim0_disp", };
2571PNAME(mout_sclk_dsd_user_p)		= { "oscclk", "sclk_dsd_disp", };
2572PNAME(mout_sclk_decon_tv_eclk_user_p)	= { "oscclk",
2573					    "sclk_decon_tv_eclk_disp", };
2574PNAME(mout_sclk_decon_vclk_user_p)	= { "oscclk",
2575					    "sclk_decon_vclk_disp", };
2576PNAME(mout_sclk_decon_eclk_user_p)	= { "oscclk",
2577					    "sclk_decon_eclk_disp", };
2578PNAME(mout_sclk_decon_tv_vlkc_user_p)	= { "oscclk",
2579					    "sclk_decon_tv_vclk_disp", };
2580PNAME(mout_aclk_disp_333_user_p)	= { "oscclk", "aclk_disp_333", };
2581
2582PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p)	= { "oscclk",
2583					"phyclk_mipidphy1_bitclkdiv8_phy", };
2584PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p)	= { "oscclk",
2585					"phyclk_mipidphy1_rxclkesc0_phy", };
2586PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p)	= { "oscclk",
2587					"phyclk_mipidphy0_bitclkdiv8_phy", };
2588PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p)	= { "oscclk",
2589					"phyclk_mipidphy0_rxclkesc0_phy", };
2590PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p)	= { "oscclk",
2591					"phyclk_hdmiphy_tmds_clko_phy", };
2592PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p)	= { "oscclk",
2593					"phyclk_hdmiphy_pixel_clko_phy", };
2594
2595PNAME(mout_sclk_dsim0_p)		= { "mout_disp_pll",
2596					    "mout_sclk_dsim0_user", };
2597PNAME(mout_sclk_decon_tv_eclk_p)	= { "mout_disp_pll",
2598					    "mout_sclk_decon_tv_eclk_user", };
2599PNAME(mout_sclk_decon_vclk_p)		= { "mout_disp_pll",
2600					    "mout_sclk_decon_vclk_user", };
2601PNAME(mout_sclk_decon_eclk_p)		= { "mout_disp_pll",
2602					    "mout_sclk_decon_eclk_user", };
2603
2604PNAME(mout_sclk_dsim1_b_disp_p)		= { "mout_sclk_dsim1_a_disp",
2605					    "mout_sclk_dsim1_user", };
2606PNAME(mout_sclk_decon_tv_vclk_c_disp_p)	= {
2607				"mout_phyclk_hdmiphy_pixel_clko_user",
2608				"mout_sclk_decon_tv_vclk_b_disp", };
2609PNAME(mout_sclk_decon_tv_vclk_b_disp_p)	= { "mout_sclk_decon_tv_vclk_a_disp",
2610					    "mout_sclk_decon_tv_vclk_user", };
2611
2612static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2613	PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2614		DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates),
2615};
2616
2617static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2618	/*
2619	 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2620	 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2621	 * and sclk_decon_{vclk|tv_vclk}.
2622	 */
2623	FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2624			1, 2, 0),
2625	FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2626			1, 2, 0),
2627};
2628
2629static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2630	/* PHY clocks from MIPI_DPHY1 */
2631	FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2632	FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2633	/* PHY clocks from MIPI_DPHY0 */
2634	FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
2635			NULL, 0, 188000000),
2636	FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
2637			NULL, 0, 100000000),
2638	/* PHY clocks from HDMI_PHY */
2639	FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2640			NULL, 0, 300000000),
2641	FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2642			NULL, 0, 166000000),
2643};
2644
2645static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2646	/* MUX_SEL_DISP0 */
2647	MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2648			0, 1),
2649
2650	/* MUX_SEL_DISP1 */
2651	MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2652			mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2653	MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2654			mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2655	MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2656			MUX_SEL_DISP1, 20, 1),
2657	MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2658			mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2659	MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2660			mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2661	MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2662			mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2663	MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2664			mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2665	MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2666			mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2667
2668	/* MUX_SEL_DISP2 */
2669	MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2670			"mout_phyclk_mipidphy1_bitclkdiv8_user",
2671			mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2672			20, 1),
2673	MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2674			"mout_phyclk_mipidphy1_rxclkesc0_user",
2675			mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2676			16, 1),
2677	MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2678			"mout_phyclk_mipidphy0_bitclkdiv8_user",
2679			mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2680			12, 1),
2681	MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2682			"mout_phyclk_mipidphy0_rxclkesc0_user",
2683			mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2684			8, 1),
2685	MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2686			"mout_phyclk_hdmiphy_tmds_clko_user",
2687			mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2688			4, 1),
2689	MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2690			"mout_phyclk_hdmiphy_pixel_clko_user",
2691			mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2692			0, 1),
2693
2694	/* MUX_SEL_DISP3 */
2695	MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2696			MUX_SEL_DISP3, 12, 1),
2697	MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2698			mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2699	MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2700			mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2701	MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2702			mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2703
2704	/* MUX_SEL_DISP4 */
2705	MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2706			mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2707	MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2708			mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2709	MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2710			"mout_sclk_decon_tv_vclk_c_disp",
2711			mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2712	MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2713			"mout_sclk_decon_tv_vclk_b_disp",
2714			mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2715	MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2716			"mout_sclk_decon_tv_vclk_a_disp",
2717			mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2718};
2719
2720static const struct samsung_div_clock disp_div_clks[] __initconst = {
2721	/* DIV_DISP */
2722	DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2723			"mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2724	DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2725			"mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2726	DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2727			DIV_DISP, 16, 3),
2728	DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2729			"mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2730	DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2731			"mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2732	DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2733			"mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2734	DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2735			DIV_DISP, 0, 2),
2736};
2737
2738static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2739	/* ENABLE_ACLK_DISP0 */
2740	GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2741			ENABLE_ACLK_DISP0, 2, 0, 0),
2742	GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2743			ENABLE_ACLK_DISP0, 0, 0, 0),
2744
2745	/* ENABLE_ACLK_DISP1 */
2746	GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2747			ENABLE_ACLK_DISP1, 25, 0, 0),
2748	GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2749			ENABLE_ACLK_DISP1, 24, 0, 0),
2750	GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2751			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2752	GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2753			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2754	GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2755			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2756	GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2757			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2758	GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2759			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2760	GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2761			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2762	GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2763			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2764	GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2765			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2766	GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2767			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2768	GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2769			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2770	GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2771			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2772	GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2773			"div_pclk_disp", ENABLE_ACLK_DISP1,
2774			12, CLK_IGNORE_UNUSED, 0),
2775	GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2776			"div_pclk_disp", ENABLE_ACLK_DISP1,
2777			11, CLK_IGNORE_UNUSED, 0),
2778	GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2779			"div_pclk_disp", ENABLE_ACLK_DISP1,
2780			10, CLK_IGNORE_UNUSED, 0),
2781	GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2782			ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2783	GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2784			ENABLE_ACLK_DISP1, 7, 0, 0),
2785	GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2786			ENABLE_ACLK_DISP1, 6, 0, 0),
2787	GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2788			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2789	GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2790			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2791	GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2792			ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2793	GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2794			ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2795	GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2796			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2797			CLK_IGNORE_UNUSED, 0),
2798	GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2799			"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2800			0, CLK_IGNORE_UNUSED, 0),
2801
2802	/* ENABLE_PCLK_DISP */
2803	GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2804			ENABLE_PCLK_DISP, 23, 0, 0),
2805	GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2806			ENABLE_PCLK_DISP, 22, 0, 0),
2807	GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2808			ENABLE_PCLK_DISP, 21, 0, 0),
2809	GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2810			ENABLE_PCLK_DISP, 20, 0, 0),
2811	GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2812			ENABLE_PCLK_DISP, 19, 0, 0),
2813	GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2814			ENABLE_PCLK_DISP, 18, 0, 0),
2815	GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2816			ENABLE_PCLK_DISP, 17, 0, 0),
2817	GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2818			ENABLE_PCLK_DISP, 16, 0, 0),
2819	GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2820			ENABLE_PCLK_DISP, 15, 0, 0),
2821	GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2822			ENABLE_PCLK_DISP, 14, 0, 0),
2823	GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2824			ENABLE_PCLK_DISP, 13, 0, 0),
2825	GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2826			ENABLE_PCLK_DISP, 12, 0, 0),
2827	GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2828			ENABLE_PCLK_DISP, 11, 0, 0),
2829	GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2830			ENABLE_PCLK_DISP, 10, 0, 0),
2831	GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2832			ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2833	GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2834			ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2835	GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2836			ENABLE_PCLK_DISP, 7, 0, 0),
2837	GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2838			ENABLE_PCLK_DISP, 6, 0, 0),
2839	GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2840			ENABLE_PCLK_DISP, 5, 0, 0),
2841	GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2842			ENABLE_PCLK_DISP, 3, 0, 0),
2843	GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2844			ENABLE_PCLK_DISP, 2, 0, 0),
2845	GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2846			ENABLE_PCLK_DISP, 1, 0, 0),
2847	GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2848			ENABLE_PCLK_DISP, 0, 0, 0),
2849
2850	/* ENABLE_SCLK_DISP */
2851	GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2852			"mout_phyclk_mipidphy1_bitclkdiv8_user",
2853			ENABLE_SCLK_DISP, 26, 0, 0),
2854	GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2855			"mout_phyclk_mipidphy1_rxclkesc0_user",
2856			ENABLE_SCLK_DISP, 25, 0, 0),
2857	GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2858			"sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2859	GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2860			"sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2861	GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2862			ENABLE_SCLK_DISP, 22, 0, 0),
2863	GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2864			"div_sclk_decon_tv_vclk_disp",
2865			ENABLE_SCLK_DISP, 21, 0, 0),
2866	GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2867			"mout_phyclk_mipidphy0_bitclkdiv8_user",
2868			ENABLE_SCLK_DISP, 15, 0, 0),
2869	GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2870			"mout_phyclk_mipidphy0_rxclkesc0_user",
2871			ENABLE_SCLK_DISP, 14, 0, 0),
2872	GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2873			"mout_phyclk_hdmiphy_tmds_clko_user",
2874			ENABLE_SCLK_DISP, 13, 0, 0),
2875	GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2876			"sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2877	GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2878			"sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2879	GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2880			"sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2881	GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2882			"sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2883	GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2884			ENABLE_SCLK_DISP, 7, 0, 0),
2885	GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2886			ENABLE_SCLK_DISP, 6, 0, 0),
2887	GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2888			ENABLE_SCLK_DISP, 5, 0, 0),
2889	GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2890			"div_sclk_decon_tv_eclk_disp",
2891			ENABLE_SCLK_DISP, 4, 0, 0),
2892	GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2893			"div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2894	GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2895			"div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2896};
2897
2898static const struct samsung_cmu_info disp_cmu_info __initconst = {
2899	.pll_clks		= disp_pll_clks,
2900	.nr_pll_clks		= ARRAY_SIZE(disp_pll_clks),
2901	.mux_clks		= disp_mux_clks,
2902	.nr_mux_clks		= ARRAY_SIZE(disp_mux_clks),
2903	.div_clks		= disp_div_clks,
2904	.nr_div_clks		= ARRAY_SIZE(disp_div_clks),
2905	.gate_clks		= disp_gate_clks,
2906	.nr_gate_clks		= ARRAY_SIZE(disp_gate_clks),
2907	.fixed_clks		= disp_fixed_clks,
2908	.nr_fixed_clks		= ARRAY_SIZE(disp_fixed_clks),
2909	.fixed_factor_clks	= disp_fixed_factor_clks,
2910	.nr_fixed_factor_clks	= ARRAY_SIZE(disp_fixed_factor_clks),
2911	.nr_clk_ids		= CLKS_NR_DISP,
2912	.clk_regs		= disp_clk_regs,
2913	.nr_clk_regs		= ARRAY_SIZE(disp_clk_regs),
2914	.suspend_regs		= disp_suspend_regs,
2915	.nr_suspend_regs	= ARRAY_SIZE(disp_suspend_regs),
2916	.clk_name		= "aclk_disp_333",
2917};
2918
2919/*
2920 * Register offset definitions for CMU_AUD
2921 */
2922#define MUX_SEL_AUD0			0x0200
2923#define MUX_SEL_AUD1			0x0204
2924#define MUX_ENABLE_AUD0			0x0300
2925#define MUX_ENABLE_AUD1			0x0304
2926#define MUX_STAT_AUD0			0x0400
2927#define DIV_AUD0			0x0600
2928#define DIV_AUD1			0x0604
2929#define DIV_STAT_AUD0			0x0700
2930#define DIV_STAT_AUD1			0x0704
2931#define ENABLE_ACLK_AUD			0x0800
2932#define ENABLE_PCLK_AUD			0x0900
2933#define ENABLE_SCLK_AUD0		0x0a00
2934#define ENABLE_SCLK_AUD1		0x0a04
2935#define ENABLE_IP_AUD0			0x0b00
2936#define ENABLE_IP_AUD1			0x0b04
2937
2938static const unsigned long aud_clk_regs[] __initconst = {
2939	MUX_SEL_AUD0,
2940	MUX_SEL_AUD1,
2941	MUX_ENABLE_AUD0,
2942	MUX_ENABLE_AUD1,
2943	DIV_AUD0,
2944	DIV_AUD1,
2945	ENABLE_ACLK_AUD,
2946	ENABLE_PCLK_AUD,
2947	ENABLE_SCLK_AUD0,
2948	ENABLE_SCLK_AUD1,
2949	ENABLE_IP_AUD0,
2950	ENABLE_IP_AUD1,
2951};
2952
2953static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
2954	{ MUX_SEL_AUD0, 0 },
2955	{ MUX_SEL_AUD1, 0 },
2956};
2957
2958/* list of all parent clock list */
2959PNAME(mout_aud_pll_user_aud_p)	= { "oscclk", "fout_aud_pll", };
2960PNAME(mout_sclk_aud_pcm_p)	= { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2961
2962static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2963	FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2964	FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2965	FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2966};
2967
2968static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2969	/* MUX_SEL_AUD0 */
2970	MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2971			mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2972
2973	/* MUX_SEL_AUD1 */
2974	MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2975			MUX_SEL_AUD1, 8, 1),
2976	MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2977			MUX_SEL_AUD1, 0, 1),
2978};
2979
2980static const struct samsung_div_clock aud_div_clks[] __initconst = {
2981	/* DIV_AUD0 */
2982	DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2983			12, 4),
2984	DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2985			8, 4),
2986	DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2987			4, 4),
2988	DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2989			0, 4),
2990
2991	/* DIV_AUD1 */
2992	DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2993			"mout_aud_pll_user", DIV_AUD1, 16, 5),
2994	DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2995			DIV_AUD1, 12, 4),
2996	DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2997			DIV_AUD1, 4, 8),
2998	DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s",  "mout_sclk_aud_i2s",
2999			DIV_AUD1, 0, 4),
3000};
3001
3002static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
3003	/* ENABLE_ACLK_AUD */
3004	GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
3005			ENABLE_ACLK_AUD, 12, 0, 0),
3006	GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
3007			ENABLE_ACLK_AUD, 7, 0, 0),
3008	GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
3009			ENABLE_ACLK_AUD, 0, 4, 0),
3010	GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
3011			ENABLE_ACLK_AUD, 0, 3, 0),
3012	GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
3013			ENABLE_ACLK_AUD, 0, 2, 0),
3014	GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
3015			0, 1, 0),
3016	GATE(CLK_ACLK_DMAC, "aclk_dmac",  "div_aclk_aud", ENABLE_ACLK_AUD,
3017			0, CLK_IGNORE_UNUSED, 0),
3018
3019	/* ENABLE_PCLK_AUD */
3020	GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
3021			13, 0, 0),
3022	GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3023			12, 0, 0),
3024	GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3025			11, 0, 0),
3026	GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
3027			ENABLE_PCLK_AUD, 10, 0, 0),
3028	GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
3029			ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3030	GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
3031			ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3032	GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
3033			ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3034	GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
3035			ENABLE_PCLK_AUD, 6, 0, 0),
3036	GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
3037			ENABLE_PCLK_AUD, 5, 0, 0),
3038	GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
3039			ENABLE_PCLK_AUD, 4, 0, 0),
3040	GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
3041			ENABLE_PCLK_AUD, 3, 0, 0),
3042	GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3043			2, 0, 0),
3044	GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
3045			ENABLE_PCLK_AUD, 0, 0, 0),
3046
3047	/* ENABLE_SCLK_AUD0 */
3048	GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3049			2, CLK_IGNORE_UNUSED, 0),
3050	GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3051			ENABLE_SCLK_AUD0, 1, 0, 0),
3052	GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3053			0, 0, 0),
3054
3055	/* ENABLE_SCLK_AUD1 */
3056	GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3057			ENABLE_SCLK_AUD1, 6, 0, 0),
3058	GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3059			ENABLE_SCLK_AUD1, 5, 0, 0),
3060	GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3061			ENABLE_SCLK_AUD1, 4, 0, 0),
3062	GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3063			ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3064	GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3065			ENABLE_SCLK_AUD1, 2, 0, 0),
3066	GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3067			ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3068	GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3069			ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3070};
3071
3072static const struct samsung_cmu_info aud_cmu_info __initconst = {
3073	.mux_clks		= aud_mux_clks,
3074	.nr_mux_clks		= ARRAY_SIZE(aud_mux_clks),
3075	.div_clks		= aud_div_clks,
3076	.nr_div_clks		= ARRAY_SIZE(aud_div_clks),
3077	.gate_clks		= aud_gate_clks,
3078	.nr_gate_clks		= ARRAY_SIZE(aud_gate_clks),
3079	.fixed_clks		= aud_fixed_clks,
3080	.nr_fixed_clks		= ARRAY_SIZE(aud_fixed_clks),
3081	.nr_clk_ids		= CLKS_NR_AUD,
3082	.clk_regs		= aud_clk_regs,
3083	.nr_clk_regs		= ARRAY_SIZE(aud_clk_regs),
3084	.suspend_regs		= aud_suspend_regs,
3085	.nr_suspend_regs	= ARRAY_SIZE(aud_suspend_regs),
3086	.clk_name		= "fout_aud_pll",
3087};
3088
3089/*
3090 * Register offset definitions for CMU_BUS{0|1|2}
3091 */
3092#define DIV_BUS				0x0600
3093#define DIV_STAT_BUS			0x0700
3094#define ENABLE_ACLK_BUS			0x0800
3095#define ENABLE_PCLK_BUS			0x0900
3096#define ENABLE_IP_BUS0			0x0b00
3097#define ENABLE_IP_BUS1			0x0b04
3098
3099#define MUX_SEL_BUS2			0x0200	/* Only for CMU_BUS2 */
3100#define MUX_ENABLE_BUS2			0x0300	/* Only for CMU_BUS2 */
3101#define MUX_STAT_BUS2			0x0400	/* Only for CMU_BUS2 */
3102
3103/* list of all parent clock list */
3104PNAME(mout_aclk_bus2_400_p)	= { "oscclk", "aclk_bus2_400", };
3105
3106#define CMU_BUS_COMMON_CLK_REGS	\
3107	DIV_BUS,		\
3108	ENABLE_ACLK_BUS,	\
3109	ENABLE_PCLK_BUS,	\
3110	ENABLE_IP_BUS0,		\
3111	ENABLE_IP_BUS1
3112
3113static const unsigned long bus01_clk_regs[] __initconst = {
3114	CMU_BUS_COMMON_CLK_REGS,
3115};
3116
3117static const unsigned long bus2_clk_regs[] __initconst = {
3118	MUX_SEL_BUS2,
3119	MUX_ENABLE_BUS2,
3120	CMU_BUS_COMMON_CLK_REGS,
3121};
3122
3123static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3124	/* DIV_BUS0 */
3125	DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3126			DIV_BUS, 0, 3),
3127};
3128
3129/* CMU_BUS0 clocks */
3130static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3131	/* ENABLE_ACLK_BUS0 */
3132	GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3133			ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3134	GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3135			ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3136	GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3137			ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3138
3139	/* ENABLE_PCLK_BUS0 */
3140	GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3141			ENABLE_PCLK_BUS, 2, 0, 0),
3142	GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3143			ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3144	GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3145			ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3146};
3147
3148/* CMU_BUS1 clocks */
3149static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3150	/* DIV_BUS1 */
3151	DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3152			DIV_BUS, 0, 3),
3153};
3154
3155static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3156	/* ENABLE_ACLK_BUS1 */
3157	GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3158			ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3159	GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3160			ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3161	GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3162			ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3163
3164	/* ENABLE_PCLK_BUS1 */
3165	GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3166			ENABLE_PCLK_BUS, 2, 0, 0),
3167	GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3168			ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3169	GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3170			ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3171};
3172
3173/* CMU_BUS2 clocks */
3174static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3175	/* MUX_SEL_BUS2 */
3176	MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3177			mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3178};
3179
3180static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3181	/* DIV_BUS2 */
3182	DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3183			"mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3184};
3185
3186static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3187	/* ENABLE_ACLK_BUS2 */
3188	GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3189			ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3190	GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3191			ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3192	GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3193			"mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3194			1, CLK_IGNORE_UNUSED, 0),
3195	GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3196			"mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3197			0, CLK_IGNORE_UNUSED, 0),
3198
3199	/* ENABLE_PCLK_BUS2 */
3200	GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3201			ENABLE_PCLK_BUS, 2, 0, 0),
3202	GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3203			ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3204	GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3205			ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3206};
3207
3208#define CMU_BUS_INFO_CLKS(id)						\
3209	.div_clks		= bus##id##_div_clks,			\
3210	.nr_div_clks		= ARRAY_SIZE(bus##id##_div_clks),	\
3211	.gate_clks		= bus##id##_gate_clks,			\
3212	.nr_gate_clks		= ARRAY_SIZE(bus##id##_gate_clks),	\
3213	.nr_clk_ids		= CLKS_NR_BUSX
3214
3215static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3216	CMU_BUS_INFO_CLKS(0),
3217	.clk_regs		= bus01_clk_regs,
3218	.nr_clk_regs		= ARRAY_SIZE(bus01_clk_regs),
3219};
3220
3221static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3222	CMU_BUS_INFO_CLKS(1),
3223	.clk_regs		= bus01_clk_regs,
3224	.nr_clk_regs		= ARRAY_SIZE(bus01_clk_regs),
3225};
3226
3227static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3228	CMU_BUS_INFO_CLKS(2),
3229	.mux_clks		= bus2_mux_clks,
3230	.nr_mux_clks		= ARRAY_SIZE(bus2_mux_clks),
3231	.clk_regs		= bus2_clk_regs,
3232	.nr_clk_regs		= ARRAY_SIZE(bus2_clk_regs),
3233};
3234
3235#define exynos5433_cmu_bus_init(id)					\
3236static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3237{									\
3238	samsung_cmu_register_one(np, &bus##id##_cmu_info);		\
3239}									\
3240CLK_OF_DECLARE(exynos5433_cmu_bus##id,					\
3241		"samsung,exynos5433-cmu-bus"#id,			\
3242		exynos5433_cmu_bus##id##_init)
3243
3244exynos5433_cmu_bus_init(0);
3245exynos5433_cmu_bus_init(1);
3246exynos5433_cmu_bus_init(2);
3247
3248/*
3249 * Register offset definitions for CMU_G3D
3250 */
3251#define G3D_PLL_LOCK			0x0000
3252#define G3D_PLL_CON0			0x0100
3253#define G3D_PLL_CON1			0x0104
3254#define G3D_PLL_FREQ_DET		0x010c
3255#define MUX_SEL_G3D			0x0200
3256#define MUX_ENABLE_G3D			0x0300
3257#define MUX_STAT_G3D			0x0400
3258#define DIV_G3D				0x0600
3259#define DIV_G3D_PLL_FREQ_DET		0x0604
3260#define DIV_STAT_G3D			0x0700
3261#define DIV_STAT_G3D_PLL_FREQ_DET	0x0704
3262#define ENABLE_ACLK_G3D			0x0800
3263#define ENABLE_PCLK_G3D			0x0900
3264#define ENABLE_SCLK_G3D			0x0a00
3265#define ENABLE_IP_G3D0			0x0b00
3266#define ENABLE_IP_G3D1			0x0b04
3267#define CLKOUT_CMU_G3D			0x0c00
3268#define CLKOUT_CMU_G3D_DIV_STAT		0x0c04
3269#define CLK_STOPCTRL			0x1000
3270
3271static const unsigned long g3d_clk_regs[] __initconst = {
3272	G3D_PLL_LOCK,
3273	G3D_PLL_CON0,
3274	G3D_PLL_CON1,
3275	G3D_PLL_FREQ_DET,
3276	MUX_SEL_G3D,
3277	MUX_ENABLE_G3D,
3278	DIV_G3D,
3279	DIV_G3D_PLL_FREQ_DET,
3280	ENABLE_ACLK_G3D,
3281	ENABLE_PCLK_G3D,
3282	ENABLE_SCLK_G3D,
3283	ENABLE_IP_G3D0,
3284	ENABLE_IP_G3D1,
3285	CLKOUT_CMU_G3D,
3286	CLKOUT_CMU_G3D_DIV_STAT,
3287	CLK_STOPCTRL,
3288};
3289
3290static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
3291	{ MUX_SEL_G3D, 0 },
3292};
3293
3294/* list of all parent clock list */
3295PNAME(mout_aclk_g3d_400_p)	= { "mout_g3d_pll", "aclk_g3d_400", };
3296PNAME(mout_g3d_pll_p)		= { "oscclk", "fout_g3d_pll", };
3297
3298static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3299	PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3300		G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates),
3301};
3302
3303static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3304	/* MUX_SEL_G3D */
3305	MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3306			MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3307	MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3308			MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3309};
3310
3311static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3312	/* DIV_G3D */
3313	DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3314			8, 2),
3315	DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3316			4, 3),
3317	DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3318			0, 3, CLK_SET_RATE_PARENT, 0),
3319};
3320
3321static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3322	/* ENABLE_ACLK_G3D */
3323	GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3324			ENABLE_ACLK_G3D, 7, 0, 0),
3325	GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3326			ENABLE_ACLK_G3D, 6, 0, 0),
3327	GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3328			ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3329	GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3330			ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3331	GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3332			ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3333	GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3334			ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3335	GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3336			ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3337	GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3338			ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3339
3340	/* ENABLE_PCLK_G3D */
3341	GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3342			ENABLE_PCLK_G3D, 3, 0, 0),
3343	GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3344			ENABLE_PCLK_G3D, 2, 0, 0),
3345	GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3346			ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3347	GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3348			ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3349
3350	/* ENABLE_SCLK_G3D */
3351	GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3352			ENABLE_SCLK_G3D, 0, 0, 0),
3353};
3354
3355static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3356	.pll_clks		= g3d_pll_clks,
3357	.nr_pll_clks		= ARRAY_SIZE(g3d_pll_clks),
3358	.mux_clks		= g3d_mux_clks,
3359	.nr_mux_clks		= ARRAY_SIZE(g3d_mux_clks),
3360	.div_clks		= g3d_div_clks,
3361	.nr_div_clks		= ARRAY_SIZE(g3d_div_clks),
3362	.gate_clks		= g3d_gate_clks,
3363	.nr_gate_clks		= ARRAY_SIZE(g3d_gate_clks),
3364	.nr_clk_ids		= CLKS_NR_G3D,
3365	.clk_regs		= g3d_clk_regs,
3366	.nr_clk_regs		= ARRAY_SIZE(g3d_clk_regs),
3367	.suspend_regs		= g3d_suspend_regs,
3368	.nr_suspend_regs	= ARRAY_SIZE(g3d_suspend_regs),
3369	.clk_name		= "aclk_g3d_400",
3370};
3371
3372/*
3373 * Register offset definitions for CMU_GSCL
3374 */
3375#define MUX_SEL_GSCL				0x0200
3376#define MUX_ENABLE_GSCL				0x0300
3377#define MUX_STAT_GSCL				0x0400
3378#define ENABLE_ACLK_GSCL			0x0800
3379#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0	0x0804
3380#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1	0x0808
3381#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2	0x080c
3382#define ENABLE_PCLK_GSCL			0x0900
3383#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0	0x0904
3384#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1	0x0908
3385#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2	0x090c
3386#define ENABLE_IP_GSCL0				0x0b00
3387#define ENABLE_IP_GSCL1				0x0b04
3388#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0	0x0b08
3389#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1	0x0b0c
3390#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2	0x0b10
3391
3392static const unsigned long gscl_clk_regs[] __initconst = {
3393	MUX_SEL_GSCL,
3394	MUX_ENABLE_GSCL,
3395	ENABLE_ACLK_GSCL,
3396	ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3397	ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3398	ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3399	ENABLE_PCLK_GSCL,
3400	ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3401	ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3402	ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3403	ENABLE_IP_GSCL0,
3404	ENABLE_IP_GSCL1,
3405	ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3406	ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3407	ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3408};
3409
3410static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
3411	{ MUX_SEL_GSCL, 0 },
3412	{ ENABLE_ACLK_GSCL, 0xfff },
3413	{ ENABLE_PCLK_GSCL, 0xff },
3414};
3415
3416/* list of all parent clock list */
3417PNAME(aclk_gscl_111_user_p)	= { "oscclk", "aclk_gscl_111", };
3418PNAME(aclk_gscl_333_user_p)	= { "oscclk", "aclk_gscl_333", };
3419
3420static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3421	/* MUX_SEL_GSCL */
3422	MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3423			aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3424	MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3425			aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3426};
3427
3428static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3429	/* ENABLE_ACLK_GSCL */
3430	GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3431			ENABLE_ACLK_GSCL, 11, 0, 0),
3432	GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3433			ENABLE_ACLK_GSCL, 10, 0, 0),
3434	GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3435			ENABLE_ACLK_GSCL, 9, 0, 0),
3436	GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3437			"mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3438			8, CLK_IGNORE_UNUSED, 0),
3439	GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3440			ENABLE_ACLK_GSCL, 7, 0, 0),
3441	GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3442			ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3443	GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3444			"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3445			CLK_IGNORE_UNUSED, 0),
3446	GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3447			"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3448			CLK_IGNORE_UNUSED, 0),
3449	GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3450			ENABLE_ACLK_GSCL, 3, 0, 0),
3451	GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3452			ENABLE_ACLK_GSCL, 2, 0, 0),
3453	GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3454			ENABLE_ACLK_GSCL, 1, 0, 0),
3455	GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3456			ENABLE_ACLK_GSCL, 0, 0, 0),
3457
3458	/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3459	GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3460			ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3461
3462	/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3463	GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3464			ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3465
3466	/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3467	GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3468			ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3469
3470	/* ENABLE_PCLK_GSCL */
3471	GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3472			ENABLE_PCLK_GSCL, 7, 0, 0),
3473	GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3474			ENABLE_PCLK_GSCL, 6, 0, 0),
3475	GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3476			ENABLE_PCLK_GSCL, 5, 0, 0),
3477	GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3478			ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3479	GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3480			"mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3481			3, CLK_IGNORE_UNUSED, 0),
3482	GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3483			ENABLE_PCLK_GSCL, 2, 0, 0),
3484	GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3485			ENABLE_PCLK_GSCL, 1, 0, 0),
3486	GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3487			ENABLE_PCLK_GSCL, 0, 0, 0),
3488
3489	/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3490	GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3491		ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3492
3493	/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3494	GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3495		ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3496
3497	/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3498	GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3499		ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3500};
3501
3502static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3503	.mux_clks		= gscl_mux_clks,
3504	.nr_mux_clks		= ARRAY_SIZE(gscl_mux_clks),
3505	.gate_clks		= gscl_gate_clks,
3506	.nr_gate_clks		= ARRAY_SIZE(gscl_gate_clks),
3507	.nr_clk_ids		= CLKS_NR_GSCL,
3508	.clk_regs		= gscl_clk_regs,
3509	.nr_clk_regs		= ARRAY_SIZE(gscl_clk_regs),
3510	.suspend_regs		= gscl_suspend_regs,
3511	.nr_suspend_regs	= ARRAY_SIZE(gscl_suspend_regs),
3512	.clk_name		= "aclk_gscl_111",
3513};
3514
3515/*
3516 * Register offset definitions for CMU_APOLLO
3517 */
3518#define APOLLO_PLL_LOCK				0x0000
3519#define APOLLO_PLL_CON0				0x0100
3520#define APOLLO_PLL_CON1				0x0104
3521#define APOLLO_PLL_FREQ_DET			0x010c
3522#define MUX_SEL_APOLLO0				0x0200
3523#define MUX_SEL_APOLLO1				0x0204
3524#define MUX_SEL_APOLLO2				0x0208
3525#define MUX_ENABLE_APOLLO0			0x0300
3526#define MUX_ENABLE_APOLLO1			0x0304
3527#define MUX_ENABLE_APOLLO2			0x0308
3528#define MUX_STAT_APOLLO0			0x0400
3529#define MUX_STAT_APOLLO1			0x0404
3530#define MUX_STAT_APOLLO2			0x0408
3531#define DIV_APOLLO0				0x0600
3532#define DIV_APOLLO1				0x0604
3533#define DIV_APOLLO_PLL_FREQ_DET			0x0608
3534#define DIV_STAT_APOLLO0			0x0700
3535#define DIV_STAT_APOLLO1			0x0704
3536#define DIV_STAT_APOLLO_PLL_FREQ_DET		0x0708
3537#define ENABLE_ACLK_APOLLO			0x0800
3538#define ENABLE_PCLK_APOLLO			0x0900
3539#define ENABLE_SCLK_APOLLO			0x0a00
3540#define ENABLE_IP_APOLLO0			0x0b00
3541#define ENABLE_IP_APOLLO1			0x0b04
3542#define CLKOUT_CMU_APOLLO			0x0c00
3543#define CLKOUT_CMU_APOLLO_DIV_STAT		0x0c04
3544#define ARMCLK_STOPCTRL				0x1000
3545#define APOLLO_PWR_CTRL				0x1020
3546#define APOLLO_PWR_CTRL2			0x1024
3547#define APOLLO_INTR_SPREAD_ENABLE		0x1080
3548#define APOLLO_INTR_SPREAD_USE_STANDBYWFI	0x1084
3549#define APOLLO_INTR_SPREAD_BLOCKING_DURATION	0x1088
3550
3551static const unsigned long apollo_clk_regs[] __initconst = {
3552	APOLLO_PLL_LOCK,
3553	APOLLO_PLL_CON0,
3554	APOLLO_PLL_CON1,
3555	APOLLO_PLL_FREQ_DET,
3556	MUX_SEL_APOLLO0,
3557	MUX_SEL_APOLLO1,
3558	MUX_SEL_APOLLO2,
3559	MUX_ENABLE_APOLLO0,
3560	MUX_ENABLE_APOLLO1,
3561	MUX_ENABLE_APOLLO2,
3562	DIV_APOLLO0,
3563	DIV_APOLLO1,
3564	DIV_APOLLO_PLL_FREQ_DET,
3565	ENABLE_ACLK_APOLLO,
3566	ENABLE_PCLK_APOLLO,
3567	ENABLE_SCLK_APOLLO,
3568	ENABLE_IP_APOLLO0,
3569	ENABLE_IP_APOLLO1,
3570	CLKOUT_CMU_APOLLO,
3571	CLKOUT_CMU_APOLLO_DIV_STAT,
3572	ARMCLK_STOPCTRL,
3573	APOLLO_PWR_CTRL,
3574	APOLLO_PWR_CTRL2,
3575	APOLLO_INTR_SPREAD_ENABLE,
3576	APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3577	APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3578};
3579
3580/* list of all parent clock list */
3581PNAME(mout_apollo_pll_p)		= { "oscclk", "fout_apollo_pll", };
3582PNAME(mout_bus_pll_apollo_user_p)	= { "oscclk", "sclk_bus_pll_apollo", };
3583PNAME(mout_apollo_p)			= { "mout_apollo_pll",
3584					    "mout_bus_pll_apollo_user", };
3585
3586static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3587	PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3588		APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates),
3589};
3590
3591static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3592	/* MUX_SEL_APOLLO0 */
3593	MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3594			MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3595			CLK_RECALC_NEW_RATES, 0),
3596
3597	/* MUX_SEL_APOLLO1 */
3598	MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3599			mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3600
3601	/* MUX_SEL_APOLLO2 */
3602	MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3603			0, 1, CLK_SET_RATE_PARENT, 0),
3604};
3605
3606static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3607	/* DIV_APOLLO0 */
3608	DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3609			DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3610			CLK_DIVIDER_READ_ONLY),
3611	DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3612			DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3613			CLK_DIVIDER_READ_ONLY),
3614	DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3615			DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3616			CLK_DIVIDER_READ_ONLY),
3617	DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3618			DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3619			CLK_DIVIDER_READ_ONLY),
3620	DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3621			DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3622			CLK_DIVIDER_READ_ONLY),
3623	DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3624			DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3625	DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3626			DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3627
3628	/* DIV_APOLLO1 */
3629	DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3630			DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3631			CLK_DIVIDER_READ_ONLY),
3632	DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3633			DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3634			CLK_DIVIDER_READ_ONLY),
3635};
3636
3637static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3638	/* ENABLE_ACLK_APOLLO */
3639	GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3640			"div_atclk_apollo", ENABLE_ACLK_APOLLO,
3641			6, CLK_IGNORE_UNUSED, 0),
3642	GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3643			"div_atclk_apollo", ENABLE_ACLK_APOLLO,
3644			5, CLK_IGNORE_UNUSED, 0),
3645	GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3646			"div_atclk_apollo", ENABLE_ACLK_APOLLO,
3647			4, CLK_IGNORE_UNUSED, 0),
3648	GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3649			"div_atclk_apollo", ENABLE_ACLK_APOLLO,
3650			3, CLK_IGNORE_UNUSED, 0),
3651	GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3652			"div_aclk_apollo", ENABLE_ACLK_APOLLO,
3653			2, CLK_IGNORE_UNUSED, 0),
3654	GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3655			"div_pclk_apollo", ENABLE_ACLK_APOLLO,
3656			1, CLK_IGNORE_UNUSED, 0),
3657	GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3658			"div_pclk_apollo", ENABLE_ACLK_APOLLO,
3659			0, CLK_IGNORE_UNUSED, 0),
3660
3661	/* ENABLE_PCLK_APOLLO */
3662	GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3663			"div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3664			2, CLK_IGNORE_UNUSED, 0),
3665	GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3666			ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3667	GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3668			"div_pclk_apollo", ENABLE_PCLK_APOLLO,
3669			0, CLK_IGNORE_UNUSED, 0),
3670
3671	/* ENABLE_SCLK_APOLLO */
3672	GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3673			ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3674	GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3675			ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3676};
3677
3678#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3679		(((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3680		 ((pclk) << 12) | ((aclk) << 8))
3681
3682#define E5433_APOLLO_DIV1(hpm, copy) \
3683		(((hpm) << 4) | ((copy) << 0))
3684
3685static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3686	{ 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3687	{ 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3688	{ 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3689	{ 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3690	{  900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3691	{  800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3692	{  700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3693	{  600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3694	{  500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3695	{  400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3696	{  0 },
3697};
3698
3699static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
3700	CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
3701		CLK_MOUT_BUS_PLL_APOLLO_USER, 0, 0x0,
3702		CPUCLK_LAYOUT_E5433, exynos5433_apolloclk_d),
3703};
3704
3705static const struct samsung_cmu_info apollo_cmu_info __initconst = {
3706	.pll_clks	= apollo_pll_clks,
3707	.nr_pll_clks	= ARRAY_SIZE(apollo_pll_clks),
3708	.mux_clks	= apollo_mux_clks,
3709	.nr_mux_clks	= ARRAY_SIZE(apollo_mux_clks),
3710	.div_clks	= apollo_div_clks,
3711	.nr_div_clks	= ARRAY_SIZE(apollo_div_clks),
3712	.gate_clks	= apollo_gate_clks,
3713	.nr_gate_clks	= ARRAY_SIZE(apollo_gate_clks),
3714	.cpu_clks	= apollo_cpu_clks,
3715	.nr_cpu_clks	= ARRAY_SIZE(apollo_cpu_clks),
3716	.nr_clk_ids	= CLKS_NR_APOLLO,
3717	.clk_regs	= apollo_clk_regs,
3718	.nr_clk_regs	= ARRAY_SIZE(apollo_clk_regs),
3719};
3720
3721static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3722{
3723	samsung_cmu_register_one(np, &apollo_cmu_info);
3724}
3725CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3726		exynos5433_cmu_apollo_init);
3727
3728/*
3729 * Register offset definitions for CMU_ATLAS
3730 */
3731#define ATLAS_PLL_LOCK				0x0000
3732#define ATLAS_PLL_CON0				0x0100
3733#define ATLAS_PLL_CON1				0x0104
3734#define ATLAS_PLL_FREQ_DET			0x010c
3735#define MUX_SEL_ATLAS0				0x0200
3736#define MUX_SEL_ATLAS1				0x0204
3737#define MUX_SEL_ATLAS2				0x0208
3738#define MUX_ENABLE_ATLAS0			0x0300
3739#define MUX_ENABLE_ATLAS1			0x0304
3740#define MUX_ENABLE_ATLAS2			0x0308
3741#define MUX_STAT_ATLAS0				0x0400
3742#define MUX_STAT_ATLAS1				0x0404
3743#define MUX_STAT_ATLAS2				0x0408
3744#define DIV_ATLAS0				0x0600
3745#define DIV_ATLAS1				0x0604
3746#define DIV_ATLAS_PLL_FREQ_DET			0x0608
3747#define DIV_STAT_ATLAS0				0x0700
3748#define DIV_STAT_ATLAS1				0x0704
3749#define DIV_STAT_ATLAS_PLL_FREQ_DET		0x0708
3750#define ENABLE_ACLK_ATLAS			0x0800
3751#define ENABLE_PCLK_ATLAS			0x0900
3752#define ENABLE_SCLK_ATLAS			0x0a00
3753#define ENABLE_IP_ATLAS0			0x0b00
3754#define ENABLE_IP_ATLAS1			0x0b04
3755#define CLKOUT_CMU_ATLAS			0x0c00
3756#define CLKOUT_CMU_ATLAS_DIV_STAT		0x0c04
3757#define ARMCLK_STOPCTRL				0x1000
3758#define ATLAS_PWR_CTRL				0x1020
3759#define ATLAS_PWR_CTRL2				0x1024
3760#define ATLAS_INTR_SPREAD_ENABLE		0x1080
3761#define ATLAS_INTR_SPREAD_USE_STANDBYWFI	0x1084
3762#define ATLAS_INTR_SPREAD_BLOCKING_DURATION	0x1088
3763
3764static const unsigned long atlas_clk_regs[] __initconst = {
3765	ATLAS_PLL_LOCK,
3766	ATLAS_PLL_CON0,
3767	ATLAS_PLL_CON1,
3768	ATLAS_PLL_FREQ_DET,
3769	MUX_SEL_ATLAS0,
3770	MUX_SEL_ATLAS1,
3771	MUX_SEL_ATLAS2,
3772	MUX_ENABLE_ATLAS0,
3773	MUX_ENABLE_ATLAS1,
3774	MUX_ENABLE_ATLAS2,
3775	DIV_ATLAS0,
3776	DIV_ATLAS1,
3777	DIV_ATLAS_PLL_FREQ_DET,
3778	ENABLE_ACLK_ATLAS,
3779	ENABLE_PCLK_ATLAS,
3780	ENABLE_SCLK_ATLAS,
3781	ENABLE_IP_ATLAS0,
3782	ENABLE_IP_ATLAS1,
3783	CLKOUT_CMU_ATLAS,
3784	CLKOUT_CMU_ATLAS_DIV_STAT,
3785	ARMCLK_STOPCTRL,
3786	ATLAS_PWR_CTRL,
3787	ATLAS_PWR_CTRL2,
3788	ATLAS_INTR_SPREAD_ENABLE,
3789	ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3790	ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3791};
3792
3793/* list of all parent clock list */
3794PNAME(mout_atlas_pll_p)			= { "oscclk", "fout_atlas_pll", };
3795PNAME(mout_bus_pll_atlas_user_p)	= { "oscclk", "sclk_bus_pll_atlas", };
3796PNAME(mout_atlas_p)			= { "mout_atlas_pll",
3797					    "mout_bus_pll_atlas_user", };
3798
3799static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3800	PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3801		ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates),
3802};
3803
3804static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3805	/* MUX_SEL_ATLAS0 */
3806	MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3807			MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3808			CLK_RECALC_NEW_RATES, 0),
3809
3810	/* MUX_SEL_ATLAS1 */
3811	MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3812			mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3813
3814	/* MUX_SEL_ATLAS2 */
3815	MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3816			0, 1, CLK_SET_RATE_PARENT, 0),
3817};
3818
3819static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3820	/* DIV_ATLAS0 */
3821	DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3822			DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3823			CLK_DIVIDER_READ_ONLY),
3824	DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3825			DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3826			CLK_DIVIDER_READ_ONLY),
3827	DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3828			DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3829			CLK_DIVIDER_READ_ONLY),
3830	DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3831			DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3832			CLK_DIVIDER_READ_ONLY),
3833	DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3834			DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3835			CLK_DIVIDER_READ_ONLY),
3836	DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3837			DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3838	DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3839			DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3840
3841	/* DIV_ATLAS1 */
3842	DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3843			DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3844			CLK_DIVIDER_READ_ONLY),
3845	DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3846			DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3847			CLK_DIVIDER_READ_ONLY),
3848};
3849
3850static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3851	/* ENABLE_ACLK_ATLAS */
3852	GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3853			"div_atclk_atlas", ENABLE_ACLK_ATLAS,
3854			9, CLK_IGNORE_UNUSED, 0),
3855	GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3856			"div_atclk_atlas", ENABLE_ACLK_ATLAS,
3857			8, CLK_IGNORE_UNUSED, 0),
3858	GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3859			"div_atclk_atlas", ENABLE_ACLK_ATLAS,
3860			7, CLK_IGNORE_UNUSED, 0),
3861	GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3862			"div_atclk_atlas", ENABLE_ACLK_ATLAS,
3863			6, CLK_IGNORE_UNUSED, 0),
3864	GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3865			"div_atclk_atlas", ENABLE_ACLK_ATLAS,
3866			5, CLK_IGNORE_UNUSED, 0),
3867	GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3868			"div_atclk_atlas", ENABLE_ACLK_ATLAS,
3869			4, CLK_IGNORE_UNUSED, 0),
3870	GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3871			"div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3872			3, CLK_IGNORE_UNUSED, 0),
3873	GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3874			"div_aclk_atlas", ENABLE_ACLK_ATLAS,
3875			2, CLK_IGNORE_UNUSED, 0),
3876	GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3877			ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3878	GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3879			ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3880
3881	/* ENABLE_PCLK_ATLAS */
3882	GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3883			"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3884			5, CLK_IGNORE_UNUSED, 0),
3885	GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3886			"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3887			4, CLK_IGNORE_UNUSED, 0),
3888	GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3889			"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3890			3, CLK_IGNORE_UNUSED, 0),
3891	GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3892			ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3893	GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3894			ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3895	GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3896			ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3897
3898	/* ENABLE_SCLK_ATLAS */
3899	GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3900			ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3901	GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3902			ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3903	GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3904			ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3905	GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3906			ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3907	GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3908			ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3909	GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3910			ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3911	GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3912			ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3913	GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3914			ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3915};
3916
3917#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3918		(((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3919		 ((pclk) << 12) | ((aclk) << 8))
3920
3921#define E5433_ATLAS_DIV1(hpm, copy) \
3922		(((hpm) << 4) | ((copy) << 0))
3923
3924static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3925	{ 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3926	{ 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3927	{ 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3928	{ 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3929	{ 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3930	{ 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3931	{ 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3932	{ 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3933	{ 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3934	{ 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3935	{  900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3936	{  800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3937	{  700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3938	{  600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3939	{  500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3940	{  0 },
3941};
3942
3943static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
3944	CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
3945		CLK_MOUT_BUS_PLL_ATLAS_USER, 0, 0x0,
3946		CPUCLK_LAYOUT_E5433, exynos5433_atlasclk_d),
3947};
3948
3949static const struct samsung_cmu_info atlas_cmu_info __initconst = {
3950	.pll_clks	= atlas_pll_clks,
3951	.nr_pll_clks	= ARRAY_SIZE(atlas_pll_clks),
3952	.mux_clks	= atlas_mux_clks,
3953	.nr_mux_clks	= ARRAY_SIZE(atlas_mux_clks),
3954	.div_clks	= atlas_div_clks,
3955	.nr_div_clks	= ARRAY_SIZE(atlas_div_clks),
3956	.gate_clks	= atlas_gate_clks,
3957	.nr_gate_clks	= ARRAY_SIZE(atlas_gate_clks),
3958	.cpu_clks	= atlas_cpu_clks,
3959	.nr_cpu_clks	= ARRAY_SIZE(atlas_cpu_clks),
3960	.nr_clk_ids	= CLKS_NR_ATLAS,
3961	.clk_regs	= atlas_clk_regs,
3962	.nr_clk_regs	= ARRAY_SIZE(atlas_clk_regs),
3963};
3964
3965static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3966{
3967	samsung_cmu_register_one(np, &atlas_cmu_info);
3968}
3969CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3970		exynos5433_cmu_atlas_init);
3971
3972/*
3973 * Register offset definitions for CMU_MSCL
3974 */
3975#define MUX_SEL_MSCL0					0x0200
3976#define MUX_SEL_MSCL1					0x0204
3977#define MUX_ENABLE_MSCL0				0x0300
3978#define MUX_ENABLE_MSCL1				0x0304
3979#define MUX_STAT_MSCL0					0x0400
3980#define MUX_STAT_MSCL1					0x0404
3981#define DIV_MSCL					0x0600
3982#define DIV_STAT_MSCL					0x0700
3983#define ENABLE_ACLK_MSCL				0x0800
3984#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0		0x0804
3985#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1		0x0808
3986#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG		0x080c
3987#define ENABLE_PCLK_MSCL				0x0900
3988#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0		0x0904
3989#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1		0x0908
3990#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG		0x090c
3991#define ENABLE_SCLK_MSCL				0x0a00
3992#define ENABLE_IP_MSCL0					0x0b00
3993#define ENABLE_IP_MSCL1					0x0b04
3994#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0		0x0b08
3995#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1		0x0b0c
3996#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG			0x0b10
3997
3998static const unsigned long mscl_clk_regs[] __initconst = {
3999	MUX_SEL_MSCL0,
4000	MUX_SEL_MSCL1,
4001	MUX_ENABLE_MSCL0,
4002	MUX_ENABLE_MSCL1,
4003	DIV_MSCL,
4004	ENABLE_ACLK_MSCL,
4005	ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4006	ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4007	ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4008	ENABLE_PCLK_MSCL,
4009	ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4010	ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4011	ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4012	ENABLE_SCLK_MSCL,
4013	ENABLE_IP_MSCL0,
4014	ENABLE_IP_MSCL1,
4015	ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
4016	ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
4017	ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
4018};
4019
4020static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
4021	{ MUX_SEL_MSCL0, 0 },
4022	{ MUX_SEL_MSCL1, 0 },
4023};
4024
4025/* list of all parent clock list */
4026PNAME(mout_sclk_jpeg_user_p)		= { "oscclk", "sclk_jpeg_mscl", };
4027PNAME(mout_aclk_mscl_400_user_p)	= { "oscclk", "aclk_mscl_400", };
4028PNAME(mout_sclk_jpeg_p)			= { "mout_sclk_jpeg_user",
4029					"mout_aclk_mscl_400_user", };
4030
4031static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
4032	/* MUX_SEL_MSCL0 */
4033	MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
4034			mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
4035	MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
4036			mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4037
4038	/* MUX_SEL_MSCL1 */
4039	MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
4040			MUX_SEL_MSCL1, 0, 1),
4041};
4042
4043static const struct samsung_div_clock mscl_div_clks[] __initconst = {
4044	/* DIV_MSCL */
4045	DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
4046			DIV_MSCL, 0, 3),
4047};
4048
4049static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
4050	/* ENABLE_ACLK_MSCL */
4051	GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
4052			ENABLE_ACLK_MSCL, 9, 0, 0),
4053	GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
4054			"mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4055	GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
4056			"mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4057	GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
4058			ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4059	GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
4060			ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4061	GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4062			ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4063	GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4064			ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4065	GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4066			ENABLE_ACLK_MSCL, 2, 0, 0),
4067	GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4068			ENABLE_ACLK_MSCL, 1, 0, 0),
4069	GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4070			ENABLE_ACLK_MSCL, 0, 0, 0),
4071
4072	/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4073	GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4074			"mout_aclk_mscl_400_user",
4075			ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4076			0, CLK_IGNORE_UNUSED, 0),
4077
4078	/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4079	GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4080			"mout_aclk_mscl_400_user",
4081			ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4082			0, CLK_IGNORE_UNUSED, 0),
4083
4084	/* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4085	GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4086			ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4087			0, CLK_IGNORE_UNUSED, 0),
4088
4089	/* ENABLE_PCLK_MSCL */
4090	GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4091			ENABLE_PCLK_MSCL, 7, 0, 0),
4092	GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4093			ENABLE_PCLK_MSCL, 6, 0, 0),
4094	GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4095			ENABLE_PCLK_MSCL, 5, 0, 0),
4096	GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4097			ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4098	GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4099			ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4100	GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4101			ENABLE_PCLK_MSCL, 2, 0, 0),
4102	GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4103			ENABLE_PCLK_MSCL, 1, 0, 0),
4104	GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4105			ENABLE_PCLK_MSCL, 0, 0, 0),
4106
4107	/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4108	GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4109			ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4110			0, CLK_IGNORE_UNUSED, 0),
4111
4112	/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4113	GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4114			ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4115			0, CLK_IGNORE_UNUSED, 0),
4116
4117	/* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4118	GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4119			ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4120			0, CLK_IGNORE_UNUSED, 0),
4121
4122	/* ENABLE_SCLK_MSCL */
4123	GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4124			CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4125};
4126
4127static const struct samsung_cmu_info mscl_cmu_info __initconst = {
4128	.mux_clks		= mscl_mux_clks,
4129	.nr_mux_clks		= ARRAY_SIZE(mscl_mux_clks),
4130	.div_clks		= mscl_div_clks,
4131	.nr_div_clks		= ARRAY_SIZE(mscl_div_clks),
4132	.gate_clks		= mscl_gate_clks,
4133	.nr_gate_clks		= ARRAY_SIZE(mscl_gate_clks),
4134	.nr_clk_ids		= CLKS_NR_MSCL,
4135	.clk_regs		= mscl_clk_regs,
4136	.nr_clk_regs		= ARRAY_SIZE(mscl_clk_regs),
4137	.suspend_regs		= mscl_suspend_regs,
4138	.nr_suspend_regs	= ARRAY_SIZE(mscl_suspend_regs),
4139	.clk_name		= "aclk_mscl_400",
4140};
4141
4142/*
4143 * Register offset definitions for CMU_MFC
4144 */
4145#define MUX_SEL_MFC				0x0200
4146#define MUX_ENABLE_MFC				0x0300
4147#define MUX_STAT_MFC				0x0400
4148#define DIV_MFC					0x0600
4149#define DIV_STAT_MFC				0x0700
4150#define ENABLE_ACLK_MFC				0x0800
4151#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC		0x0804
4152#define ENABLE_PCLK_MFC				0x0900
4153#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC		0x0904
4154#define ENABLE_IP_MFC0				0x0b00
4155#define ENABLE_IP_MFC1				0x0b04
4156#define ENABLE_IP_MFC_SECURE_SMMU_MFC		0x0b08
4157
4158static const unsigned long mfc_clk_regs[] __initconst = {
4159	MUX_SEL_MFC,
4160	MUX_ENABLE_MFC,
4161	DIV_MFC,
4162	ENABLE_ACLK_MFC,
4163	ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4164	ENABLE_PCLK_MFC,
4165	ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4166	ENABLE_IP_MFC0,
4167	ENABLE_IP_MFC1,
4168	ENABLE_IP_MFC_SECURE_SMMU_MFC,
4169};
4170
4171static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
4172	{ MUX_SEL_MFC, 0 },
4173};
4174
4175PNAME(mout_aclk_mfc_400_user_p)		= { "oscclk", "aclk_mfc_400", };
4176
4177static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4178	/* MUX_SEL_MFC */
4179	MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4180			mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4181};
4182
4183static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4184	/* DIV_MFC */
4185	DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4186			DIV_MFC, 0, 2),
4187};
4188
4189static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4190	/* ENABLE_ACLK_MFC */
4191	GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4192			ENABLE_ACLK_MFC, 6, 0, 0),
4193	GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4194			ENABLE_ACLK_MFC, 5, 0, 0),
4195	GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4196			ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4197	GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4198			ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4199	GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4200			ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4201	GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4202			ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4203	GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4204			ENABLE_ACLK_MFC, 0, 0, 0),
4205
4206	/* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4207	GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4208			ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4209			1, CLK_IGNORE_UNUSED, 0),
4210	GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4211			ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4212			0, CLK_IGNORE_UNUSED, 0),
4213
4214	/* ENABLE_PCLK_MFC */
4215	GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4216			ENABLE_PCLK_MFC, 4, 0, 0),
4217	GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4218			ENABLE_PCLK_MFC, 3, 0, 0),
4219	GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4220			ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4221	GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4222			ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4223	GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4224			ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4225
4226	/* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4227	GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4228			ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4229			1, CLK_IGNORE_UNUSED, 0),
4230	GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4231			ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4232			0, CLK_IGNORE_UNUSED, 0),
4233};
4234
4235static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4236	.mux_clks		= mfc_mux_clks,
4237	.nr_mux_clks		= ARRAY_SIZE(mfc_mux_clks),
4238	.div_clks		= mfc_div_clks,
4239	.nr_div_clks		= ARRAY_SIZE(mfc_div_clks),
4240	.gate_clks		= mfc_gate_clks,
4241	.nr_gate_clks		= ARRAY_SIZE(mfc_gate_clks),
4242	.nr_clk_ids		= CLKS_NR_MFC,
4243	.clk_regs		= mfc_clk_regs,
4244	.nr_clk_regs		= ARRAY_SIZE(mfc_clk_regs),
4245	.suspend_regs		= mfc_suspend_regs,
4246	.nr_suspend_regs	= ARRAY_SIZE(mfc_suspend_regs),
4247	.clk_name		= "aclk_mfc_400",
4248};
4249
4250/*
4251 * Register offset definitions for CMU_HEVC
4252 */
4253#define MUX_SEL_HEVC				0x0200
4254#define MUX_ENABLE_HEVC				0x0300
4255#define MUX_STAT_HEVC				0x0400
4256#define DIV_HEVC				0x0600
4257#define DIV_STAT_HEVC				0x0700
4258#define ENABLE_ACLK_HEVC			0x0800
4259#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC	0x0804
4260#define ENABLE_PCLK_HEVC			0x0900
4261#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC	0x0904
4262#define ENABLE_IP_HEVC0				0x0b00
4263#define ENABLE_IP_HEVC1				0x0b04
4264#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC		0x0b08
4265
4266static const unsigned long hevc_clk_regs[] __initconst = {
4267	MUX_SEL_HEVC,
4268	MUX_ENABLE_HEVC,
4269	DIV_HEVC,
4270	ENABLE_ACLK_HEVC,
4271	ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4272	ENABLE_PCLK_HEVC,
4273	ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4274	ENABLE_IP_HEVC0,
4275	ENABLE_IP_HEVC1,
4276	ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4277};
4278
4279static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
4280	{ MUX_SEL_HEVC, 0 },
4281};
4282
4283PNAME(mout_aclk_hevc_400_user_p)	= { "oscclk", "aclk_hevc_400", };
4284
4285static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4286	/* MUX_SEL_HEVC */
4287	MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4288			mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4289};
4290
4291static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4292	/* DIV_HEVC */
4293	DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4294			DIV_HEVC, 0, 2),
4295};
4296
4297static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4298	/* ENABLE_ACLK_HEVC */
4299	GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4300			ENABLE_ACLK_HEVC, 6, 0, 0),
4301	GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4302			ENABLE_ACLK_HEVC, 5, 0, 0),
4303	GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4304			ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4305	GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4306			ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4307	GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4308			ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4309	GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4310			ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4311	GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4312			ENABLE_ACLK_HEVC, 0, 0, 0),
4313
4314	/* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4315	GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4316			"mout_aclk_hevc_400_user",
4317			ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4318			1, CLK_IGNORE_UNUSED, 0),
4319	GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4320			"mout_aclk_hevc_400_user",
4321			ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4322			0, CLK_IGNORE_UNUSED, 0),
4323
4324	/* ENABLE_PCLK_HEVC */
4325	GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4326			ENABLE_PCLK_HEVC, 4, 0, 0),
4327	GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4328			ENABLE_PCLK_HEVC, 3, 0, 0),
4329	GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4330			ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4331	GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4332			ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4333	GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4334			ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4335
4336	/* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4337	GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4338			ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4339			1, CLK_IGNORE_UNUSED, 0),
4340	GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4341			ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4342			0, CLK_IGNORE_UNUSED, 0),
4343};
4344
4345static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4346	.mux_clks		= hevc_mux_clks,
4347	.nr_mux_clks		= ARRAY_SIZE(hevc_mux_clks),
4348	.div_clks		= hevc_div_clks,
4349	.nr_div_clks		= ARRAY_SIZE(hevc_div_clks),
4350	.gate_clks		= hevc_gate_clks,
4351	.nr_gate_clks		= ARRAY_SIZE(hevc_gate_clks),
4352	.nr_clk_ids		= CLKS_NR_HEVC,
4353	.clk_regs		= hevc_clk_regs,
4354	.nr_clk_regs		= ARRAY_SIZE(hevc_clk_regs),
4355	.suspend_regs		= hevc_suspend_regs,
4356	.nr_suspend_regs	= ARRAY_SIZE(hevc_suspend_regs),
4357	.clk_name		= "aclk_hevc_400",
4358};
4359
4360/*
4361 * Register offset definitions for CMU_ISP
4362 */
4363#define MUX_SEL_ISP			0x0200
4364#define MUX_ENABLE_ISP			0x0300
4365#define MUX_STAT_ISP			0x0400
4366#define DIV_ISP				0x0600
4367#define DIV_STAT_ISP			0x0700
4368#define ENABLE_ACLK_ISP0		0x0800
4369#define ENABLE_ACLK_ISP1		0x0804
4370#define ENABLE_ACLK_ISP2		0x0808
4371#define ENABLE_PCLK_ISP			0x0900
4372#define ENABLE_SCLK_ISP			0x0a00
4373#define ENABLE_IP_ISP0			0x0b00
4374#define ENABLE_IP_ISP1			0x0b04
4375#define ENABLE_IP_ISP2			0x0b08
4376#define ENABLE_IP_ISP3			0x0b0c
4377
4378static const unsigned long isp_clk_regs[] __initconst = {
4379	MUX_SEL_ISP,
4380	MUX_ENABLE_ISP,
4381	DIV_ISP,
4382	ENABLE_ACLK_ISP0,
4383	ENABLE_ACLK_ISP1,
4384	ENABLE_ACLK_ISP2,
4385	ENABLE_PCLK_ISP,
4386	ENABLE_SCLK_ISP,
4387	ENABLE_IP_ISP0,
4388	ENABLE_IP_ISP1,
4389	ENABLE_IP_ISP2,
4390	ENABLE_IP_ISP3,
4391};
4392
4393static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
4394	{ MUX_SEL_ISP, 0 },
4395};
4396
4397PNAME(mout_aclk_isp_dis_400_user_p)	= { "oscclk", "aclk_isp_dis_400", };
4398PNAME(mout_aclk_isp_400_user_p)		= { "oscclk", "aclk_isp_400", };
4399
4400static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4401	/* MUX_SEL_ISP */
4402	MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4403			mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4404	MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4405			mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4406};
4407
4408static const struct samsung_div_clock isp_div_clks[] __initconst = {
4409	/* DIV_ISP */
4410	DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4411			"mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4412	DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4413			DIV_ISP, 8, 3),
4414	DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4415			"mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4416	DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4417			"mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4418};
4419
4420static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4421	/* ENABLE_ACLK_ISP0 */
4422	GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4423			ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4424	GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4425			ENABLE_ACLK_ISP0, 5, 0, 0),
4426	GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4427			ENABLE_ACLK_ISP0, 4, 0, 0),
4428	GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4429			ENABLE_ACLK_ISP0, 3, 0, 0),
4430	GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4431			ENABLE_ACLK_ISP0, 2, 0, 0),
4432	GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4433			ENABLE_ACLK_ISP0, 1, 0, 0),
4434	GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4435			ENABLE_ACLK_ISP0, 0, 0, 0),
4436
4437	/* ENABLE_ACLK_ISP1 */
4438	GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4439			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4440			17, CLK_IGNORE_UNUSED, 0),
4441	GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4442			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4443			16, CLK_IGNORE_UNUSED, 0),
4444	GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4445			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4446			15, CLK_IGNORE_UNUSED, 0),
4447	GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4448			"div_pclk_isp", ENABLE_ACLK_ISP1,
4449			14, CLK_IGNORE_UNUSED, 0),
4450	GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4451			"div_pclk_isp", ENABLE_ACLK_ISP1,
4452			13, CLK_IGNORE_UNUSED, 0),
4453	GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4454			"mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4455			12, CLK_IGNORE_UNUSED, 0),
4456	GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4457			"mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4458			11, CLK_IGNORE_UNUSED, 0),
4459	GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4460			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4461			10, CLK_IGNORE_UNUSED, 0),
4462	GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4463			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4464			9, CLK_IGNORE_UNUSED, 0),
4465	GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4466			"div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4467			8, CLK_IGNORE_UNUSED, 0),
4468	GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4469			"div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4470			7, CLK_IGNORE_UNUSED, 0),
4471	GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4472			ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4473	GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4474			ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4475	GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4476			"div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4477			4, CLK_IGNORE_UNUSED, 0),
4478	GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4479			"div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4480			3, CLK_IGNORE_UNUSED, 0),
4481	GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4482			ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4483	GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4484			ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4485	GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4486			ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4487
4488	/* ENABLE_ACLK_ISP2 */
4489	GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4490			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4491			13, CLK_IGNORE_UNUSED, 0),
4492	GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4493			ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4494	GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4495			ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4496	GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4497			ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4498	GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4499			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4500			9, CLK_IGNORE_UNUSED, 0),
4501	GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4502			ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4503	GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4504			ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4505	GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4506			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4507			6, CLK_IGNORE_UNUSED, 0),
4508	GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4509			ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4510	GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4511			ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4512	GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4513			ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4514	GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4515			"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4516			2, CLK_IGNORE_UNUSED, 0),
4517	GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4518			ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4519	GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4520			ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4521
4522	/* ENABLE_PCLK_ISP */
4523	GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4524			ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4525	GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4526			ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4527	GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4528			ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4529	GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4530			ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4531	GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4532			ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4533	GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4534			ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4535	GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4536			ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4537	GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4538			ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4539	GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4540			ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4541	GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4542			ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4543	GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4544			ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4545	GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4546			ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4547	GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4548			ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4549	GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4550			ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4551	GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4552			ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4553	GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4554			ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4555	GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4556			ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4557	GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4558			ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4559	GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4560			"div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4561			7, CLK_IGNORE_UNUSED, 0),
4562	GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4563			ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4564	GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4565			ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4566	GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4567			ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4568	GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4569			ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4570	GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4571			ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4572	GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4573			ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4574	GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4575			ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4576
4577	/* ENABLE_SCLK_ISP */
4578	GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4579			"mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4580			5, CLK_IGNORE_UNUSED, 0),
4581	GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4582			"mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4583			4, CLK_IGNORE_UNUSED, 0),
4584	GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4585			"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4586			3, CLK_IGNORE_UNUSED, 0),
4587	GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4588			"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4589			2, CLK_IGNORE_UNUSED, 0),
4590	GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4591			"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4592			1, CLK_IGNORE_UNUSED, 0),
4593	GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4594			"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4595			0, CLK_IGNORE_UNUSED, 0),
4596};
4597
4598static const struct samsung_cmu_info isp_cmu_info __initconst = {
4599	.mux_clks		= isp_mux_clks,
4600	.nr_mux_clks		= ARRAY_SIZE(isp_mux_clks),
4601	.div_clks		= isp_div_clks,
4602	.nr_div_clks		= ARRAY_SIZE(isp_div_clks),
4603	.gate_clks		= isp_gate_clks,
4604	.nr_gate_clks		= ARRAY_SIZE(isp_gate_clks),
4605	.nr_clk_ids		= CLKS_NR_ISP,
4606	.clk_regs		= isp_clk_regs,
4607	.nr_clk_regs		= ARRAY_SIZE(isp_clk_regs),
4608	.suspend_regs		= isp_suspend_regs,
4609	.nr_suspend_regs	= ARRAY_SIZE(isp_suspend_regs),
4610	.clk_name		= "aclk_isp_400",
4611};
4612
4613/*
4614 * Register offset definitions for CMU_CAM0
4615 */
4616#define MUX_SEL_CAM00			0x0200
4617#define MUX_SEL_CAM01			0x0204
4618#define MUX_SEL_CAM02			0x0208
4619#define MUX_SEL_CAM03			0x020c
4620#define MUX_SEL_CAM04			0x0210
4621#define MUX_ENABLE_CAM00		0x0300
4622#define MUX_ENABLE_CAM01		0x0304
4623#define MUX_ENABLE_CAM02		0x0308
4624#define MUX_ENABLE_CAM03		0x030c
4625#define MUX_ENABLE_CAM04		0x0310
4626#define MUX_STAT_CAM00			0x0400
4627#define MUX_STAT_CAM01			0x0404
4628#define MUX_STAT_CAM02			0x0408
4629#define MUX_STAT_CAM03			0x040c
4630#define MUX_STAT_CAM04			0x0410
4631#define MUX_IGNORE_CAM01		0x0504
4632#define DIV_CAM00			0x0600
4633#define DIV_CAM01			0x0604
4634#define DIV_CAM02			0x0608
4635#define DIV_CAM03			0x060c
4636#define DIV_STAT_CAM00			0x0700
4637#define DIV_STAT_CAM01			0x0704
4638#define DIV_STAT_CAM02			0x0708
4639#define DIV_STAT_CAM03			0x070c
4640#define ENABLE_ACLK_CAM00		0X0800
4641#define ENABLE_ACLK_CAM01		0X0804
4642#define ENABLE_ACLK_CAM02		0X0808
4643#define ENABLE_PCLK_CAM0		0X0900
4644#define ENABLE_SCLK_CAM0		0X0a00
4645#define ENABLE_IP_CAM00			0X0b00
4646#define ENABLE_IP_CAM01			0X0b04
4647#define ENABLE_IP_CAM02			0X0b08
4648#define ENABLE_IP_CAM03			0X0b0C
4649
4650static const unsigned long cam0_clk_regs[] __initconst = {
4651	MUX_SEL_CAM00,
4652	MUX_SEL_CAM01,
4653	MUX_SEL_CAM02,
4654	MUX_SEL_CAM03,
4655	MUX_SEL_CAM04,
4656	MUX_ENABLE_CAM00,
4657	MUX_ENABLE_CAM01,
4658	MUX_ENABLE_CAM02,
4659	MUX_ENABLE_CAM03,
4660	MUX_ENABLE_CAM04,
4661	MUX_IGNORE_CAM01,
4662	DIV_CAM00,
4663	DIV_CAM01,
4664	DIV_CAM02,
4665	DIV_CAM03,
4666	ENABLE_ACLK_CAM00,
4667	ENABLE_ACLK_CAM01,
4668	ENABLE_ACLK_CAM02,
4669	ENABLE_PCLK_CAM0,
4670	ENABLE_SCLK_CAM0,
4671	ENABLE_IP_CAM00,
4672	ENABLE_IP_CAM01,
4673	ENABLE_IP_CAM02,
4674	ENABLE_IP_CAM03,
4675};
4676
4677static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
4678	{ MUX_SEL_CAM00, 0 },
4679	{ MUX_SEL_CAM01, 0 },
4680	{ MUX_SEL_CAM02, 0 },
4681	{ MUX_SEL_CAM03, 0 },
4682	{ MUX_SEL_CAM04, 0 },
4683};
4684
4685PNAME(mout_aclk_cam0_333_user_p)	= { "oscclk", "aclk_cam0_333", };
4686PNAME(mout_aclk_cam0_400_user_p)	= { "oscclk", "aclk_cam0_400", };
4687PNAME(mout_aclk_cam0_552_user_p)	= { "oscclk", "aclk_cam0_552", };
4688
4689PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4690					      "phyclk_rxbyteclkhs0_s4_phy", };
4691PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4692					       "phyclk_rxbyteclkhs0_s2a_phy", };
4693
4694PNAME(mout_aclk_lite_d_b_p)		= { "mout_aclk_lite_d_a",
4695					    "mout_aclk_cam0_333_user", };
4696PNAME(mout_aclk_lite_d_a_p)		= { "mout_aclk_cam0_552_user",
4697					    "mout_aclk_cam0_400_user", };
4698PNAME(mout_aclk_lite_b_b_p)		= { "mout_aclk_lite_b_a",
4699					    "mout_aclk_cam0_333_user", };
4700PNAME(mout_aclk_lite_b_a_p)		= { "mout_aclk_cam0_552_user",
4701					    "mout_aclk_cam0_400_user", };
4702PNAME(mout_aclk_lite_a_b_p)		= { "mout_aclk_lite_a_a",
4703					    "mout_aclk_cam0_333_user", };
4704PNAME(mout_aclk_lite_a_a_p)		= { "mout_aclk_cam0_552_user",
4705					    "mout_aclk_cam0_400_user", };
4706PNAME(mout_aclk_cam0_400_p)		= { "mout_aclk_cam0_400_user",
4707					    "mout_aclk_cam0_333_user", };
4708
4709PNAME(mout_aclk_csis1_b_p)		= { "mout_aclk_csis1_a",
4710					    "mout_aclk_cam0_333_user" };
4711PNAME(mout_aclk_csis1_a_p)		= { "mout_aclk_cam0_552_user",
4712					    "mout_aclk_cam0_400_user", };
4713PNAME(mout_aclk_csis0_b_p)		= { "mout_aclk_csis0_a",
4714					    "mout_aclk_cam0_333_user", };
4715PNAME(mout_aclk_csis0_a_p)		= { "mout_aclk_cam0_552_user",
4716					    "mout_aclk-cam0_400_user", };
4717PNAME(mout_aclk_3aa1_b_p)		= { "mout_aclk_3aa1_a",
4718					    "mout_aclk_cam0_333_user", };
4719PNAME(mout_aclk_3aa1_a_p)		= { "mout_aclk_cam0_552_user",
4720					    "mout_aclk_cam0_400_user", };
4721PNAME(mout_aclk_3aa0_b_p)		= { "mout_aclk_3aa0_a",
4722					    "mout_aclk_cam0_333_user", };
4723PNAME(mout_aclk_3aa0_a_p)		= { "mout_aclk_cam0_552_user",
4724					    "mout_aclk_cam0_400_user", };
4725
4726PNAME(mout_sclk_lite_freecnt_c_p)	= { "mout_sclk_lite_freecnt_b",
4727					    "div_pclk_lite_d", };
4728PNAME(mout_sclk_lite_freecnt_b_p)	= { "mout_sclk_lite_freecnt_a",
4729					    "div_pclk_pixelasync_lite_c", };
4730PNAME(mout_sclk_lite_freecnt_a_p)	= { "div_pclk_lite_a",
4731					    "div_pclk_lite_b", };
4732PNAME(mout_sclk_pixelasync_lite_c_b_p)	= { "mout_sclk_pixelasync_lite_c_a",
4733					    "mout_aclk_cam0_333_user", };
4734PNAME(mout_sclk_pixelasync_lite_c_a_p)	= { "mout_aclk_cam0_552_user",
4735					    "mout_aclk_cam0_400_user", };
4736PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4737					"mout_sclk_pixelasync_lite_c_init_a",
4738					"mout_aclk_cam0_400_user", };
4739PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4740					"mout_aclk_cam0_552_user",
4741					"mout_aclk_cam0_400_user", };
4742
4743static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4744	FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4745			NULL, 0, 100000000),
4746	FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4747			NULL, 0, 100000000),
4748};
4749
4750static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4751	/* MUX_SEL_CAM00 */
4752	MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4753			mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4754	MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4755			mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4756	MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4757			mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4758
4759	/* MUX_SEL_CAM01 */
4760	MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4761			"mout_phyclk_rxbyteclkhs0_s4_user",
4762			mout_phyclk_rxbyteclkhs0_s4_user_p,
4763			MUX_SEL_CAM01, 4, 1),
4764	MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4765			"mout_phyclk_rxbyteclkhs0_s2a_user",
4766			mout_phyclk_rxbyteclkhs0_s2a_user_p,
4767			MUX_SEL_CAM01, 0, 1),
4768
4769	/* MUX_SEL_CAM02 */
4770	MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4771			MUX_SEL_CAM02, 24, 1),
4772	MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4773			MUX_SEL_CAM02, 20, 1),
4774	MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4775			MUX_SEL_CAM02, 16, 1),
4776	MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4777			MUX_SEL_CAM02, 12, 1),
4778	MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4779			MUX_SEL_CAM02, 8, 1),
4780	MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4781			MUX_SEL_CAM02, 4, 1),
4782	MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4783			MUX_SEL_CAM02, 0, 1),
4784
4785	/* MUX_SEL_CAM03 */
4786	MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4787			MUX_SEL_CAM03, 28, 1),
4788	MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4789			MUX_SEL_CAM03, 24, 1),
4790	MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4791			MUX_SEL_CAM03, 20, 1),
4792	MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4793			MUX_SEL_CAM03, 16, 1),
4794	MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4795			MUX_SEL_CAM03, 12, 1),
4796	MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4797			MUX_SEL_CAM03, 8, 1),
4798	MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4799			MUX_SEL_CAM03, 4, 1),
4800	MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4801			MUX_SEL_CAM03, 0, 1),
4802
4803	/* MUX_SEL_CAM04 */
4804	MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4805			mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4806	MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4807			mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4808	MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4809			mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4810	MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4811			mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4812	MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4813			mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4814	MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4815			"mout_sclk_pixelasync_lite_c_init_b",
4816			mout_sclk_pixelasync_lite_c_init_b_p,
4817			MUX_SEL_CAM04, 4, 1),
4818	MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4819			"mout_sclk_pixelasync_lite_c_init_a",
4820			mout_sclk_pixelasync_lite_c_init_a_p,
4821			MUX_SEL_CAM04, 0, 1),
4822};
4823
4824static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4825	/* DIV_CAM00 */
4826	DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4827			DIV_CAM00, 8, 2),
4828	DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4829			DIV_CAM00, 4, 3),
4830	DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4831			"mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4832
4833	/* DIV_CAM01 */
4834	DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4835			DIV_CAM01, 20, 2),
4836	DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4837			DIV_CAM01, 16, 3),
4838	DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4839			DIV_CAM01, 12, 2),
4840	DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4841			DIV_CAM01, 8, 3),
4842	DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4843			DIV_CAM01, 4, 2),
4844	DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4845			DIV_CAM01, 0, 3),
4846
4847	/* DIV_CAM02 */
4848	DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4849			DIV_CAM02, 20, 3),
4850	DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4851			DIV_CAM02, 16, 3),
4852	DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4853			DIV_CAM02, 12, 2),
4854	DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4855			DIV_CAM02, 8, 3),
4856	DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4857			DIV_CAM02, 4, 2),
4858	DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4859			DIV_CAM02, 0, 3),
4860
4861	/* DIV_CAM03 */
4862	DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4863			"mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4864	DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4865			"div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4866	DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4867			"div_sclk_pixelasync_lite_c_init",
4868			"mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4869};
4870
4871static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4872	/* ENABLE_ACLK_CAM00 */
4873	GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4874			6, 0, 0),
4875	GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4876			5, 0, 0),
4877	GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4878			4, 0, 0),
4879	GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4880			3, 0, 0),
4881	GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4882			ENABLE_ACLK_CAM00, 2, 0, 0),
4883	GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4884			ENABLE_ACLK_CAM00, 1, 0, 0),
4885	GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4886			ENABLE_ACLK_CAM00, 0, 0, 0),
4887
4888	/* ENABLE_ACLK_CAM01 */
4889	GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4890			ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4891	GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4892			ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4893	GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4894			ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4895	GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4896			ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4897	GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4898			ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4899	GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4900			ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4901	GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4902			ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4903	GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4904			ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4905	GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4906			"div_pclk_lite_d", ENABLE_ACLK_CAM01,
4907			23, CLK_IGNORE_UNUSED, 0),
4908	GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4909			"div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4910			22, CLK_IGNORE_UNUSED, 0),
4911	GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4912			"div_pclk_lite_b", ENABLE_ACLK_CAM01,
4913			21, CLK_IGNORE_UNUSED, 0),
4914	GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4915			"div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4916			20, CLK_IGNORE_UNUSED, 0),
4917	GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4918			"div_pclk_lite_a", ENABLE_ACLK_CAM01,
4919			19, CLK_IGNORE_UNUSED, 0),
4920	GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4921			"div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4922			18, CLK_IGNORE_UNUSED, 0),
4923	GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4924			"div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4925			17, CLK_IGNORE_UNUSED, 0),
4926	GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4927			"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4928			16, CLK_IGNORE_UNUSED, 0),
4929	GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4930			"div_aclk_3aa1", ENABLE_ACLK_CAM01,
4931			15, CLK_IGNORE_UNUSED, 0),
4932	GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4933			"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4934			14, CLK_IGNORE_UNUSED, 0),
4935	GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4936			"div_aclk_3aa0", ENABLE_ACLK_CAM01,
4937			13, CLK_IGNORE_UNUSED, 0),
4938	GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4939			"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4940			12, CLK_IGNORE_UNUSED, 0),
4941	GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4942			"div_aclk_lite_d", ENABLE_ACLK_CAM01,
4943			11, CLK_IGNORE_UNUSED, 0),
4944	GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4945			"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4946			10, CLK_IGNORE_UNUSED, 0),
4947	GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4948			"div_aclk_lite_b", ENABLE_ACLK_CAM01,
4949			9, CLK_IGNORE_UNUSED, 0),
4950	GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4951			"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4952			8, CLK_IGNORE_UNUSED, 0),
4953	GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4954			"div_aclk_lite_a", ENABLE_ACLK_CAM01,
4955			7, CLK_IGNORE_UNUSED, 0),
4956	GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4957			"div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4958			6, CLK_IGNORE_UNUSED, 0),
4959	GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4960			ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4961	GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4962			ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4963	GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4964			ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4965	GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4966			ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4967	GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4968			ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4969	GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4970			ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4971
4972	/* ENABLE_ACLK_CAM02 */
4973	GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4974			ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4975	GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4976			ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4977	GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4978			ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4979	GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4980			ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4981	GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4982			ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4983	GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4984			ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4985	GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4986			ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4987	GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4988			ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4989	GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4990			ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4991	GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4992			ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4993
4994	/* ENABLE_PCLK_CAM0 */
4995	GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4996			ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4997	GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4998			ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4999	GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
5000			ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
5001	GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
5002			ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
5003	GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
5004			ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
5005	GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
5006			ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
5007	GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
5008			ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
5009	GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
5010			ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
5011	GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
5012			ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
5013	GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
5014			ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
5015	GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
5016			ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
5017	GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
5018			ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
5019	GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
5020			ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
5021	GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
5022			"div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5023			12, CLK_IGNORE_UNUSED, 0),
5024	GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
5025			"div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5026			11, CLK_IGNORE_UNUSED, 0),
5027	GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
5028			"div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5029			10, CLK_IGNORE_UNUSED, 0),
5030	GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
5031			ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5032	GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
5033			ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5034	GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
5035			"div_aclk_cam0_200", ENABLE_PCLK_CAM0,
5036			7, CLK_IGNORE_UNUSED, 0),
5037	GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
5038			ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5039	GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
5040			ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5041	GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
5042			ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5043	GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
5044			ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5045	GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
5046			ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5047	GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
5048			ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5049	GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
5050			ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5051
5052	/* ENABLE_SCLK_CAM0 */
5053	GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5054			"mout_phyclk_rxbyteclkhs0_s4_user",
5055			ENABLE_SCLK_CAM0, 8, 0, 0),
5056	GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5057			"mout_phyclk_rxbyteclkhs0_s2a_user",
5058			ENABLE_SCLK_CAM0, 7, 0, 0),
5059	GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5060			"mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5061	GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5062			"div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5063	GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5064			"div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5065	GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5066			"div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5067	GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5068			"div_sclk_pixelasync_lite_c",
5069			ENABLE_SCLK_CAM0, 2, 0, 0),
5070	GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5071			"div_sclk_pixelasync_lite_c_init",
5072			ENABLE_SCLK_CAM0, 1, 0, 0),
5073	GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5074			"div_sclk_pixelasync_lite_c",
5075			ENABLE_SCLK_CAM0, 0, 0, 0),
5076};
5077
5078static const struct samsung_cmu_info cam0_cmu_info __initconst = {
5079	.mux_clks		= cam0_mux_clks,
5080	.nr_mux_clks		= ARRAY_SIZE(cam0_mux_clks),
5081	.div_clks		= cam0_div_clks,
5082	.nr_div_clks		= ARRAY_SIZE(cam0_div_clks),
5083	.gate_clks		= cam0_gate_clks,
5084	.nr_gate_clks		= ARRAY_SIZE(cam0_gate_clks),
5085	.fixed_clks		= cam0_fixed_clks,
5086	.nr_fixed_clks		= ARRAY_SIZE(cam0_fixed_clks),
5087	.nr_clk_ids		= CLKS_NR_CAM0,
5088	.clk_regs		= cam0_clk_regs,
5089	.nr_clk_regs		= ARRAY_SIZE(cam0_clk_regs),
5090	.suspend_regs		= cam0_suspend_regs,
5091	.nr_suspend_regs	= ARRAY_SIZE(cam0_suspend_regs),
5092	.clk_name		= "aclk_cam0_400",
5093};
5094
5095/*
5096 * Register offset definitions for CMU_CAM1
5097 */
5098#define MUX_SEL_CAM10			0x0200
5099#define MUX_SEL_CAM11			0x0204
5100#define MUX_SEL_CAM12			0x0208
5101#define MUX_ENABLE_CAM10		0x0300
5102#define MUX_ENABLE_CAM11		0x0304
5103#define MUX_ENABLE_CAM12		0x0308
5104#define MUX_STAT_CAM10			0x0400
5105#define MUX_STAT_CAM11			0x0404
5106#define MUX_STAT_CAM12			0x0408
5107#define MUX_IGNORE_CAM11		0x0504
5108#define DIV_CAM10			0x0600
5109#define DIV_CAM11			0x0604
5110#define DIV_STAT_CAM10			0x0700
5111#define DIV_STAT_CAM11			0x0704
5112#define ENABLE_ACLK_CAM10		0X0800
5113#define ENABLE_ACLK_CAM11		0X0804
5114#define ENABLE_ACLK_CAM12		0X0808
5115#define ENABLE_PCLK_CAM1		0X0900
5116#define ENABLE_SCLK_CAM1		0X0a00
5117#define ENABLE_IP_CAM10			0X0b00
5118#define ENABLE_IP_CAM11			0X0b04
5119#define ENABLE_IP_CAM12			0X0b08
5120
5121static const unsigned long cam1_clk_regs[] __initconst = {
5122	MUX_SEL_CAM10,
5123	MUX_SEL_CAM11,
5124	MUX_SEL_CAM12,
5125	MUX_ENABLE_CAM10,
5126	MUX_ENABLE_CAM11,
5127	MUX_ENABLE_CAM12,
5128	MUX_IGNORE_CAM11,
5129	DIV_CAM10,
5130	DIV_CAM11,
5131	ENABLE_ACLK_CAM10,
5132	ENABLE_ACLK_CAM11,
5133	ENABLE_ACLK_CAM12,
5134	ENABLE_PCLK_CAM1,
5135	ENABLE_SCLK_CAM1,
5136	ENABLE_IP_CAM10,
5137	ENABLE_IP_CAM11,
5138	ENABLE_IP_CAM12,
5139};
5140
5141static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
5142	{ MUX_SEL_CAM10, 0 },
5143	{ MUX_SEL_CAM11, 0 },
5144	{ MUX_SEL_CAM12, 0 },
5145};
5146
5147PNAME(mout_sclk_isp_uart_user_p)	= { "oscclk", "sclk_isp_uart_cam1", };
5148PNAME(mout_sclk_isp_spi1_user_p)	= { "oscclk", "sclk_isp_spi1_cam1", };
5149PNAME(mout_sclk_isp_spi0_user_p)	= { "oscclk", "sclk_isp_spi0_cam1", };
5150
5151PNAME(mout_aclk_cam1_333_user_p)	= { "oscclk", "aclk_cam1_333", };
5152PNAME(mout_aclk_cam1_400_user_p)	= { "oscclk", "aclk_cam1_400", };
5153PNAME(mout_aclk_cam1_552_user_p)	= { "oscclk", "aclk_cam1_552", };
5154
5155PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5156					       "phyclk_rxbyteclkhs0_s2b_phy", };
5157
5158PNAME(mout_aclk_csis2_b_p)		= { "mout_aclk_csis2_a",
5159					    "mout_aclk_cam1_333_user", };
5160PNAME(mout_aclk_csis2_a_p)		= { "mout_aclk_cam1_552_user",
5161					    "mout_aclk_cam1_400_user", };
5162
5163PNAME(mout_aclk_fd_b_p)			= { "mout_aclk_fd_a",
5164					    "mout_aclk_cam1_333_user", };
5165PNAME(mout_aclk_fd_a_p)			= { "mout_aclk_cam1_552_user",
5166					    "mout_aclk_cam1_400_user", };
5167
5168PNAME(mout_aclk_lite_c_b_p)		= { "mout_aclk_lite_c_a",
5169					    "mout_aclk_cam1_333_user", };
5170PNAME(mout_aclk_lite_c_a_p)		= { "mout_aclk_cam1_552_user",
5171					    "mout_aclk_cam1_400_user", };
5172
5173static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5174	FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5175			0, 100000000),
5176};
5177
5178static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5179	/* MUX_SEL_CAM10 */
5180	MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5181			mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5182	MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5183			mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5184	MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5185			mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5186	MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5187			mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5188	MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5189			mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5190	MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5191			mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5192
5193	/* MUX_SEL_CAM11 */
5194	MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5195			"mout_phyclk_rxbyteclkhs0_s2b_user",
5196			mout_phyclk_rxbyteclkhs0_s2b_user_p,
5197			MUX_SEL_CAM11, 0, 1),
5198
5199	/* MUX_SEL_CAM12 */
5200	MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5201			MUX_SEL_CAM12, 20, 1),
5202	MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5203			MUX_SEL_CAM12, 16, 1),
5204	MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5205			MUX_SEL_CAM12, 12, 1),
5206	MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5207			MUX_SEL_CAM12, 8, 1),
5208	MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5209			MUX_SEL_CAM12, 4, 1),
5210	MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5211			MUX_SEL_CAM12, 0, 1),
5212};
5213
5214static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5215	/* DIV_CAM10 */
5216	DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5217			"div_pclk_cam1_83", DIV_CAM10, 16, 2),
5218	DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5219			"mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5220	DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5221			"mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5222	DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5223			"mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5224	DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5225			DIV_CAM10, 0, 3),
5226
5227	/* DIV_CAM11 */
5228	DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5229			DIV_CAM11, 16, 3),
5230	DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5231	DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5232	DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5233			DIV_CAM11, 4, 2),
5234	DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5235			DIV_CAM11, 0, 3),
5236};
5237
5238static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5239	/* ENABLE_ACLK_CAM10 */
5240	GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5241			ENABLE_ACLK_CAM10, 4, 0, 0),
5242	GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5243			ENABLE_ACLK_CAM10, 3, 0, 0),
5244	GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5245			ENABLE_ACLK_CAM10, 1, 0, 0),
5246	GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5247			ENABLE_ACLK_CAM10, 0, 0, 0),
5248
5249	/* ENABLE_ACLK_CAM11 */
5250	GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5251			ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5252	GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5253			ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5254	GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5255			"div_pclk_lite_c", ENABLE_ACLK_CAM11,
5256			27, CLK_IGNORE_UNUSED, 0),
5257	GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5258			"div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5259			26, CLK_IGNORE_UNUSED, 0),
5260	GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5261			"div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5262			25, CLK_IGNORE_UNUSED, 0),
5263	GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5264			"div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5265			24, CLK_IGNORE_UNUSED, 0),
5266	GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5267			"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5268			23, CLK_IGNORE_UNUSED, 0),
5269	GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5270			"mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5271			22, CLK_IGNORE_UNUSED, 0),
5272	GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5273			"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5274			21, CLK_IGNORE_UNUSED, 0),
5275	GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5276			"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5277			20, CLK_IGNORE_UNUSED, 0),
5278	GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5279			"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5280			19, CLK_IGNORE_UNUSED, 0),
5281	GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5282			"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5283			18, CLK_IGNORE_UNUSED, 0),
5284	GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5285			"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5286			17, CLK_IGNORE_UNUSED, 0),
5287	GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5288			"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5289			16, CLK_IGNORE_UNUSED, 0),
5290	GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5291			"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5292			15, CLK_IGNORE_UNUSED, 0),
5293	GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5294			ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5295	GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5296			"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5297			13, CLK_IGNORE_UNUSED, 0),
5298	GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5299			"div_aclk_lite_c", ENABLE_ACLK_CAM11,
5300			12, CLK_IGNORE_UNUSED, 0),
5301	GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5302			ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5303	GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5304			ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5305	GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5306			"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5307			9, CLK_IGNORE_UNUSED, 0),
5308	GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5309			ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5310	GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5311			ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5312	GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5313			ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5314	GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5315			ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5316	GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5317			ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5318	GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5319			ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5320	GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5321			ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5322	GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5323			ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5324	GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5325			ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5326
5327	/* ENABLE_ACLK_CAM12 */
5328	GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5329			"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5330			10, CLK_IGNORE_UNUSED, 0),
5331	GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5332			ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5333	GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5334			"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5335			8, CLK_IGNORE_UNUSED, 0),
5336	GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5337			ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5338	GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5339			ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5340	GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5341			ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5342	GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5343			"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5344			4, CLK_IGNORE_UNUSED, 0),
5345	GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5346			"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5347			3, CLK_IGNORE_UNUSED, 0),
5348	GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5349			"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5350			2, CLK_IGNORE_UNUSED, 0),
5351	GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5352			ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5353	GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5354			"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5355			0, CLK_IGNORE_UNUSED, 0),
5356
5357	/* ENABLE_PCLK_CAM1 */
5358	GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5359			ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5360	GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5361			ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5362	GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5363			ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5364	GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5365			ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5366	GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5367			ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5368	GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5369			ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5370	GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5371			ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5372	GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5373			"div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5374			20, CLK_IGNORE_UNUSED, 0),
5375	GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5376			"div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5377			19, CLK_IGNORE_UNUSED, 0),
5378	GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5379			ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5380	GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5381			"div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5382			17, CLK_IGNORE_UNUSED, 0),
5383	GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5384			ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5385	GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5386			ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5387	GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5388			"div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5389			14, CLK_IGNORE_UNUSED, 0),
5390	GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5391			ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5392	GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5393			ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5394	GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5395			ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5396	GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5397			ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5398	GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5399			ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5400	GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5401			ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5402	GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5403			ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5404	GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5405			ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5406	GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5407			ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5408	GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5409			ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5410	GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5411			ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5412	GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5413			ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5414	GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5415			ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5416	GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5417			ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5418
5419	/* ENABLE_SCLK_CAM1 */
5420	GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5421			15, 0, 0),
5422	GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5423			14, 0, 0),
5424	GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5425			13, 0, 0),
5426	GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5427			12, 0, 0),
5428	GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5429			"mout_phyclk_rxbyteclkhs0_s2b_user",
5430			ENABLE_SCLK_CAM1, 11, 0, 0),
5431	GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5432			ENABLE_SCLK_CAM1, 10, 0, 0),
5433	GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5434			ENABLE_SCLK_CAM1, 9, 0, 0),
5435	GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5436			ENABLE_SCLK_CAM1, 7, 0, 0),
5437	GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5438			ENABLE_SCLK_CAM1, 6, 0, 0),
5439	GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5440			ENABLE_SCLK_CAM1, 5, 0, 0),
5441	GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5442			ENABLE_SCLK_CAM1, 4, 0, 0),
5443	GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5444			ENABLE_SCLK_CAM1, 3, 0, 0),
5445	GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5446			ENABLE_SCLK_CAM1, 2, 0, 0),
5447	GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5448			ENABLE_SCLK_CAM1, 1, 0, 0),
5449	GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5450			ENABLE_SCLK_CAM1, 0, 0, 0),
5451};
5452
5453static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5454	.mux_clks		= cam1_mux_clks,
5455	.nr_mux_clks		= ARRAY_SIZE(cam1_mux_clks),
5456	.div_clks		= cam1_div_clks,
5457	.nr_div_clks		= ARRAY_SIZE(cam1_div_clks),
5458	.gate_clks		= cam1_gate_clks,
5459	.nr_gate_clks		= ARRAY_SIZE(cam1_gate_clks),
5460	.fixed_clks		= cam1_fixed_clks,
5461	.nr_fixed_clks		= ARRAY_SIZE(cam1_fixed_clks),
5462	.nr_clk_ids		= CLKS_NR_CAM1,
5463	.clk_regs		= cam1_clk_regs,
5464	.nr_clk_regs		= ARRAY_SIZE(cam1_clk_regs),
5465	.suspend_regs		= cam1_suspend_regs,
5466	.nr_suspend_regs	= ARRAY_SIZE(cam1_suspend_regs),
5467	.clk_name		= "aclk_cam1_400",
5468};
5469
5470/*
5471 * Register offset definitions for CMU_IMEM
5472 */
5473#define ENABLE_ACLK_IMEM_SLIMSSS		0x080c
5474#define ENABLE_PCLK_IMEM_SLIMSSS		0x0908
5475
5476static const unsigned long imem_clk_regs[] __initconst = {
5477	ENABLE_ACLK_IMEM_SLIMSSS,
5478	ENABLE_PCLK_IMEM_SLIMSSS,
5479};
5480
5481static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
5482	/* ENABLE_ACLK_IMEM_SLIMSSS */
5483	GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
5484			ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5485
5486	/* ENABLE_PCLK_IMEM_SLIMSSS */
5487	GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
5488			ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5489};
5490
5491static const struct samsung_cmu_info imem_cmu_info __initconst = {
5492	.gate_clks		= imem_gate_clks,
5493	.nr_gate_clks		= ARRAY_SIZE(imem_gate_clks),
5494	.nr_clk_ids		= CLKS_NR_IMEM,
5495	.clk_regs		= imem_clk_regs,
5496	.nr_clk_regs		= ARRAY_SIZE(imem_clk_regs),
5497	.clk_name		= "aclk_imem_200",
5498};
5499
5500static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5501{
5502	return exynos_arm64_register_cmu_pm(pdev, false);
5503}
5504
5505static const struct of_device_id exynos5433_cmu_of_match[] = {
5506	{
5507		.compatible = "samsung,exynos5433-cmu-aud",
5508		.data = &aud_cmu_info,
5509	}, {
5510		.compatible = "samsung,exynos5433-cmu-cam0",
5511		.data = &cam0_cmu_info,
5512	}, {
5513		.compatible = "samsung,exynos5433-cmu-cam1",
5514		.data = &cam1_cmu_info,
5515	}, {
5516		.compatible = "samsung,exynos5433-cmu-disp",
5517		.data = &disp_cmu_info,
5518	}, {
5519		.compatible = "samsung,exynos5433-cmu-g2d",
5520		.data = &g2d_cmu_info,
5521	}, {
5522		.compatible = "samsung,exynos5433-cmu-g3d",
5523		.data = &g3d_cmu_info,
5524	}, {
5525		.compatible = "samsung,exynos5433-cmu-fsys",
5526		.data = &fsys_cmu_info,
5527	}, {
5528		.compatible = "samsung,exynos5433-cmu-gscl",
5529		.data = &gscl_cmu_info,
5530	}, {
5531		.compatible = "samsung,exynos5433-cmu-mfc",
5532		.data = &mfc_cmu_info,
5533	}, {
5534		.compatible = "samsung,exynos5433-cmu-hevc",
5535		.data = &hevc_cmu_info,
5536	}, {
5537		.compatible = "samsung,exynos5433-cmu-isp",
5538		.data = &isp_cmu_info,
5539	}, {
5540		.compatible = "samsung,exynos5433-cmu-mscl",
5541		.data = &mscl_cmu_info,
5542	}, {
5543		.compatible = "samsung,exynos5433-cmu-imem",
5544		.data = &imem_cmu_info,
5545	}, {
5546	},
5547};
5548
5549static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
5550	SET_RUNTIME_PM_OPS(exynos_arm64_cmu_suspend, exynos_arm64_cmu_resume,
5551			   NULL)
5552	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5553				     pm_runtime_force_resume)
5554};
5555
5556static struct platform_driver exynos5433_cmu_driver __refdata = {
5557	.driver	= {
5558		.name = "exynos5433-cmu",
5559		.of_match_table = exynos5433_cmu_of_match,
5560		.suppress_bind_attrs = true,
5561		.pm = &exynos5433_cmu_pm_ops,
5562	},
5563	.probe = exynos5433_cmu_probe,
5564};
5565
5566static int __init exynos5433_cmu_init(void)
5567{
5568	return platform_driver_register(&exynos5433_cmu_driver);
5569}
5570core_initcall(exynos5433_cmu_init);