clk-exynos5420.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   4 * Authors: Thomas Abraham <thomas.ab@samsung.com>
   5 *	    Chander Kashyap <k.chander@samsung.com>
   6 *
   7 * Common Clock Framework support for Exynos5420 SoC.
   8 */
   9
  10#include <dt-bindings/clock/exynos5420.h>
  11#include <linux/slab.h>
  12#include <linux/clk-provider.h>
  13#include <linux/mod_devicetable.h>
  14#include <linux/of.h>
  15#include <linux/of_address.h>
  16#include <linux/clk.h>
  17
  18#include "clk.h"
  19#include "clk-cpu.h"
  20#include "clk-exynos5-subcmu.h"
  21
  22#define APLL_LOCK		0x0
  23#define APLL_CON0		0x100
  24#define SRC_CPU			0x200
  25#define DIV_CPU0		0x500
  26#define DIV_CPU1		0x504
  27#define GATE_BUS_CPU		0x700
  28#define GATE_SCLK_CPU		0x800
  29#define CLKOUT_CMU_CPU		0xa00
  30#define SRC_MASK_CPERI		0x4300
  31#define GATE_IP_G2D		0x8800
  32#define CPLL_LOCK		0x10020
  33#define DPLL_LOCK		0x10030
  34#define EPLL_LOCK		0x10040
  35#define RPLL_LOCK		0x10050
  36#define IPLL_LOCK		0x10060
  37#define SPLL_LOCK		0x10070
  38#define VPLL_LOCK		0x10080
  39#define MPLL_LOCK		0x10090
  40#define CPLL_CON0		0x10120
  41#define DPLL_CON0		0x10128
  42#define EPLL_CON0		0x10130
  43#define EPLL_CON1		0x10134
  44#define EPLL_CON2		0x10138
  45#define RPLL_CON0		0x10140
  46#define RPLL_CON1		0x10144
  47#define RPLL_CON2		0x10148
  48#define IPLL_CON0		0x10150
  49#define SPLL_CON0		0x10160
  50#define VPLL_CON0		0x10170
  51#define MPLL_CON0		0x10180
  52#define SRC_TOP0		0x10200
  53#define SRC_TOP1		0x10204
  54#define SRC_TOP2		0x10208
  55#define SRC_TOP3		0x1020c
  56#define SRC_TOP4		0x10210
  57#define SRC_TOP5		0x10214
  58#define SRC_TOP6		0x10218
  59#define SRC_TOP7		0x1021c
  60#define SRC_TOP8		0x10220 /* 5800 specific */
  61#define SRC_TOP9		0x10224 /* 5800 specific */
  62#define SRC_DISP10		0x1022c
  63#define SRC_MAU			0x10240
  64#define SRC_FSYS		0x10244
  65#define SRC_PERIC0		0x10250
  66#define SRC_PERIC1		0x10254
  67#define SRC_ISP			0x10270
  68#define SRC_CAM			0x10274 /* 5800 specific */
  69#define SRC_TOP10		0x10280
  70#define SRC_TOP11		0x10284
  71#define SRC_TOP12		0x10288
  72#define SRC_TOP13		0x1028c /* 5800 specific */
  73#define SRC_MASK_TOP0		0x10300
  74#define SRC_MASK_TOP1		0x10304
  75#define SRC_MASK_TOP2		0x10308
  76#define SRC_MASK_TOP7		0x1031c
  77#define SRC_MASK_DISP10		0x1032c
  78#define SRC_MASK_MAU		0x10334
  79#define SRC_MASK_FSYS		0x10340
  80#define SRC_MASK_PERIC0		0x10350
  81#define SRC_MASK_PERIC1		0x10354
  82#define SRC_MASK_ISP		0x10370
  83#define DIV_TOP0		0x10500
  84#define DIV_TOP1		0x10504
  85#define DIV_TOP2		0x10508
  86#define DIV_TOP8		0x10520 /* 5800 specific */
  87#define DIV_TOP9		0x10524 /* 5800 specific */
  88#define DIV_DISP10		0x1052c
  89#define DIV_MAU			0x10544
  90#define DIV_FSYS0		0x10548
  91#define DIV_FSYS1		0x1054c
  92#define DIV_FSYS2		0x10550
  93#define DIV_PERIC0		0x10558
  94#define DIV_PERIC1		0x1055c
  95#define DIV_PERIC2		0x10560
  96#define DIV_PERIC3		0x10564
  97#define DIV_PERIC4		0x10568
  98#define DIV_CAM			0x10574 /* 5800 specific */
  99#define SCLK_DIV_ISP0		0x10580
 100#define SCLK_DIV_ISP1		0x10584
 101#define DIV2_RATIO0		0x10590
 102#define DIV4_RATIO		0x105a0
 103#define GATE_BUS_TOP		0x10700
 104#define GATE_BUS_DISP1		0x10728
 105#define GATE_BUS_GEN		0x1073c
 106#define GATE_BUS_FSYS0		0x10740
 107#define GATE_BUS_FSYS2		0x10748
 108#define GATE_BUS_PERIC		0x10750
 109#define GATE_BUS_PERIC1		0x10754
 110#define GATE_BUS_PERIS0		0x10760
 111#define GATE_BUS_PERIS1		0x10764
 112#define GATE_BUS_NOC		0x10770
 113#define GATE_TOP_SCLK_ISP	0x10870
 114#define GATE_IP_GSCL0		0x10910
 115#define GATE_IP_GSCL1		0x10920
 116#define GATE_IP_CAM		0x10924 /* 5800 specific */
 117#define GATE_IP_MFC		0x1092c
 118#define GATE_IP_DISP1		0x10928
 119#define GATE_IP_G3D		0x10930
 120#define GATE_IP_GEN		0x10934
 121#define GATE_IP_FSYS		0x10944
 122#define GATE_IP_PERIC		0x10950
 123#define GATE_IP_PERIS		0x10960
 124#define GATE_IP_MSCL		0x10970
 125#define GATE_TOP_SCLK_GSCL	0x10820
 126#define GATE_TOP_SCLK_DISP1	0x10828
 127#define GATE_TOP_SCLK_MAU	0x1083c
 128#define GATE_TOP_SCLK_FSYS	0x10840
 129#define GATE_TOP_SCLK_PERIC	0x10850
 130#define TOP_SPARE2		0x10b08
 131#define BPLL_LOCK		0x20010
 132#define BPLL_CON0		0x20110
 133#define SRC_CDREX		0x20200
 134#define DIV_CDREX0		0x20500
 135#define DIV_CDREX1		0x20504
 136#define GATE_BUS_CDREX0		0x20700
 137#define GATE_BUS_CDREX1		0x20704
 138#define KPLL_LOCK		0x28000
 139#define KPLL_CON0		0x28100
 140#define SRC_KFC			0x28200
 141#define DIV_KFC0		0x28500
 142
 143/* NOTE: Must be equal to the last clock ID increased by one */
 144#define CLKS_NR			(CLK_DOUT_PCLK_DREX1 + 1)
 145
 146/* Exynos5x SoC type */
 147enum exynos5x_soc {
 148	EXYNOS5420,
 149	EXYNOS5800,
 150};
 151
 152/* list of PLLs */
 153enum exynos5x_plls {
 154	apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
 155	bpll, kpll,
 156	nr_plls			/* number of PLLs */
 157};
 158
 159static void __iomem *reg_base;
 160static enum exynos5x_soc exynos5x_soc;
 161
 162/*
 163 * list of controller registers to be saved and restored during a
 164 * suspend/resume cycle.
 165 */
 166static const unsigned long exynos5x_clk_regs[] __initconst = {
 167	SRC_CPU,
 168	DIV_CPU0,
 169	DIV_CPU1,
 170	GATE_BUS_CPU,
 171	GATE_SCLK_CPU,
 172	CLKOUT_CMU_CPU,
 173	APLL_CON0,
 174	KPLL_CON0,
 175	CPLL_CON0,
 176	DPLL_CON0,
 177	EPLL_CON0,
 178	EPLL_CON1,
 179	EPLL_CON2,
 180	RPLL_CON0,
 181	RPLL_CON1,
 182	RPLL_CON2,
 183	IPLL_CON0,
 184	SPLL_CON0,
 185	VPLL_CON0,
 186	MPLL_CON0,
 187	SRC_TOP0,
 188	SRC_TOP1,
 189	SRC_TOP2,
 190	SRC_TOP3,
 191	SRC_TOP4,
 192	SRC_TOP5,
 193	SRC_TOP6,
 194	SRC_TOP7,
 195	SRC_DISP10,
 196	SRC_MAU,
 197	SRC_FSYS,
 198	SRC_PERIC0,
 199	SRC_PERIC1,
 200	SRC_TOP10,
 201	SRC_TOP11,
 202	SRC_TOP12,
 203	SRC_MASK_TOP2,
 204	SRC_MASK_TOP7,
 205	SRC_MASK_DISP10,
 206	SRC_MASK_FSYS,
 207	SRC_MASK_PERIC0,
 208	SRC_MASK_PERIC1,
 209	SRC_MASK_TOP0,
 210	SRC_MASK_TOP1,
 211	SRC_MASK_MAU,
 212	SRC_MASK_ISP,
 213	SRC_ISP,
 214	DIV_TOP0,
 215	DIV_TOP1,
 216	DIV_TOP2,
 217	DIV_DISP10,
 218	DIV_MAU,
 219	DIV_FSYS0,
 220	DIV_FSYS1,
 221	DIV_FSYS2,
 222	DIV_PERIC0,
 223	DIV_PERIC1,
 224	DIV_PERIC2,
 225	DIV_PERIC3,
 226	DIV_PERIC4,
 227	SCLK_DIV_ISP0,
 228	SCLK_DIV_ISP1,
 229	DIV2_RATIO0,
 230	DIV4_RATIO,
 231	GATE_BUS_DISP1,
 232	GATE_BUS_TOP,
 233	GATE_BUS_GEN,
 234	GATE_BUS_FSYS0,
 235	GATE_BUS_FSYS2,
 236	GATE_BUS_PERIC,
 237	GATE_BUS_PERIC1,
 238	GATE_BUS_PERIS0,
 239	GATE_BUS_PERIS1,
 240	GATE_BUS_NOC,
 241	GATE_TOP_SCLK_ISP,
 242	GATE_IP_GSCL0,
 243	GATE_IP_GSCL1,
 244	GATE_IP_MFC,
 245	GATE_IP_DISP1,
 246	GATE_IP_G3D,
 247	GATE_IP_GEN,
 248	GATE_IP_FSYS,
 249	GATE_IP_PERIC,
 250	GATE_IP_PERIS,
 251	GATE_IP_MSCL,
 252	GATE_TOP_SCLK_GSCL,
 253	GATE_TOP_SCLK_DISP1,
 254	GATE_TOP_SCLK_MAU,
 255	GATE_TOP_SCLK_FSYS,
 256	GATE_TOP_SCLK_PERIC,
 257	TOP_SPARE2,
 258	SRC_CDREX,
 259	DIV_CDREX0,
 260	DIV_CDREX1,
 261	SRC_KFC,
 262	DIV_KFC0,
 263	GATE_BUS_CDREX0,
 264	GATE_BUS_CDREX1,
 265};
 266
 267static const unsigned long exynos5800_clk_regs[] __initconst = {
 268	SRC_TOP8,
 269	SRC_TOP9,
 270	SRC_CAM,
 271	SRC_TOP1,
 272	DIV_TOP8,
 273	DIV_TOP9,
 274	DIV_CAM,
 275	GATE_IP_CAM,
 276};
 277
 278static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
 279	{ .offset = SRC_MASK_CPERI,		.value = 0xffffffff, },
 280	{ .offset = SRC_MASK_TOP0,		.value = 0x11111111, },
 281	{ .offset = SRC_MASK_TOP1,		.value = 0x11101111, },
 282	{ .offset = SRC_MASK_TOP2,		.value = 0x11111110, },
 283	{ .offset = SRC_MASK_TOP7,		.value = 0x00111100, },
 284	{ .offset = SRC_MASK_DISP10,		.value = 0x11111110, },
 285	{ .offset = SRC_MASK_MAU,		.value = 0x10000000, },
 286	{ .offset = SRC_MASK_FSYS,		.value = 0x11111110, },
 287	{ .offset = SRC_MASK_PERIC0,		.value = 0x11111110, },
 288	{ .offset = SRC_MASK_PERIC1,		.value = 0x11111100, },
 289	{ .offset = SRC_MASK_ISP,		.value = 0x11111000, },
 290	{ .offset = GATE_BUS_TOP,		.value = 0xffffffff, },
 291	{ .offset = GATE_BUS_DISP1,		.value = 0xffffffff, },
 292	{ .offset = GATE_IP_PERIC,		.value = 0xffffffff, },
 293	{ .offset = GATE_IP_PERIS,		.value = 0xffffffff, },
 294};
 295
 296/* list of all parent clocks */
 297PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 298				"mout_sclk_mpll", "mout_sclk_spll"};
 299PNAME(mout_cpu_p) = {"mout_apll", "mout_mspll_cpu"};
 300PNAME(mout_kfc_p) = {"mout_kpll", "mout_mspll_kfc"};
 301PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
 302PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
 303PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
 304PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
 305PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
 306PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
 307PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
 308PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
 309PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
 310PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
 311PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
 312
 313PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 314					"mout_sclk_mpll"};
 315PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
 316			"mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
 317			"mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
 318PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
 319PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
 320PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
 321
 322PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
 323PNAME(mout_sw_aclk66_p)	= {"dout_aclk66", "mout_sclk_spll"};
 324PNAME(mout_user_aclk66_peric_p)	= { "fin_pll", "mout_sw_aclk66"};
 325PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
 326
 327PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
 328PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
 329PNAME(mout_user_pclk200_fsys_p)	= {"fin_pll", "mout_sw_pclk200_fsys"};
 330PNAME(mout_user_aclk200_fsys_p)	= {"fin_pll", "mout_sw_aclk200_fsys"};
 331
 332PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
 333PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
 334PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
 335PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
 336
 337PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
 338PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
 339PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
 340
 341PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
 342PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
 343
 344PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
 345					"mout_sclk_spll"};
 346PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
 347
 348PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
 349PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
 350
 351PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
 352PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
 353
 354PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
 355PNAME(mout_user_aclk400_mscl_p)	= {"fin_pll", "mout_sw_aclk400_mscl"};
 356
 357PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
 358PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
 359
 360PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
 361PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
 362
 363PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
 364PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
 365PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
 366
 367PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
 368PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
 369
 370PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
 371PNAME(mout_user_aclk300_gscl_p)	= {"fin_pll", "mout_sw_aclk300_gscl"};
 372
 373PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
 374PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
 375PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
 376PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
 377
 378PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
 379PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
 380
 381PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
 382PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
 383
 384PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
 385PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
 386
 387PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
 388PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
 389
 390PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
 391			"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 392			"mout_sclk_epll", "mout_sclk_rpll"};
 393PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
 394			"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 395			"mout_sclk_epll", "mout_sclk_rpll"};
 396PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
 397			"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 398			"mout_sclk_epll", "mout_sclk_rpll"};
 399PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
 400			"dout_audio2", "spdif_extclk", "mout_sclk_ipll",
 401			"mout_sclk_epll", "mout_sclk_rpll"};
 402PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
 403PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
 404			 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 405			 "mout_sclk_epll", "mout_sclk_rpll"};
 406PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
 407				"mout_sclk_mpll", "mout_sclk_spll"};
 408PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
 409
 410/* List of parents specific to exynos5800 */
 411PNAME(mout_epll2_5800_p)	= { "mout_sclk_epll", "ff_dout_epll2" };
 412PNAME(mout_group1_5800_p)	= { "mout_sclk_cpll", "mout_sclk_dpll",
 413				"mout_sclk_mpll", "ff_dout_spll2" };
 414PNAME(mout_group2_5800_p)	= { "mout_sclk_cpll", "mout_sclk_dpll",
 415					"mout_sclk_mpll", "ff_dout_spll2",
 416					"mout_epll2", "mout_sclk_ipll" };
 417PNAME(mout_group3_5800_p)	= { "mout_sclk_cpll", "mout_sclk_dpll",
 418					"mout_sclk_mpll", "ff_dout_spll2",
 419					"mout_epll2" };
 420PNAME(mout_group5_5800_p)	= { "mout_sclk_cpll", "mout_sclk_dpll",
 421					"mout_sclk_mpll", "mout_sclk_spll" };
 422PNAME(mout_group6_5800_p)	= { "mout_sclk_ipll", "mout_sclk_dpll",
 423				"mout_sclk_mpll", "ff_dout_spll2" };
 424PNAME(mout_group7_5800_p)	= { "mout_sclk_cpll", "mout_sclk_dpll",
 425					"mout_sclk_mpll", "mout_sclk_spll",
 426					"mout_epll2", "mout_sclk_ipll" };
 427PNAME(mout_mx_mspll_ccore_p)	= {"sclk_bpll", "mout_sclk_dpll",
 428					"mout_sclk_mpll", "ff_dout_spll2",
 429					"mout_sclk_spll", "mout_sclk_epll"};
 430PNAME(mout_mau_epll_clk_5800_p)	= { "mout_sclk_epll", "mout_sclk_dpll",
 431					"mout_sclk_mpll",
 432					"ff_dout_spll2" };
 433PNAME(mout_group8_5800_p)	= { "dout_aclk432_scaler", "dout_sclk_sw" };
 434PNAME(mout_group9_5800_p)	= { "dout_osc_div", "mout_sw_aclk432_scaler" };
 435PNAME(mout_group10_5800_p)	= { "dout_aclk432_cam", "dout_sclk_sw" };
 436PNAME(mout_group11_5800_p)	= { "dout_osc_div", "mout_sw_aclk432_cam" };
 437PNAME(mout_group12_5800_p)	= { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
 438PNAME(mout_group13_5800_p)	= { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
 439PNAME(mout_group14_5800_p)	= { "dout_aclk550_cam", "dout_sclk_sw" };
 440PNAME(mout_group15_5800_p)	= { "dout_osc_div", "mout_sw_aclk550_cam" };
 441PNAME(mout_group16_5800_p)	= { "dout_osc_div", "mout_mau_epll_clk" };
 442PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
 443					"mout_sclk_mpll", "ff_dout_spll2",
 444					"mout_sclk_spll", "mout_sclk_epll"};
 445
 446/* fixed rate clocks generated outside the soc */
 447static struct samsung_fixed_rate_clock
 448		exynos5x_fixed_rate_ext_clks[] __initdata = {
 449	FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
 450};
 451
 452/* fixed rate clocks generated inside the soc */
 453static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
 454	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
 455	FRATE(0, "sclk_pwi", NULL, 0, 24000000),
 456	FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
 457	FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
 458	FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
 459};
 460
 461static const struct samsung_fixed_factor_clock
 462		exynos5x_fixed_factor_clks[] __initconst = {
 463	FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
 464	FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
 465};
 466
 467static const struct samsung_fixed_factor_clock
 468		exynos5800_fixed_factor_clks[] __initconst = {
 469	FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
 470	FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
 471};
 472
 473static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
 474	MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
 475	MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
 476	MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
 477	MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
 478
 479	MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
 480	MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
 481	MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
 482	MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
 483	MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
 484
 485	MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
 486	MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
 487	MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
 488	MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
 489	MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
 490	MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
 491
 492	MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
 493		mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
 494
 495	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 496			mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
 497	MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
 498			SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
 499	MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
 500	MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
 501
 502	MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
 503	MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
 504	MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
 505	MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
 506
 507	MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
 508			SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
 509	MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
 510							SRC_TOP9, 16, 1),
 511	MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
 512							SRC_TOP9, 20, 1),
 513	MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
 514							SRC_TOP9, 24, 1),
 515	MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
 516							SRC_TOP9, 28, 1),
 517
 518	MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
 519	MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
 520							SRC_TOP13, 20, 1),
 521	MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
 522							SRC_TOP13, 24, 1),
 523	MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
 524							SRC_TOP13, 28, 1),
 525
 526	MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
 527};
 528
 529static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
 530	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 531			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
 532	DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
 533				DIV_TOP8, 16, 3),
 534	DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
 535				DIV_TOP8, 20, 3),
 536	DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
 537				DIV_TOP8, 24, 3),
 538	DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
 539				DIV_TOP8, 28, 3),
 540
 541	DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
 542	DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
 543};
 544
 545static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
 546	GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
 547				GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
 548	GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
 549				GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
 550};
 551
 552static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 553	MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
 554	MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
 555				TOP_SPARE2, 4, 1),
 556
 557	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
 558	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
 559	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
 560	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
 561
 562	MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
 563	MUX(0, "mout_aclk333_432_isp", mout_group4_p,
 564				SRC_TOP1, 4, 2),
 565	MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
 566	MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
 567	MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
 568
 569	MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
 570	MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
 571	MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
 572	MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
 573	MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
 574	MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
 575
 576	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 577			mout_group5_5800_p, SRC_TOP7, 16, 2),
 578	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
 579	      CLK_SET_RATE_PARENT, 0),
 580
 581	MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
 582};
 583
 584static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
 585	DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
 586			"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
 587};
 588
 589static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
 590	GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
 591	/* Maudio Block */
 592	GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
 593			SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
 594	GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
 595		GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
 596	GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
 597		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
 598};
 599
 600static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 601	MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
 602			SRC_TOP7, 4, 1),
 603	MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p,
 604	    SRC_TOP7, 8, 2),
 605	MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p,
 606	    SRC_TOP7, 12, 2),
 607	MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
 608	      CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 609	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
 610	MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
 611	      CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
 612	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 613
 614	MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
 615	MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
 616	MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
 617	MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
 618
 619	MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
 620	MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
 621
 622	MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
 623	      CLK_SET_RATE_PARENT, 0),
 624
 625	MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
 626			SRC_TOP3, 0, 1),
 627	MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
 628			SRC_TOP3, 4, 1),
 629	MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
 630			mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
 631	MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
 632			SRC_TOP3, 12, 1),
 633	MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
 634			SRC_TOP3, 16, 1),
 635	MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
 636			SRC_TOP3, 20, 1),
 637	MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
 638			SRC_TOP3, 24, 1),
 639	MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
 640			SRC_TOP3, 28, 1),
 641
 642	MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
 643			SRC_TOP4, 0, 1),
 644	MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
 645			SRC_TOP4, 4, 1),
 646	MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
 647			SRC_TOP4, 8, 1),
 648	MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
 649			SRC_TOP4, 12, 1),
 650	MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
 651			SRC_TOP4, 16, 1),
 652	MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
 653	MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
 654	MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
 655			SRC_TOP4, 28, 1),
 656
 657	MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
 658			mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
 659	MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
 660			SRC_TOP5, 4, 1),
 661	MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
 662			SRC_TOP5, 8, 1),
 663	MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
 664			SRC_TOP5, 12, 1),
 665	MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
 666			SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
 667	MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
 668			SRC_TOP5, 20, 1),
 669	MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
 670			mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
 671	MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
 672			mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
 673
 674	MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
 675	MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
 676	      CLK_SET_RATE_PARENT, 0),
 677	MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
 678	MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
 679	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 680	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
 681			CLK_SET_RATE_PARENT, 0),
 682	MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
 683	MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 684
 685	MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
 686			SRC_TOP10, 0, 1),
 687	MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
 688			SRC_TOP10, 4, 1),
 689	MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
 690			SRC_TOP10, 8, 1),
 691	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
 692			SRC_TOP10, 12, 1),
 693	MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
 694			SRC_TOP10, 16, 1),
 695	MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
 696			SRC_TOP10, 20, 1),
 697	MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
 698			SRC_TOP10, 24, 1),
 699	MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
 700			SRC_TOP10, 28, 1),
 701
 702	MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
 703			SRC_TOP11, 0, 1),
 704	MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
 705			SRC_TOP11, 4, 1),
 706	MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
 707	MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
 708			SRC_TOP11, 12, 1),
 709	MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
 710	MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
 711	MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
 712			SRC_TOP11, 28, 1),
 713
 714	MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
 715			mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
 716	MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
 717			SRC_TOP12, 8, 1),
 718	MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
 719			SRC_TOP12, 12, 1),
 720	MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
 721			SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
 722	MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
 723			SRC_TOP12, 20, 1),
 724	MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
 725			mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
 726	MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
 727			mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
 728
 729	/* DISP1 Block */
 730	MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
 731	MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
 732	MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
 733	MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
 734	MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
 735
 736	MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
 737
 738	/* CDREX block */
 739	MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
 740			SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
 741	MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
 742			CLK_SET_RATE_PARENT, 0),
 743
 744	/* MAU Block */
 745	MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
 746
 747	/* FSYS Block */
 748	MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
 749	MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
 750	MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
 751	MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
 752	MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
 753	MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
 754	MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
 755
 756	/* PERIC Block */
 757	MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
 758	MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
 759	MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
 760	MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
 761	MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 762	MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 763	MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
 764	MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
 765	MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
 766	MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
 767	MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
 768	MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
 769
 770	/* ISP Block */
 771	MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
 772	MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
 773	MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
 774	MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
 775	MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
 776};
 777
 778static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
 779	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
 780	DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
 781	DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
 782	DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
 783	DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
 784
 785	DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
 786			DIV_TOP0, 0, 3),
 787	DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
 788			DIV_TOP0, 4, 3),
 789	DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
 790			DIV_TOP0, 8, 3),
 791	DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
 792			DIV_TOP0, 12, 3),
 793	DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
 794			DIV_TOP0, 20, 3),
 795	DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
 796			DIV_TOP0, 24, 3),
 797	DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
 798			DIV_TOP0, 28, 3),
 799	DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
 800			"mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
 801	DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
 802			"mout_aclk333_432_isp", DIV_TOP1, 4, 3),
 803	DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
 804			DIV_TOP1, 8, 6),
 805	DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
 806			"mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
 807	DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
 808			DIV_TOP1, 20, 3),
 809	DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
 810			DIV_TOP1, 24, 3),
 811	DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
 812			DIV_TOP1, 28, 3),
 813
 814	DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
 815			DIV_TOP2, 8, 3),
 816	DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
 817			DIV_TOP2, 12, 3),
 818	DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
 819			16, 3, CLK_SET_RATE_PARENT, 0),
 820	DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
 821			DIV_TOP2, 20, 3),
 822	DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
 823			"mout_aclk300_disp1", DIV_TOP2, 24, 3),
 824	DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
 825			DIV_TOP2, 28, 3),
 826
 827	/* DISP1 Block */
 828	DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
 829	DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 830	DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
 831	DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
 832	DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
 833			"mout_aclk400_disp1", DIV_TOP2, 4, 3),
 834
 835	/* CDREX Block */
 836	/*
 837	 * The three clocks below are controlled using the same register and
 838	 * bits. They are put into one because there is a need of
 839	 * synchronization between the BUS and DREXs (two external memory
 840	 * interfaces).
 841	 * They are put here to show this HW assumption and for clock
 842	 * information summary completeness.
 843	 */
 844	DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
 845			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
 846	DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
 847			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
 848	DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
 849			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
 850
 851	DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
 852			DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
 853	DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
 854			DIV_CDREX0, 16, 3),
 855	DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
 856			DIV_CDREX0, 8, 3),
 857	DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
 858			DIV_CDREX0, 3, 5),
 859
 860	DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
 861			DIV_CDREX1, 8, 3),
 862
 863	/* Audio Block */
 864	DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
 865	DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 866
 867	/* USB3.0 */
 868	DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
 869	DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
 870	DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
 871	DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
 872
 873	/* MMC */
 874	DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
 875	DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
 876	DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
 877
 878	DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
 879	DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
 880
 881	/* UART and PWM */
 882	DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
 883	DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
 884	DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
 885	DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
 886	DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
 887
 888	/* SPI */
 889	DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
 890	DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
 891	DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
 892
 893
 894	/* PCM */
 895	DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
 896	DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
 897
 898	/* Audio - I2S */
 899	DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
 900	DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
 901	DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
 902	DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
 903	DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
 904
 905	/* SPI Pre-Ratio */
 906	DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
 907	DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
 908	DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
 909
 910	/* GSCL Block */
 911	DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
 912
 913	/* PSGEN */
 914	DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
 915	DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
 916
 917	/* ISP Block */
 918	DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
 919	DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
 920	DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
 921	DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
 922	DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
 923	DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
 924	DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
 925	DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
 926			CLK_SET_RATE_PARENT, 0),
 927	DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
 928			CLK_SET_RATE_PARENT, 0),
 929};
 930
 931static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 932	/* G2D */
 933	GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
 934	GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
 935	GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
 936	GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
 937	GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
 938
 939	GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
 940			GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
 941	GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
 942			GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
 943
 944	GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
 945			GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
 946	GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
 947			GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
 948	GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
 949			GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
 950	GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
 951			GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
 952	GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
 953			GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
 954	GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
 955			GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
 956	GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
 957			GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
 958	GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
 959			GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
 960	GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
 961			GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
 962	GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
 963			GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
 964	GATE(0, "aclk166", "mout_user_aclk166",
 965			GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
 966	GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
 967			GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
 968	GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
 969			GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
 970	GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
 971			GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
 972	GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
 973			GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
 974	GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
 975			GATE_BUS_TOP, 28, 0, 0),
 976	GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
 977			GATE_BUS_TOP, 29, 0, 0),
 978
 979	GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
 980			SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
 981
 982	/* sclk */
 983	GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
 984		GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 985	GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
 986		GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 987	GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
 988		GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 989	GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
 990		GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
 991	GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
 992		GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
 993	GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
 994		GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 995	GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
 996		GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 997	GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
 998		GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 999	GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
1000		GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1001	GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
1002		GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
1003	GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
1004		GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
1005	GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
1006		GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
1007	GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
1008		GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
1009
1010	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
1011		GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
1012	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
1013		GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
1014	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
1015		GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1016	GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
1017		GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
1018	GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
1019		GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
1020	GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
1021		GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
1022	GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
1023		GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1024
1025	/* Display */
1026	GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
1027			GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
1028	GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
1029			GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1030	GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
1031			GATE_TOP_SCLK_DISP1, 9, 0, 0),
1032	GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
1033			GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1034	GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1035			GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1036
1037	/* FSYS Block */
1038	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1039	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1040	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1041	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1042	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1043	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1044	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1045	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1046	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1047			GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1048	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1049	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1050	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1051	GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1052			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1053
1054	/* PERIC Block */
1055	GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1056			GATE_IP_PERIC, 0, 0, 0),
1057	GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1058			GATE_IP_PERIC, 1, 0, 0),
1059	GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1060			GATE_IP_PERIC, 2, 0, 0),
1061	GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1062			GATE_IP_PERIC, 3, 0, 0),
1063	GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1064			GATE_IP_PERIC, 6, 0, 0),
1065	GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1066			GATE_IP_PERIC, 7, 0, 0),
1067	GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1068			GATE_IP_PERIC, 8, 0, 0),
1069	GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1070			GATE_IP_PERIC, 9, 0, 0),
1071	GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1072			GATE_IP_PERIC, 10, 0, 0),
1073	GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1074			GATE_IP_PERIC, 11, 0, 0),
1075	GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1076			GATE_IP_PERIC, 12, 0, 0),
1077	GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1078			GATE_IP_PERIC, 13, 0, 0),
1079	GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1080			GATE_IP_PERIC, 14, 0, 0),
1081	GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1082			GATE_IP_PERIC, 15, 0, 0),
1083	GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1084			GATE_IP_PERIC, 16, 0, 0),
1085	GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1086			GATE_IP_PERIC, 17, 0, 0),
1087	GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1088			GATE_IP_PERIC, 18, 0, 0),
1089	GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1090			GATE_IP_PERIC, 20, 0, 0),
1091	GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1092			GATE_IP_PERIC, 21, 0, 0),
1093	GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1094			GATE_IP_PERIC, 22, 0, 0),
1095	GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1096			GATE_IP_PERIC, 23, 0, 0),
1097	GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1098			GATE_IP_PERIC, 24, 0, 0),
1099	GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1100			GATE_IP_PERIC, 26, 0, 0),
1101	GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1102			GATE_IP_PERIC, 28, 0, 0),
1103	GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1104			GATE_IP_PERIC, 30, 0, 0),
1105	GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1106			GATE_IP_PERIC, 31, 0, 0),
1107
1108	GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1109			GATE_BUS_PERIC, 22, 0, 0),
1110
1111	/* PERIS Block */
1112	GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1113			GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1114	GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1115			GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1116	GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1117	GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1118	GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1119	GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1120	GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1121	GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1122	GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1123	GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1124	GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1125	GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1126	GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1127	GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1128	GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1129	GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1130	GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1131	GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1132
1133	/* GEN Block */
1134	GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1135	GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1136	GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1137	GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1138	GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1139	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1140			GATE_IP_GEN, 6, 0, 0),
1141	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1142	GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1143			GATE_IP_GEN, 9, 0, 0),
1144
1145	/* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1146	GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1147			GATE_BUS_GEN, 28, 0, 0),
1148	GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1149
1150	/* GSCL Block */
1151	GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1152			GATE_TOP_SCLK_GSCL, 6, 0, 0),
1153	GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1154			GATE_TOP_SCLK_GSCL, 7, 0, 0),
1155
1156	GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1157			GATE_IP_GSCL0, 4, 0, 0),
1158	GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1159			GATE_IP_GSCL0, 5, 0, 0),
1160	GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1161			GATE_IP_GSCL0, 6, 0, 0),
1162
1163	GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1164			GATE_IP_GSCL1, 2, 0, 0),
1165	GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1166			GATE_IP_GSCL1, 3, 0, 0),
1167	GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1168			GATE_IP_GSCL1, 4, 0, 0),
1169	GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12,
1170			CLK_IS_CRITICAL, 0),
1171	GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
1172			CLK_IS_CRITICAL, 0),
1173	GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333",
1174			GATE_IP_GSCL1, 16, 0, 0),
1175	GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1176			GATE_IP_GSCL1, 17, 0, 0),
1177
1178	/* ISP */
1179	GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1180			GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1181	GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1182			GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1183	GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1184			GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1185	GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1186			GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1187	GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1188			GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1189	GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1190			GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1191	GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1192			GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1193
1194	/* CDREX */
1195	GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
1196			GATE_BUS_CDREX0, 0, 0, 0),
1197	GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
1198			GATE_BUS_CDREX0, 1, 0, 0),
1199	GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
1200			SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
1201
1202	GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
1203			GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
1204	GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
1205			GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
1206	GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
1207			GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
1208	GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
1209			GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
1210
1211	GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
1212			GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
1213	GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
1214			GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
1215	GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
1216			GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
1217	GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
1218			GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
1219};
1220
1221static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
1222	DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
1223};
1224
1225static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
1226	GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1227	GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1228	GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1229	GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1230	GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1231	GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1232			GATE_IP_DISP1, 7, 0, 0),
1233	GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1234			GATE_IP_DISP1, 8, 0, 0),
1235	GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1236			GATE_IP_DISP1, 9, 0, 0),
1237};
1238
1239static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
1240	{ GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
1241	{ SRC_TOP5, 0, BIT(0) },	/* MUX mout_user_aclk400_disp1 */
1242	{ SRC_TOP5, 0, BIT(24) },	/* MUX mout_user_aclk300_disp1 */
1243	{ SRC_TOP3, 0, BIT(8) },	/* MUX mout_user_aclk200_disp1 */
1244	{ DIV2_RATIO0, 0, 0x30000 },		/* DIV dout_disp1_blk */
1245};
1246
1247static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
1248	DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
1249			DIV2_RATIO0, 4, 2),
1250};
1251
1252static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
1253	GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1254	GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1255	GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1256			GATE_IP_GSCL1, 6, 0, 0),
1257	GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1258			GATE_IP_GSCL1, 7, 0, 0),
1259};
1260
1261static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
1262	{ GATE_IP_GSCL0, 0x3, 0x3 },	/* GSC gates */
1263	{ GATE_IP_GSCL1, 0xc0, 0xc0 },	/* GSC gates */
1264	{ SRC_TOP5, 0, BIT(28) },	/* MUX mout_user_aclk300_gscl */
1265	{ DIV2_RATIO0, 0, 0x30 },	/* DIV dout_gscl_blk_300 */
1266};
1267
1268static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
1269	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
1270	     CLK_SET_RATE_PARENT, 0),
1271};
1272
1273static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
1274	{ GATE_IP_G3D, 0x3ff, 0x3ff },	/* G3D gates */
1275	{ SRC_TOP5, 0, BIT(16) },	/* MUX mout_user_aclk_g3d */
1276};
1277
1278static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
1279	DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1280};
1281
1282static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
1283	GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1284	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1285	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1286};
1287
1288static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
1289	{ GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
1290	{ SRC_TOP4, 0, BIT(28) },		/* MUX mout_user_aclk333 */
1291	{ DIV4_RATIO, 0, 0x3 },			/* DIV dout_mfc_blk */
1292};
1293
1294static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {
1295	/* MSCL Block */
1296	GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1297	GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1298	GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1299	GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1300			GATE_IP_MSCL, 8, 0, 0),
1301	GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1302			GATE_IP_MSCL, 9, 0, 0),
1303	GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1304			GATE_IP_MSCL, 10, 0, 0),
1305};
1306
1307static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {
1308	DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
1309};
1310
1311static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {
1312	{ GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
1313	{ SRC_TOP3, 0, BIT(4) },		/* MUX mout_user_aclk400_mscl */
1314	{ DIV2_RATIO0, 0, 0x30000000 },		/* DIV dout_mscl_blk */
1315};
1316
1317static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {
1318	GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
1319			SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
1320	GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1321		GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1322	GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1323		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1324};
1325
1326static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {
1327	{ SRC_TOP9, 0, BIT(8) },	/* MUX mout_user_mau_epll */
1328};
1329
1330static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {
1331	.div_clks	= exynos5x_disp_div_clks,
1332	.nr_div_clks	= ARRAY_SIZE(exynos5x_disp_div_clks),
1333	.gate_clks	= exynos5x_disp_gate_clks,
1334	.nr_gate_clks	= ARRAY_SIZE(exynos5x_disp_gate_clks),
1335	.suspend_regs	= exynos5x_disp_suspend_regs,
1336	.nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
1337	.pd_name	= "DISP",
1338};
1339
1340static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
1341	.div_clks	= exynos5x_gsc_div_clks,
1342	.nr_div_clks	= ARRAY_SIZE(exynos5x_gsc_div_clks),
1343	.gate_clks	= exynos5x_gsc_gate_clks,
1344	.nr_gate_clks	= ARRAY_SIZE(exynos5x_gsc_gate_clks),
1345	.suspend_regs	= exynos5x_gsc_suspend_regs,
1346	.nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
1347	.pd_name	= "GSC",
1348};
1349
1350static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
1351	.gate_clks	= exynos5x_g3d_gate_clks,
1352	.nr_gate_clks	= ARRAY_SIZE(exynos5x_g3d_gate_clks),
1353	.suspend_regs	= exynos5x_g3d_suspend_regs,
1354	.nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
1355	.pd_name	= "G3D",
1356};
1357
1358static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
1359	.div_clks	= exynos5x_mfc_div_clks,
1360	.nr_div_clks	= ARRAY_SIZE(exynos5x_mfc_div_clks),
1361	.gate_clks	= exynos5x_mfc_gate_clks,
1362	.nr_gate_clks	= ARRAY_SIZE(exynos5x_mfc_gate_clks),
1363	.suspend_regs	= exynos5x_mfc_suspend_regs,
1364	.nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
1365	.pd_name	= "MFC",
1366};
1367
1368static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {
1369	.div_clks	= exynos5x_mscl_div_clks,
1370	.nr_div_clks	= ARRAY_SIZE(exynos5x_mscl_div_clks),
1371	.gate_clks	= exynos5x_mscl_gate_clks,
1372	.nr_gate_clks	= ARRAY_SIZE(exynos5x_mscl_gate_clks),
1373	.suspend_regs	= exynos5x_mscl_suspend_regs,
1374	.nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs),
1375	.pd_name	= "MSC",
1376};
1377
1378static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
1379	.gate_clks	= exynos5800_mau_gate_clks,
1380	.nr_gate_clks	= ARRAY_SIZE(exynos5800_mau_gate_clks),
1381	.suspend_regs	= exynos5800_mau_suspend_regs,
1382	.nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs),
1383	.pd_name	= "MAU",
1384};
1385
1386static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
1387	&exynos5x_disp_subcmu,
1388	&exynos5x_gsc_subcmu,
1389	&exynos5x_g3d_subcmu,
1390	&exynos5x_mfc_subcmu,
1391	&exynos5x_mscl_subcmu,
1392};
1393
1394static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
1395	&exynos5x_disp_subcmu,
1396	&exynos5x_gsc_subcmu,
1397	&exynos5x_g3d_subcmu,
1398	&exynos5x_mfc_subcmu,
1399	&exynos5x_mscl_subcmu,
1400	&exynos5800_mau_subcmu,
1401};
1402
1403static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1404	PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1405	PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1406	PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1407	PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1408	PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1409	PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1410	PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1411	PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1412	PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1413	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
1414	PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
1415	PLL_35XX_RATE(24 * MHZ, 900000000,  150, 2, 1),
1416	PLL_35XX_RATE(24 * MHZ, 800000000,  200, 3, 1),
1417	PLL_35XX_RATE(24 * MHZ, 700000000,  175, 3, 1),
1418	PLL_35XX_RATE(24 * MHZ, 600000000,  200, 2, 2),
1419	PLL_35XX_RATE(24 * MHZ, 500000000,  250, 3, 2),
1420	PLL_35XX_RATE(24 * MHZ, 400000000,  200, 3, 2),
1421	PLL_35XX_RATE(24 * MHZ, 300000000,  200, 2, 3),
1422	PLL_35XX_RATE(24 * MHZ, 200000000,  200, 3, 3),
1423};
1424
1425static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
1426	PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
1427	PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
1428	PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
1429	PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
1430	PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
1431	PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
1432	PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
1433	PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
1434};
1435
1436static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
1437	PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1438	PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1439	PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1440	PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
1441	PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1442	PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1443	PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
1444	PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
1445	PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
1446	PLL_36XX_RATE(24 * MHZ,  73728000U, 98, 2, 4, 19923),
1447	PLL_36XX_RATE(24 * MHZ,  67737602U, 90, 2, 4, 20762),
1448	PLL_36XX_RATE(24 * MHZ,  65536003U, 131, 3, 4, 4719),
1449	PLL_36XX_RATE(24 * MHZ,  49152000U, 197, 3, 5, -25690),
1450	PLL_36XX_RATE(24 * MHZ,  45158401U, 90, 3, 4, 20762),
1451	PLL_36XX_RATE(24 * MHZ,  32768001U, 131, 3, 5, 4719),
1452};
1453
1454static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {
1455	PLL_35XX_RATE(24 * MHZ, 600000000U,  200, 2, 2),
1456	PLL_35XX_RATE(24 * MHZ, 543000000U,  181, 2, 2),
1457	PLL_35XX_RATE(24 * MHZ, 480000000U,  160, 2, 2),
1458	PLL_35XX_RATE(24 * MHZ, 420000000U,  140, 2, 2),
1459	PLL_35XX_RATE(24 * MHZ, 350000000U,  175, 3, 2),
1460	PLL_35XX_RATE(24 * MHZ, 266000000U,  266, 3, 3),
1461	PLL_35XX_RATE(24 * MHZ, 177000000U,  118, 2, 3),
1462	PLL_35XX_RATE(24 * MHZ, 100000000U,  200, 3, 4),
1463};
1464
1465static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1466	[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1467		APLL_CON0, NULL),
1468	[cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1469		CPLL_CON0, NULL),
1470	[dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1471		DPLL_CON0, NULL),
1472	[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1473		EPLL_CON0, NULL),
1474	[rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1475		RPLL_CON0, NULL),
1476	[ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1477		IPLL_CON0, NULL),
1478	[spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1479		SPLL_CON0, NULL),
1480	[vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1481		VPLL_CON0, NULL),
1482	[mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1483		MPLL_CON0, NULL),
1484	[bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1485		BPLL_CON0, NULL),
1486	[kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1487		KPLL_CON0, NULL),
1488};
1489
1490#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud)			\
1491		((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |	\
1492		 ((cpud) << 4)))
1493
1494static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
1495	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1496	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1497	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1498	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1499	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1500	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1501	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1502	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1503	{ 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
1504	{  900000, E5420_EGL_DIV0(3, 6, 6, 2), },
1505	{  800000, E5420_EGL_DIV0(3, 5, 5, 2), },
1506	{  700000, E5420_EGL_DIV0(3, 5, 5, 2), },
1507	{  600000, E5420_EGL_DIV0(3, 4, 4, 2), },
1508	{  500000, E5420_EGL_DIV0(3, 3, 3, 2), },
1509	{  400000, E5420_EGL_DIV0(3, 3, 3, 2), },
1510	{  300000, E5420_EGL_DIV0(3, 3, 3, 2), },
1511	{  200000, E5420_EGL_DIV0(3, 3, 3, 2), },
1512	{  0 },
1513};
1514
1515static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
1516	{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
1517	{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
1518	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1519	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1520	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1521	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1522	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1523	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1524	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1525	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1526	{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
1527	{  900000, E5420_EGL_DIV0(3, 7, 6, 2), },
1528	{  800000, E5420_EGL_DIV0(3, 7, 5, 2), },
1529	{  700000, E5420_EGL_DIV0(3, 7, 5, 2), },
1530	{  600000, E5420_EGL_DIV0(3, 7, 4, 2), },
1531	{  500000, E5420_EGL_DIV0(3, 7, 3, 2), },
1532	{  400000, E5420_EGL_DIV0(3, 7, 3, 2), },
1533	{  300000, E5420_EGL_DIV0(3, 7, 3, 2), },
1534	{  200000, E5420_EGL_DIV0(3, 7, 3, 2), },
1535	{  0 },
1536};
1537
1538#define E5420_KFC_DIV(kpll, pclk, aclk)					\
1539		((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
1540
1541static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
1542	{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
1543	{ 1300000, E5420_KFC_DIV(3, 5, 2), },
1544	{ 1200000, E5420_KFC_DIV(3, 5, 2), },
1545	{ 1100000, E5420_KFC_DIV(3, 5, 2), },
1546	{ 1000000, E5420_KFC_DIV(3, 5, 2), },
1547	{  900000, E5420_KFC_DIV(3, 5, 2), },
1548	{  800000, E5420_KFC_DIV(3, 5, 2), },
1549	{  700000, E5420_KFC_DIV(3, 4, 2), },
1550	{  600000, E5420_KFC_DIV(3, 4, 2), },
1551	{  500000, E5420_KFC_DIV(3, 4, 2), },
1552	{  400000, E5420_KFC_DIV(3, 3, 2), },
1553	{  300000, E5420_KFC_DIV(3, 3, 2), },
1554	{  200000, E5420_KFC_DIV(3, 3, 2), },
1555	{  0 },
1556};
1557
1558static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {
1559	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
1560		0x0, CPUCLK_LAYOUT_E4210, exynos5420_eglclk_d),
1561	CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
1562		0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
1563};
1564
1565static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {
1566	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
1567		0x0, CPUCLK_LAYOUT_E4210, exynos5800_eglclk_d),
1568	CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
1569		0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
1570};
1571
1572static const struct of_device_id ext_clk_match[] __initconst = {
1573	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1574	{ },
1575};
1576
1577/* register exynos5420 clocks */
1578static void __init exynos5x_clk_init(struct device_node *np,
1579		enum exynos5x_soc soc)
1580{
1581	struct samsung_clk_provider *ctx;
1582	struct clk_hw **hws;
1583
1584	if (np) {
1585		reg_base = of_iomap(np, 0);
1586		if (!reg_base)
1587			panic("%s: failed to map registers\n", __func__);
1588	} else {
1589		panic("%s: unable to determine soc\n", __func__);
1590	}
1591
1592	exynos5x_soc = soc;
1593
1594	ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
1595	hws = ctx->clk_data.hws;
1596
1597	samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1598			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1599			ext_clk_match);
1600
1601	if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
1602		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1603		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
1604		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1605		exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
1606	}
1607
1608	if (soc == EXYNOS5420)
1609		exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1610	else
1611		exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
1612
1613	samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls));
1614	samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1615			ARRAY_SIZE(exynos5x_fixed_rate_clks));
1616	samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1617			ARRAY_SIZE(exynos5x_fixed_factor_clks));
1618	samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1619			ARRAY_SIZE(exynos5x_mux_clks));
1620	samsung_clk_register_div(ctx, exynos5x_div_clks,
1621			ARRAY_SIZE(exynos5x_div_clks));
1622	samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1623			ARRAY_SIZE(exynos5x_gate_clks));
1624
1625	if (soc == EXYNOS5420) {
1626		samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1627				ARRAY_SIZE(exynos5420_mux_clks));
1628		samsung_clk_register_div(ctx, exynos5420_div_clks,
1629				ARRAY_SIZE(exynos5420_div_clks));
1630		samsung_clk_register_gate(ctx, exynos5420_gate_clks,
1631				ARRAY_SIZE(exynos5420_gate_clks));
1632	} else {
1633		samsung_clk_register_fixed_factor(
1634				ctx, exynos5800_fixed_factor_clks,
1635				ARRAY_SIZE(exynos5800_fixed_factor_clks));
1636		samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1637				ARRAY_SIZE(exynos5800_mux_clks));
1638		samsung_clk_register_div(ctx, exynos5800_div_clks,
1639				ARRAY_SIZE(exynos5800_div_clks));
1640		samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1641				ARRAY_SIZE(exynos5800_gate_clks));
1642	}
1643
1644	if (soc == EXYNOS5420) {
1645		samsung_clk_register_cpu(ctx, exynos5420_cpu_clks,
1646				ARRAY_SIZE(exynos5420_cpu_clks));
1647	} else {
1648		samsung_clk_register_cpu(ctx, exynos5800_cpu_clks,
1649				ARRAY_SIZE(exynos5800_cpu_clks));
1650	}
1651
1652	samsung_clk_extended_sleep_init(reg_base,
1653		exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
1654		exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
1655
1656	if (soc == EXYNOS5800) {
1657		samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
1658				       ARRAY_SIZE(exynos5800_clk_regs));
1659
1660		exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus),
1661				     exynos5800_subcmus);
1662	} else {
1663		exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1664				     exynos5x_subcmus);
1665	}
1666
1667	/*
1668	 * Keep top part of G3D clock path enabled permanently to ensure
1669	 * that the internal busses get their clock regardless of the
1670	 * main G3D clock enablement status.
1671	 */
1672	clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
1673	/*
1674	 * Keep top BPLL mux enabled permanently to ensure that DRAM operates
1675	 * properly.
1676	 */
1677	clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
1678
1679	samsung_clk_of_add_provider(np, ctx);
1680}
1681
1682static void __init exynos5420_clk_init(struct device_node *np)
1683{
1684	exynos5x_clk_init(np, EXYNOS5420);
1685}
1686CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
1687		      exynos5420_clk_init);
1688
1689static void __init exynos5800_clk_init(struct device_node *np)
1690{
1691	exynos5x_clk_init(np, EXYNOS5800);
1692}
1693CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
1694		      exynos5800_clk_init);