clk-exynos-audss.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4 * Author: Padmavathi Venna <padma.v@samsung.com>
  5 *
  6 * Common Clock Framework support for Audio Subsystem Clock Controller.
  7 */
  8
  9#include <linux/slab.h>
 10#include <linux/io.h>
 11#include <linux/clk.h>
 12#include <linux/clk-provider.h>
 13#include <linux/of.h>
 14#include <linux/mod_devicetable.h>
 15#include <linux/module.h>
 16#include <linux/platform_device.h>
 17#include <linux/pm_runtime.h>
 18
 19#include <dt-bindings/clock/exynos-audss-clk.h>
 20
 21static DEFINE_SPINLOCK(lock);
 22static void __iomem *reg_base;
 23static struct clk_hw_onecell_data *clk_data;
 24/*
 25 * On Exynos5420 this will be a clock which has to be enabled before any
 26 * access to audss registers. Typically a child of EPLL.
 27 *
 28 * On other platforms this will be -ENODEV.
 29 */
 30static struct clk *epll;
 31
 32#define ASS_CLK_SRC 0x0
 33#define ASS_CLK_DIV 0x4
 34#define ASS_CLK_GATE 0x8
 35
 36static unsigned long reg_save[][2] = {
 37	{ ASS_CLK_SRC,  0 },
 38	{ ASS_CLK_DIV,  0 },
 39	{ ASS_CLK_GATE, 0 },
 40};
 41
 42static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
 43{
 44	int i;
 45
 46	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
 47		reg_save[i][1] = readl(reg_base + reg_save[i][0]);
 48
 49	return 0;
 50}
 51
 52static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
 53{
 54	int i;
 55
 56	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
 57		writel(reg_save[i][1], reg_base + reg_save[i][0]);
 58
 59	return 0;
 60}
 61
 62struct exynos_audss_clk_drvdata {
 63	unsigned int has_adma_clk:1;
 64	unsigned int has_mst_clk:1;
 65	unsigned int enable_epll:1;
 66	unsigned int num_clks;
 67};
 68
 69static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
 70	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
 71	.enable_epll	= 1,
 72};
 73
 74static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
 75	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
 76	.has_mst_clk	= 1,
 77};
 78
 79static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
 80	.num_clks	= EXYNOS_AUDSS_MAX_CLKS,
 81	.has_adma_clk	= 1,
 82	.enable_epll	= 1,
 83};
 84
 85static const struct of_device_id exynos_audss_clk_of_match[] = {
 86	{
 87		.compatible	= "samsung,exynos4210-audss-clock",
 88		.data		= &exynos4210_drvdata,
 89	}, {
 90		.compatible	= "samsung,exynos5250-audss-clock",
 91		.data		= &exynos4210_drvdata,
 92	}, {
 93		.compatible	= "samsung,exynos5410-audss-clock",
 94		.data		= &exynos5410_drvdata,
 95	}, {
 96		.compatible	= "samsung,exynos5420-audss-clock",
 97		.data		= &exynos5420_drvdata,
 98	},
 99	{ },
100};
101MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
102
103static void exynos_audss_clk_teardown(void)
104{
105	int i;
106
107	for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
108		if (!IS_ERR(clk_data->hws[i]))
109			clk_hw_unregister_mux(clk_data->hws[i]);
110	}
111
112	for (; i < EXYNOS_SRP_CLK; i++) {
113		if (!IS_ERR(clk_data->hws[i]))
114			clk_hw_unregister_divider(clk_data->hws[i]);
115	}
116
117	for (; i < clk_data->num; i++) {
118		if (!IS_ERR(clk_data->hws[i]))
119			clk_hw_unregister_gate(clk_data->hws[i]);
120	}
121}
122
123/* register exynos_audss clocks */
124static int exynos_audss_clk_probe(struct platform_device *pdev)
125{
126	const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
127	const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
128	const char *sclk_pcm_p = "sclk_pcm0";
129	struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
130	const struct exynos_audss_clk_drvdata *variant;
131	struct clk_hw **clk_table;
132	struct device *dev = &pdev->dev;
133	int i, ret = 0;
134
135	variant = of_device_get_match_data(&pdev->dev);
136	if (!variant)
137		return -EINVAL;
138
139	reg_base = devm_platform_ioremap_resource(pdev, 0);
140	if (IS_ERR(reg_base))
141		return PTR_ERR(reg_base);
142
143	epll = ERR_PTR(-ENODEV);
144
145	clk_data = devm_kzalloc(dev,
146				struct_size(clk_data, hws,
147					    EXYNOS_AUDSS_MAX_CLKS),
148				GFP_KERNEL);
149	if (!clk_data)
150		return -ENOMEM;
151
152	clk_data->num = variant->num_clks;
153	clk_table = clk_data->hws;
154
155	pll_ref = devm_clk_get(dev, "pll_ref");
156	pll_in = devm_clk_get(dev, "pll_in");
157	if (!IS_ERR(pll_ref))
158		mout_audss_p[0] = __clk_get_name(pll_ref);
159	if (!IS_ERR(pll_in)) {
160		mout_audss_p[1] = __clk_get_name(pll_in);
161
162		if (variant->enable_epll) {
163			epll = pll_in;
164
165			ret = clk_prepare_enable(epll);
166			if (ret) {
167				dev_err(dev,
168					"failed to prepare the epll clock\n");
169				return ret;
170			}
171		}
172	}
173
174	/*
175	 * Enable runtime PM here to allow the clock core using runtime PM
176	 * for the registered clocks. Additionally, we increase the runtime
177	 * PM usage count before registering the clocks, to prevent the
178	 * clock core from runtime suspending the device.
179	 */
180	pm_runtime_get_noresume(dev);
181	pm_runtime_set_active(dev);
182	pm_runtime_enable(dev);
183
184	clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
185				mout_audss_p, ARRAY_SIZE(mout_audss_p),
186				CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
187				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
188
189	cdclk = devm_clk_get(dev, "cdclk");
190	sclk_audio = devm_clk_get(dev, "sclk_audio");
191	if (!IS_ERR(cdclk))
192		mout_i2s_p[1] = __clk_get_name(cdclk);
193	if (!IS_ERR(sclk_audio))
194		mout_i2s_p[2] = __clk_get_name(sclk_audio);
195	clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
196				mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
197				CLK_SET_RATE_NO_REPARENT,
198				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
199
200	clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
201				"mout_audss", CLK_SET_RATE_PARENT,
202				reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
203
204	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
205				"dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
206				reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
207
208	clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
209				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
210				&lock);
211
212	clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
213				"dout_srp", CLK_SET_RATE_PARENT,
214				reg_base + ASS_CLK_GATE, 0, 0, &lock);
215
216	clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
217				"dout_aud_bus", CLK_SET_RATE_PARENT,
218				reg_base + ASS_CLK_GATE, 2, 0, &lock);
219
220	clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
221				"dout_i2s", CLK_SET_RATE_PARENT,
222				reg_base + ASS_CLK_GATE, 3, 0, &lock);
223
224	clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
225				 "sclk_pcm", CLK_SET_RATE_PARENT,
226				reg_base + ASS_CLK_GATE, 4, 0, &lock);
227
228	sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
229	if (!IS_ERR(sclk_pcm_in))
230		sclk_pcm_p = __clk_get_name(sclk_pcm_in);
231	clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
232				sclk_pcm_p, CLK_SET_RATE_PARENT,
233				reg_base + ASS_CLK_GATE, 5, 0, &lock);
234
235	if (variant->has_adma_clk) {
236		clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
237				"dout_srp", CLK_SET_RATE_PARENT,
238				reg_base + ASS_CLK_GATE, 9, 0, &lock);
239	}
240
241	for (i = 0; i < clk_data->num; i++) {
242		if (IS_ERR(clk_table[i])) {
243			dev_err(dev, "failed to register clock %d\n", i);
244			ret = PTR_ERR(clk_table[i]);
245			goto unregister;
246		}
247	}
248
249	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
250				     clk_data);
251	if (ret) {
252		dev_err(dev, "failed to add clock provider\n");
253		goto unregister;
254	}
255
256	pm_runtime_put_sync(dev);
257
258	return 0;
259
260unregister:
261	exynos_audss_clk_teardown();
262	pm_runtime_put_sync(dev);
263	pm_runtime_disable(dev);
264
265	if (!IS_ERR(epll))
266		clk_disable_unprepare(epll);
267
268	return ret;
269}
270
271static void exynos_audss_clk_remove(struct platform_device *pdev)
272{
273	of_clk_del_provider(pdev->dev.of_node);
274
275	exynos_audss_clk_teardown();
276	pm_runtime_disable(&pdev->dev);
277
278	if (!IS_ERR(epll))
279		clk_disable_unprepare(epll);
280}
281
282static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
283	SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
284			   NULL)
285	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
286				     pm_runtime_force_resume)
287};
288
289static struct platform_driver exynos_audss_clk_driver = {
290	.driver	= {
291		.name = "exynos-audss-clk",
292		.of_match_table = exynos_audss_clk_of_match,
293		.pm = &exynos_audss_clk_pm_ops,
294	},
295	.probe = exynos_audss_clk_probe,
296	.remove = exynos_audss_clk_remove,
297};
298
299module_platform_driver(exynos_audss_clk_driver);
300
301MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
302MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
303MODULE_LICENSE("GPL v2");
304MODULE_ALIAS("platform:exynos-audss-clk");