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rst-rv1126b.c
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linux-6.19.14/drivers/clk/rockchip/rst-rv1126b.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2025 Rockchip Electronics Co., Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <dt-bindings/reset/rockchip,rv1126b-cru.h> 10#include "clk.h" 11 12/* 0x20000000 + 0x0A00 */ 13#define TOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x0 * 4 + reg * 16 + bit) 14/* 0x20010000 + 0x0A00 */ 15#define BUSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + reg * 16 + bit) 16/* 0x20020000 + 0x0A00 */ 17#define PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + reg * 16 + bit) 18/* 0x20030000 + 0x0A00 */ 19#define CORECRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000 * 4 + reg * 16 + bit) 20/* 0x20040000 + 0x0A00 */ 21#define PMUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x40000 * 4 + reg * 16 + bit) 22/* 0x20050000 + 0x0A00 */ 23#define PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x50000 * 4 + reg * 16 + bit) 24/* 0x20060000 + 0x0A00 */ 25#define DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x60000 * 4 + reg * 16 + bit) 26/* 0x20068000 + 0x0A00 */ 27#define SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x68000 * 4 + reg * 16 + bit) 28/* 0x20070000 + 0x0A00 */ 29#define VICRU_RESET_OFFSET(id, reg, bit) [id] = (0x70000 * 4 + reg * 16 + bit) 30/* 0x20080000 + 0x0A00 */ 31#define VEPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x80000 * 4 + reg * 16 + bit) 32/* 0x20090000 + 0x0A00 */ 33#define NPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x90000 * 4 + reg * 16 + bit) 34/* 0x200A0000 + 0x0A00 */ 35#define VDOCRU_RESET_OFFSET(id, reg, bit) [id] = (0xA0000 * 4 + reg * 16 + bit) 36/* 0x200B0000 + 0x0A00 */ 37#define VCPCRU_RESET_OFFSET(id, reg, bit) [id] = (0xB0000 * 4 + reg * 16 + bit) 38 39/* =================mapping table for reset ID to register offset================== */ 40static const int rv1126b_register_offset[] = { 41 /* TOPCRU-->SOFTRST_CON00 */ 42 43 /* TOPCRU-->SOFTRST_CON15 */ 44 TOPCRU_RESET_OFFSET(SRST_P_CRU, 15, 1), 45 TOPCRU_RESET_OFFSET(SRST_P_CRU_BIU, 15, 2), 46 47 /* BUSCRU-->SOFTRST_CON00 */ 48 BUSCRU_RESET_OFFSET(SRST_A_TOP_BIU, 0, 0), 49 BUSCRU_RESET_OFFSET(SRST_A_RKCE_BIU, 0, 1), 50 BUSCRU_RESET_OFFSET(SRST_A_BUS_BIU, 0, 2), 51 BUSCRU_RESET_OFFSET(SRST_H_BUS_BIU, 0, 3), 52 BUSCRU_RESET_OFFSET(SRST_P_BUS_BIU, 0, 4), 53 BUSCRU_RESET_OFFSET(SRST_P_CRU_BUS, 0, 5), 54 BUSCRU_RESET_OFFSET(SRST_P_SYS_GRF, 0, 6), 55 BUSCRU_RESET_OFFSET(SRST_H_BOOTROM, 0, 7), 56 BUSCRU_RESET_OFFSET(SRST_A_GIC400, 0, 8), 57 BUSCRU_RESET_OFFSET(SRST_A_SPINLOCK, 0, 9), 58 BUSCRU_RESET_OFFSET(SRST_P_WDT_NS, 0, 10), 59 BUSCRU_RESET_OFFSET(SRST_T_WDT_NS, 0, 11), 60 61 /* BUSCRU-->SOFTRST_CON01 */ 62 BUSCRU_RESET_OFFSET(SRST_P_WDT_HPMCU, 1, 0), 63 BUSCRU_RESET_OFFSET(SRST_T_WDT_HPMCU, 1, 1), 64 BUSCRU_RESET_OFFSET(SRST_H_CACHE, 1, 2), 65 BUSCRU_RESET_OFFSET(SRST_P_HPMCU_MAILBOX, 1, 3), 66 BUSCRU_RESET_OFFSET(SRST_P_HPMCU_INTMUX, 1, 4), 67 BUSCRU_RESET_OFFSET(SRST_HPMCU_FULL_CLUSTER, 1, 5), 68 BUSCRU_RESET_OFFSET(SRST_HPMCU_PWUP, 1, 6), 69 BUSCRU_RESET_OFFSET(SRST_HPMCU_ONLY_CORE, 1, 7), 70 BUSCRU_RESET_OFFSET(SRST_T_HPMCU_JTAG, 1, 8), 71 BUSCRU_RESET_OFFSET(SRST_P_RKDMA, 1, 11), 72 BUSCRU_RESET_OFFSET(SRST_A_RKDMA, 1, 12), 73 74 /* BUSCRU-->SOFTRST_CON02 */ 75 BUSCRU_RESET_OFFSET(SRST_P_DCF, 2, 0), 76 BUSCRU_RESET_OFFSET(SRST_A_DCF, 2, 1), 77 BUSCRU_RESET_OFFSET(SRST_H_RGA, 2, 2), 78 BUSCRU_RESET_OFFSET(SRST_A_RGA, 2, 3), 79 BUSCRU_RESET_OFFSET(SRST_CORE_RGA, 2, 4), 80 BUSCRU_RESET_OFFSET(SRST_P_TIMER, 2, 5), 81 BUSCRU_RESET_OFFSET(SRST_TIMER0, 2, 6), 82 BUSCRU_RESET_OFFSET(SRST_TIMER1, 2, 7), 83 BUSCRU_RESET_OFFSET(SRST_TIMER2, 2, 8), 84 BUSCRU_RESET_OFFSET(SRST_TIMER3, 2, 9), 85 BUSCRU_RESET_OFFSET(SRST_TIMER4, 2, 10), 86 BUSCRU_RESET_OFFSET(SRST_TIMER5, 2, 11), 87 BUSCRU_RESET_OFFSET(SRST_A_RKCE, 2, 12), 88 BUSCRU_RESET_OFFSET(SRST_PKA_RKCE, 2, 13), 89 BUSCRU_RESET_OFFSET(SRST_H_RKRNG_S, 2, 14), 90 BUSCRU_RESET_OFFSET(SRST_H_RKRNG_NS, 2, 15), 91 92 /* BUSCRU-->SOFTRST_CON03 */ 93 BUSCRU_RESET_OFFSET(SRST_P_I2C0, 3, 0), 94 BUSCRU_RESET_OFFSET(SRST_I2C0, 3, 1), 95 BUSCRU_RESET_OFFSET(SRST_P_I2C1, 3, 2), 96 BUSCRU_RESET_OFFSET(SRST_I2C1, 3, 3), 97 BUSCRU_RESET_OFFSET(SRST_P_I2C3, 3, 4), 98 BUSCRU_RESET_OFFSET(SRST_I2C3, 3, 5), 99 BUSCRU_RESET_OFFSET(SRST_P_I2C4, 3, 6), 100 BUSCRU_RESET_OFFSET(SRST_I2C4, 3, 7), 101 BUSCRU_RESET_OFFSET(SRST_P_I2C5, 3, 8), 102 BUSCRU_RESET_OFFSET(SRST_I2C5, 3, 9), 103 BUSCRU_RESET_OFFSET(SRST_P_SPI0, 3, 10), 104 BUSCRU_RESET_OFFSET(SRST_SPI0, 3, 11), 105 BUSCRU_RESET_OFFSET(SRST_P_SPI1, 3, 12), 106 BUSCRU_RESET_OFFSET(SRST_SPI1, 3, 13), 107 108 /* BUSCRU-->SOFTRST_CON04 */ 109 BUSCRU_RESET_OFFSET(SRST_P_PWM0, 4, 0), 110 BUSCRU_RESET_OFFSET(SRST_PWM0, 4, 1), 111 BUSCRU_RESET_OFFSET(SRST_P_PWM2, 4, 4), 112 BUSCRU_RESET_OFFSET(SRST_PWM2, 4, 5), 113 BUSCRU_RESET_OFFSET(SRST_P_PWM3, 4, 8), 114 BUSCRU_RESET_OFFSET(SRST_PWM3, 4, 9), 115 116 /* BUSCRU-->SOFTRST_CON05 */ 117 BUSCRU_RESET_OFFSET(SRST_P_UART1, 5, 0), 118 BUSCRU_RESET_OFFSET(SRST_S_UART1, 5, 1), 119 BUSCRU_RESET_OFFSET(SRST_P_UART2, 5, 2), 120 BUSCRU_RESET_OFFSET(SRST_S_UART2, 5, 3), 121 BUSCRU_RESET_OFFSET(SRST_P_UART3, 5, 4), 122 BUSCRU_RESET_OFFSET(SRST_S_UART3, 5, 5), 123 BUSCRU_RESET_OFFSET(SRST_P_UART4, 5, 6), 124 BUSCRU_RESET_OFFSET(SRST_S_UART4, 5, 7), 125 BUSCRU_RESET_OFFSET(SRST_P_UART5, 5, 8), 126 BUSCRU_RESET_OFFSET(SRST_S_UART5, 5, 9), 127 BUSCRU_RESET_OFFSET(SRST_P_UART6, 5, 10), 128 BUSCRU_RESET_OFFSET(SRST_S_UART6, 5, 11), 129 BUSCRU_RESET_OFFSET(SRST_P_UART7, 5, 12), 130 BUSCRU_RESET_OFFSET(SRST_S_UART7, 5, 13), 131 132 /* BUSCRU-->SOFTRST_CON06 */ 133 BUSCRU_RESET_OFFSET(SRST_P_TSADC, 6, 0), 134 BUSCRU_RESET_OFFSET(SRST_TSADC, 6, 1), 135 BUSCRU_RESET_OFFSET(SRST_H_SAI0, 6, 2), 136 BUSCRU_RESET_OFFSET(SRST_M_SAI0, 6, 3), 137 BUSCRU_RESET_OFFSET(SRST_H_SAI1, 6, 4), 138 BUSCRU_RESET_OFFSET(SRST_M_SAI1, 6, 5), 139 BUSCRU_RESET_OFFSET(SRST_H_SAI2, 6, 6), 140 BUSCRU_RESET_OFFSET(SRST_M_SAI2, 6, 7), 141 BUSCRU_RESET_OFFSET(SRST_H_RKDSM, 6, 8), 142 BUSCRU_RESET_OFFSET(SRST_M_RKDSM, 6, 9), 143 BUSCRU_RESET_OFFSET(SRST_H_PDM, 6, 10), 144 BUSCRU_RESET_OFFSET(SRST_M_PDM, 6, 11), 145 BUSCRU_RESET_OFFSET(SRST_PDM, 6, 12), 146 147 /* BUSCRU-->SOFTRST_CON07 */ 148 BUSCRU_RESET_OFFSET(SRST_H_ASRC0, 7, 0), 149 BUSCRU_RESET_OFFSET(SRST_ASRC0, 7, 1), 150 BUSCRU_RESET_OFFSET(SRST_H_ASRC1, 7, 2), 151 BUSCRU_RESET_OFFSET(SRST_ASRC1, 7, 3), 152 BUSCRU_RESET_OFFSET(SRST_P_AUDIO_ADC_BUS, 7, 4), 153 BUSCRU_RESET_OFFSET(SRST_M_AUDIO_ADC_BUS, 7, 5), 154 BUSCRU_RESET_OFFSET(SRST_P_RKCE, 7, 6), 155 BUSCRU_RESET_OFFSET(SRST_H_NS_RKCE, 7, 7), 156 BUSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 7, 8), 157 BUSCRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 7, 9), 158 BUSCRU_RESET_OFFSET(SRST_USER_OTPC_NS, 7, 10), 159 BUSCRU_RESET_OFFSET(SRST_OTPC_ARB, 7, 11), 160 BUSCRU_RESET_OFFSET(SRST_P_OTP_MASK, 7, 12), 161 162 /* PERICRU-->SOFTRST_CON00 */ 163 PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 0, 0), 164 PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 0, 1), 165 PERICRU_RESET_OFFSET(SRST_P_RTC_BIU, 0, 2), 166 PERICRU_RESET_OFFSET(SRST_P_CRU_PERI, 0, 3), 167 PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 0, 4), 168 PERICRU_RESET_OFFSET(SRST_P_GPIO1, 0, 5), 169 PERICRU_RESET_OFFSET(SRST_DB_GPIO1, 0, 6), 170 PERICRU_RESET_OFFSET(SRST_P_IOC_VCCIO1, 0, 7), 171 PERICRU_RESET_OFFSET(SRST_A_USB3OTG, 0, 8), 172 PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 0, 11), 173 PERICRU_RESET_OFFSET(SRST_H_ARB_USB2HOST, 0, 12), 174 PERICRU_RESET_OFFSET(SRST_P_RTC_TEST, 0, 13), 175 176 /* PERICRU-->SOFTRST_CON01 */ 177 PERICRU_RESET_OFFSET(SRST_H_EMMC, 1, 0), 178 PERICRU_RESET_OFFSET(SRST_H_FSPI0, 1, 1), 179 PERICRU_RESET_OFFSET(SRST_H_XIP_FSPI0, 1, 2), 180 PERICRU_RESET_OFFSET(SRST_S_2X_FSPI0, 1, 3), 181 PERICRU_RESET_OFFSET(SRST_UTMI_USB2HOST, 1, 5), 182 PERICRU_RESET_OFFSET(SRST_REF_PIPEPHY, 1, 7), 183 PERICRU_RESET_OFFSET(SRST_P_PIPEPHY, 1, 8), 184 PERICRU_RESET_OFFSET(SRST_P_PIPEPHY_GRF, 1, 9), 185 PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 1, 10), 186 PERICRU_RESET_OFFSET(SRST_POR_USB2PHY, 1, 11), 187 PERICRU_RESET_OFFSET(SRST_OTG_USB2PHY, 1, 12), 188 PERICRU_RESET_OFFSET(SRST_HOST_USB2PHY, 1, 13), 189 190 /* CORECRU-->SOFTRST_CON00 */ 191 CORECRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 0, 0), 192 CORECRU_RESET_OFFSET(SRST_NCOREPORESET0, 0, 1), 193 CORECRU_RESET_OFFSET(SRST_NCORESET0, 0, 2), 194 CORECRU_RESET_OFFSET(SRST_NCOREPORESET1, 0, 3), 195 CORECRU_RESET_OFFSET(SRST_NCORESET1, 0, 4), 196 CORECRU_RESET_OFFSET(SRST_NCOREPORESET2, 0, 5), 197 CORECRU_RESET_OFFSET(SRST_NCORESET2, 0, 6), 198 CORECRU_RESET_OFFSET(SRST_NCOREPORESET3, 0, 7), 199 CORECRU_RESET_OFFSET(SRST_NCORESET3, 0, 8), 200 CORECRU_RESET_OFFSET(SRST_NDBGRESET, 0, 9), 201 CORECRU_RESET_OFFSET(SRST_NL2RESET, 0, 10), 202 203 /* CORECRU-->SOFTRST_CON01 */ 204 CORECRU_RESET_OFFSET(SRST_A_CORE_BIU, 1, 0), 205 CORECRU_RESET_OFFSET(SRST_P_CORE_BIU, 1, 1), 206 CORECRU_RESET_OFFSET(SRST_H_CORE_BIU, 1, 2), 207 CORECRU_RESET_OFFSET(SRST_P_DBG, 1, 3), 208 CORECRU_RESET_OFFSET(SRST_POT_DBG, 1, 4), 209 CORECRU_RESET_OFFSET(SRST_NT_DBG, 1, 5), 210 CORECRU_RESET_OFFSET(SRST_P_CORE_PVTPLL, 1, 6), 211 CORECRU_RESET_OFFSET(SRST_P_CRU_CORE, 1, 7), 212 CORECRU_RESET_OFFSET(SRST_P_CORE_GRF, 1, 8), 213 CORECRU_RESET_OFFSET(SRST_P_DFT2APB, 1, 10), 214 215 /* PMUCRU-->SOFTRST_CON00 */ 216 PMUCRU_RESET_OFFSET(SRST_H_PMU_BIU, 0, 0), 217 PMUCRU_RESET_OFFSET(SRST_P_PMU_GPIO0, 0, 7), 218 PMUCRU_RESET_OFFSET(SRST_DB_PMU_GPIO0, 0, 8), 219 PMUCRU_RESET_OFFSET(SRST_P_PMU_HP_TIMER, 0, 10), 220 PMUCRU_RESET_OFFSET(SRST_PMU_HP_TIMER, 0, 11), 221 PMUCRU_RESET_OFFSET(SRST_PMU_32K_HP_TIMER, 0, 12), 222 223 /* PMUCRU-->SOFTRST_CON01 */ 224 PMUCRU_RESET_OFFSET(SRST_P_PWM1, 1, 0), 225 PMUCRU_RESET_OFFSET(SRST_PWM1, 1, 1), 226 PMUCRU_RESET_OFFSET(SRST_P_I2C2, 1, 2), 227 PMUCRU_RESET_OFFSET(SRST_I2C2, 1, 3), 228 PMUCRU_RESET_OFFSET(SRST_P_UART0, 1, 4), 229 PMUCRU_RESET_OFFSET(SRST_S_UART0, 1, 5), 230 231 /* PMUCRU-->SOFTRST_CON02 */ 232 PMUCRU_RESET_OFFSET(SRST_P_RCOSC_CTRL, 2, 0), 233 PMUCRU_RESET_OFFSET(SRST_REF_RCOSC_CTRL, 2, 2), 234 PMUCRU_RESET_OFFSET(SRST_P_IOC_PMUIO0, 2, 3), 235 PMUCRU_RESET_OFFSET(SRST_P_CRU_PMU, 2, 4), 236 PMUCRU_RESET_OFFSET(SRST_P_PMU_GRF, 2, 5), 237 PMUCRU_RESET_OFFSET(SRST_PREROLL, 2, 7), 238 PMUCRU_RESET_OFFSET(SRST_PREROLL_32K, 2, 8), 239 PMUCRU_RESET_OFFSET(SRST_H_PMU_SRAM, 2, 9), 240 241 /* PMUCRU-->SOFTRST_CON03 */ 242 PMUCRU_RESET_OFFSET(SRST_P_WDT_LPMCU, 3, 0), 243 PMUCRU_RESET_OFFSET(SRST_T_WDT_LPMCU, 3, 1), 244 PMUCRU_RESET_OFFSET(SRST_LPMCU_FULL_CLUSTER, 3, 2), 245 PMUCRU_RESET_OFFSET(SRST_LPMCU_PWUP, 3, 3), 246 PMUCRU_RESET_OFFSET(SRST_LPMCU_ONLY_CORE, 3, 4), 247 PMUCRU_RESET_OFFSET(SRST_T_LPMCU_JTAG, 3, 5), 248 PMUCRU_RESET_OFFSET(SRST_P_LPMCU_MAILBOX, 3, 6), 249 250 /* PMU1CRU-->SOFTRST_CON00 */ 251 PMU1CRU_RESET_OFFSET(SRST_P_SPI2AHB, 0, 0), 252 PMU1CRU_RESET_OFFSET(SRST_H_SPI2AHB, 0, 1), 253 PMU1CRU_RESET_OFFSET(SRST_H_FSPI1, 0, 2), 254 PMU1CRU_RESET_OFFSET(SRST_H_XIP_FSPI1, 0, 3), 255 PMU1CRU_RESET_OFFSET(SRST_S_1X_FSPI1, 0, 4), 256 PMU1CRU_RESET_OFFSET(SRST_P_IOC_PMUIO1, 0, 5), 257 PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 0, 6), 258 PMU1CRU_RESET_OFFSET(SRST_P_AUDIO_ADC_PMU, 0, 7), 259 PMU1CRU_RESET_OFFSET(SRST_M_AUDIO_ADC_PMU, 0, 8), 260 PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 9), 261 262 /* PMU1CRU-->SOFTRST_CON01 */ 263 PMU1CRU_RESET_OFFSET(SRST_P_LPDMA, 1, 0), 264 PMU1CRU_RESET_OFFSET(SRST_A_LPDMA, 1, 1), 265 PMU1CRU_RESET_OFFSET(SRST_H_LPSAI, 1, 2), 266 PMU1CRU_RESET_OFFSET(SRST_M_LPSAI, 1, 3), 267 PMU1CRU_RESET_OFFSET(SRST_P_AOA_TDD, 1, 4), 268 PMU1CRU_RESET_OFFSET(SRST_P_AOA_FE, 1, 5), 269 PMU1CRU_RESET_OFFSET(SRST_P_AOA_AAD, 1, 6), 270 PMU1CRU_RESET_OFFSET(SRST_P_AOA_APB, 1, 7), 271 PMU1CRU_RESET_OFFSET(SRST_P_AOA_SRAM, 1, 8), 272 273 /* DDRCRU-->SOFTRST_CON00 */ 274 DDRCRU_RESET_OFFSET(SRST_P_DDR_BIU, 0, 1), 275 DDRCRU_RESET_OFFSET(SRST_P_DDRC, 0, 2), 276 DDRCRU_RESET_OFFSET(SRST_P_DDRMON, 0, 3), 277 DDRCRU_RESET_OFFSET(SRST_TIMER_DDRMON, 0, 4), 278 DDRCRU_RESET_OFFSET(SRST_P_DFICTRL, 0, 5), 279 DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 0, 6), 280 DDRCRU_RESET_OFFSET(SRST_P_CRU_DDR, 0, 7), 281 DDRCRU_RESET_OFFSET(SRST_P_DDRPHY, 0, 8), 282 DDRCRU_RESET_OFFSET(SRST_P_DMA2DDR, 0, 9), 283 284 /* SUBDDRCRU-->SOFTRST_CON00 */ 285 SUBDDRCRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 0, 0), 286 SUBDDRCRU_RESET_OFFSET(SRST_A_SYSMEM, 0, 1), 287 SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_BIU, 0, 2), 288 SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH0_CPU, 0, 3), 289 SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH1_NPU, 0, 4), 290 SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH2_POE, 0, 5), 291 SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH3_VI, 0, 6), 292 SUBDDRCRU_RESET_OFFSET(SRST_CORE_DDRC, 0, 7), 293 SUBDDRCRU_RESET_OFFSET(SRST_DDRMON, 0, 8), 294 SUBDDRCRU_RESET_OFFSET(SRST_DFICTRL, 0, 9), 295 SUBDDRCRU_RESET_OFFSET(SRST_RS, 0, 11), 296 SUBDDRCRU_RESET_OFFSET(SRST_A_DMA2DDR, 0, 12), 297 SUBDDRCRU_RESET_OFFSET(SRST_DDRPHY, 0, 13), 298 299 /* VICRU-->SOFTRST_CON00 */ 300 VICRU_RESET_OFFSET(SRST_REF_PVTPLL_ISP, 0, 0), 301 VICRU_RESET_OFFSET(SRST_A_GMAC_BIU, 0, 1), 302 VICRU_RESET_OFFSET(SRST_A_VI_BIU, 0, 2), 303 VICRU_RESET_OFFSET(SRST_H_VI_BIU, 0, 3), 304 VICRU_RESET_OFFSET(SRST_P_VI_BIU, 0, 4), 305 VICRU_RESET_OFFSET(SRST_P_CRU_VI, 0, 5), 306 VICRU_RESET_OFFSET(SRST_P_VI_GRF, 0, 6), 307 VICRU_RESET_OFFSET(SRST_P_VI_PVTPLL, 0, 7), 308 VICRU_RESET_OFFSET(SRST_P_DSMC, 0, 8), 309 VICRU_RESET_OFFSET(SRST_A_DSMC, 0, 9), 310 VICRU_RESET_OFFSET(SRST_H_CAN0, 0, 10), 311 VICRU_RESET_OFFSET(SRST_CAN0, 0, 11), 312 VICRU_RESET_OFFSET(SRST_H_CAN1, 0, 12), 313 VICRU_RESET_OFFSET(SRST_CAN1, 0, 13), 314 315 /* VICRU-->SOFTRST_CON01 */ 316 VICRU_RESET_OFFSET(SRST_P_GPIO2, 1, 0), 317 VICRU_RESET_OFFSET(SRST_DB_GPIO2, 1, 1), 318 VICRU_RESET_OFFSET(SRST_P_GPIO4, 1, 2), 319 VICRU_RESET_OFFSET(SRST_DB_GPIO4, 1, 3), 320 VICRU_RESET_OFFSET(SRST_P_GPIO5, 1, 4), 321 VICRU_RESET_OFFSET(SRST_DB_GPIO5, 1, 5), 322 VICRU_RESET_OFFSET(SRST_P_GPIO6, 1, 6), 323 VICRU_RESET_OFFSET(SRST_DB_GPIO6, 1, 7), 324 VICRU_RESET_OFFSET(SRST_P_GPIO7, 1, 8), 325 VICRU_RESET_OFFSET(SRST_DB_GPIO7, 1, 9), 326 VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO2, 1, 10), 327 VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO4, 1, 11), 328 VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO5, 1, 12), 329 VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO6, 1, 13), 330 VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO7, 1, 14), 331 332 /* VICRU-->SOFTRST_CON02 */ 333 VICRU_RESET_OFFSET(SRST_CORE_ISP, 2, 0), 334 VICRU_RESET_OFFSET(SRST_H_VICAP, 2, 1), 335 VICRU_RESET_OFFSET(SRST_A_VICAP, 2, 2), 336 VICRU_RESET_OFFSET(SRST_D_VICAP, 2, 3), 337 VICRU_RESET_OFFSET(SRST_ISP0_VICAP, 2, 4), 338 VICRU_RESET_OFFSET(SRST_CORE_VPSS, 2, 5), 339 VICRU_RESET_OFFSET(SRST_CORE_VPSL, 2, 6), 340 VICRU_RESET_OFFSET(SRST_P_CSI2HOST0, 2, 7), 341 VICRU_RESET_OFFSET(SRST_P_CSI2HOST1, 2, 8), 342 VICRU_RESET_OFFSET(SRST_P_CSI2HOST2, 2, 9), 343 VICRU_RESET_OFFSET(SRST_P_CSI2HOST3, 2, 10), 344 VICRU_RESET_OFFSET(SRST_H_SDMMC0, 2, 11), 345 VICRU_RESET_OFFSET(SRST_A_GMAC, 2, 12), 346 VICRU_RESET_OFFSET(SRST_P_CSIPHY0, 2, 13), 347 VICRU_RESET_OFFSET(SRST_P_CSIPHY1, 2, 14), 348 349 /* VICRU-->SOFTRST_CON03 */ 350 VICRU_RESET_OFFSET(SRST_P_MACPHY, 3, 0), 351 VICRU_RESET_OFFSET(SRST_MACPHY, 3, 1), 352 VICRU_RESET_OFFSET(SRST_P_SARADC1, 3, 2), 353 VICRU_RESET_OFFSET(SRST_SARADC1, 3, 3), 354 VICRU_RESET_OFFSET(SRST_P_SARADC2, 3, 5), 355 VICRU_RESET_OFFSET(SRST_SARADC2, 3, 6), 356 357 /* VEPUCRU-->SOFTRST_CON00 */ 358 VEPUCRU_RESET_OFFSET(SRST_REF_PVTPLL_VEPU, 0, 0), 359 VEPUCRU_RESET_OFFSET(SRST_A_VEPU_BIU, 0, 1), 360 VEPUCRU_RESET_OFFSET(SRST_H_VEPU_BIU, 0, 2), 361 VEPUCRU_RESET_OFFSET(SRST_P_VEPU_BIU, 0, 3), 362 VEPUCRU_RESET_OFFSET(SRST_P_CRU_VEPU, 0, 4), 363 VEPUCRU_RESET_OFFSET(SRST_P_VEPU_GRF, 0, 5), 364 VEPUCRU_RESET_OFFSET(SRST_P_GPIO3, 0, 7), 365 VEPUCRU_RESET_OFFSET(SRST_DB_GPIO3, 0, 8), 366 VEPUCRU_RESET_OFFSET(SRST_P_IOC_VCCIO3, 0, 9), 367 VEPUCRU_RESET_OFFSET(SRST_P_SARADC0, 0, 10), 368 VEPUCRU_RESET_OFFSET(SRST_SARADC0, 0, 11), 369 VEPUCRU_RESET_OFFSET(SRST_H_SDMMC1, 0, 13), 370 371 /* VEPUCRU-->SOFTRST_CON01 */ 372 VEPUCRU_RESET_OFFSET(SRST_P_VEPU_PVTPLL, 1, 0), 373 VEPUCRU_RESET_OFFSET(SRST_H_VEPU, 1, 1), 374 VEPUCRU_RESET_OFFSET(SRST_A_VEPU, 1, 2), 375 VEPUCRU_RESET_OFFSET(SRST_CORE_VEPU, 1, 3), 376 377 /* NPUCRU-->SOFTRST_CON00 */ 378 NPUCRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 0, 0), 379 NPUCRU_RESET_OFFSET(SRST_A_NPU_BIU, 0, 2), 380 NPUCRU_RESET_OFFSET(SRST_H_NPU_BIU, 0, 3), 381 NPUCRU_RESET_OFFSET(SRST_P_NPU_BIU, 0, 4), 382 NPUCRU_RESET_OFFSET(SRST_P_CRU_NPU, 0, 5), 383 NPUCRU_RESET_OFFSET(SRST_P_NPU_GRF, 0, 6), 384 NPUCRU_RESET_OFFSET(SRST_P_NPU_PVTPLL, 0, 8), 385 NPUCRU_RESET_OFFSET(SRST_H_RKNN, 0, 9), 386 NPUCRU_RESET_OFFSET(SRST_A_RKNN, 0, 10), 387 388 /* VDOCRU-->SOFTRST_CON00 */ 389 VDOCRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 0, 0), 390 VDOCRU_RESET_OFFSET(SRST_A_VDO_BIU, 0, 1), 391 VDOCRU_RESET_OFFSET(SRST_H_VDO_BIU, 0, 3), 392 VDOCRU_RESET_OFFSET(SRST_P_VDO_BIU, 0, 4), 393 VDOCRU_RESET_OFFSET(SRST_P_CRU_VDO, 0, 5), 394 VDOCRU_RESET_OFFSET(SRST_P_VDO_GRF, 0, 6), 395 VDOCRU_RESET_OFFSET(SRST_A_RKVDEC, 0, 7), 396 VDOCRU_RESET_OFFSET(SRST_H_RKVDEC, 0, 8), 397 VDOCRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 0, 9), 398 VDOCRU_RESET_OFFSET(SRST_A_VOP, 0, 10), 399 VDOCRU_RESET_OFFSET(SRST_H_VOP, 0, 11), 400 VDOCRU_RESET_OFFSET(SRST_D_VOP, 0, 12), 401 VDOCRU_RESET_OFFSET(SRST_A_OOC, 0, 13), 402 VDOCRU_RESET_OFFSET(SRST_H_OOC, 0, 14), 403 VDOCRU_RESET_OFFSET(SRST_D_OOC, 0, 15), 404 405 /* VDOCRU-->SOFTRST_CON01 */ 406 VDOCRU_RESET_OFFSET(SRST_H_RKJPEG, 1, 3), 407 VDOCRU_RESET_OFFSET(SRST_A_RKJPEG, 1, 4), 408 VDOCRU_RESET_OFFSET(SRST_A_RKMMU_DECOM, 1, 5), 409 VDOCRU_RESET_OFFSET(SRST_H_RKMMU_DECOM, 1, 6), 410 VDOCRU_RESET_OFFSET(SRST_D_DECOM, 1, 8), 411 VDOCRU_RESET_OFFSET(SRST_A_DECOM, 1, 9), 412 VDOCRU_RESET_OFFSET(SRST_P_DECOM, 1, 10), 413 VDOCRU_RESET_OFFSET(SRST_P_MIPI_DSI, 1, 12), 414 VDOCRU_RESET_OFFSET(SRST_P_DSIPHY, 1, 13), 415 416 /* VCPCRU-->SOFTRST_CON00 */ 417 VCPCRU_RESET_OFFSET(SRST_REF_PVTPLL_VCP, 0, 0), 418 VCPCRU_RESET_OFFSET(SRST_A_VCP_BIU, 0, 1), 419 VCPCRU_RESET_OFFSET(SRST_H_VCP_BIU, 0, 2), 420 VCPCRU_RESET_OFFSET(SRST_P_VCP_BIU, 0, 3), 421 VCPCRU_RESET_OFFSET(SRST_P_CRU_VCP, 0, 4), 422 VCPCRU_RESET_OFFSET(SRST_P_VCP_GRF, 0, 5), 423 VCPCRU_RESET_OFFSET(SRST_P_VCP_PVTPLL, 0, 7), 424 VCPCRU_RESET_OFFSET(SRST_A_AISP_BIU, 0, 8), 425 VCPCRU_RESET_OFFSET(SRST_H_AISP_BIU, 0, 9), 426 VCPCRU_RESET_OFFSET(SRST_CORE_AISP, 0, 13), 427 428 /* VCPCRU-->SOFTRST_CON01 */ 429 VCPCRU_RESET_OFFSET(SRST_H_FEC, 1, 0), 430 VCPCRU_RESET_OFFSET(SRST_A_FEC, 1, 1), 431 VCPCRU_RESET_OFFSET(SRST_CORE_FEC, 1, 2), 432 VCPCRU_RESET_OFFSET(SRST_H_AVSP, 1, 3), 433 VCPCRU_RESET_OFFSET(SRST_A_AVSP, 1, 4), 434}; 435 436void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base) 437{ 438 rockchip_register_softrst_lut(np, 439 rv1126b_register_offset, 440 ARRAY_SIZE(rv1126b_register_offset), 441 reg_base + RV1126B_SOFTRST_CON(0), 442 ROCKCHIP_SOFTRST_HIWORD_MASK); 443}
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