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rst-rk3528.c
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linux-6.19.14/drivers/clk/rockchip/rst-rk3528.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Based on Sebastian Reichel's implementation for RK3588 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <dt-bindings/reset/rockchip,rk3528-cru.h> 10#include "clk.h" 11 12/* 0xFF4A0000 + 0x0A00 */ 13#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) 14 15/* mapping table for reset ID to register offset */ 16static const int rk3528_register_offset[] = { 17 /* CRU_SOFTRST_CON03 */ 18 RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0), 19 RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1), 20 RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2), 21 RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3), 22 RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4), 23 RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5), 24 RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6), 25 RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7), 26 RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8), 27 RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9), 28 RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10), 29 30 /* CRU_SOFTRST_CON05 */ 31 RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13), 32 RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14), 33 RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15), 34 35 /* CRU_SOFTRST_CON06 */ 36 RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2), 37 RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3), 38 RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4), 39 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7), 40 41 /* CRU_SOFTRST_CON08 */ 42 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1), 43 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3), 44 RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8), 45 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10), 46 RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11), 47 RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12), 48 RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13), 49 RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15), 50 51 /* CRU_SOFTRST_CON09 */ 52 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0), 53 RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1), 54 RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2), 55 RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4), 56 RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5), 57 RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6), 58 RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7), 59 RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8), 60 RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9), 61 RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10), 62 RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11), 63 RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12), 64 RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13), 65 RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15), 66 67 /* CRU_SOFTRST_CON10 */ 68 RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0), 69 RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3), 70 RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7), 71 RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8), 72 RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10), 73 RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11), 74 RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12), 75 RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13), 76 RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14), 77 78 /* CRU_SOFTRST_CON11 */ 79 RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4), 80 RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5), 81 RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7), 82 RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8), 83 RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10), 84 RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11), 85 RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12), 86 87 /* CRU_SOFTRST_CON25 */ 88 RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6), 89 RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7), 90 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8), 91 RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9), 92 RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10), 93 RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11), 94 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12), 95 RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13), 96 RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14), 97 RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15), 98 99 /* CRU_SOFTRST_CON26 */ 100 RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0), 101 RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1), 102 RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2), 103 RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3), 104 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4), 105 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5), 106 RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6), 107 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8), 108 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9), 109 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10), 110 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11), 111 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12), 112 RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13), 113 114 /* CRU_SOFTRST_CON27 */ 115 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0), 116 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1), 117 RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4), 118 RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5), 119 RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7), 120 RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8), 121 RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9), 122 RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10), 123 RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11), 124 RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12), 125 RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13), 126 RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14), 127 RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15), 128 129 /* CRU_SOFTRST_CON28 */ 130 RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0), 131 RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1), 132 RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2), 133 RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3), 134 RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4), 135 RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5), 136 137 /* CRU_SOFTRST_CON30 */ 138 RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1), 139 RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2), 140 RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3), 141 RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6), 142 RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7), 143 144 /* CRU_SOFTRST_CON32 */ 145 RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2), 146 RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4), 147 RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5), 148 RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6), 149 RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7), 150 RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8), 151 RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9), 152 RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10), 153 RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11), 154 RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12), 155 RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13), 156 RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14), 157 RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15), 158 159 /* CRU_SOFTRST_CON33 */ 160 RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1), 161 162 /* CRU_SOFTRST_CON34 */ 163 RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3), 164 RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5), 165 RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8), 166 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9), 167 168 /* CRU_SOFTRST_CON36 */ 169 RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3), 170 RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4), 171 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5), 172 RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6), 173 RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7), 174 RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8), 175 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9), 176 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10), 177 RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11), 178 RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12), 179 RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13), 180 RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14), 181 182 /* CRU_SOFTRST_CON37 */ 183 RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2), 184 RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3), 185 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8), 186 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9), 187 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10), 188 RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14), 189 RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15), 190 191 /* CRU_SOFTRST_CON38 */ 192 RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0), 193 RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1), 194 RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2), 195 RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3), 196 RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4), 197 RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5), 198 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6), 199 RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7), 200 RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8), 201 RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9), 202 RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10), 203 204 /* CRU_SOFTRST_CON39 */ 205 RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3), 206 RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4), 207 RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5), 208 RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7), 209 RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8), 210 RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9), 211 RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10), 212 RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11), 213 RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12), 214 RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13), 215 RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15), 216 217 /* CRU_SOFTRST_CON40 */ 218 RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1), 219 RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2), 220 RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3), 221 RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4), 222 RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5), 223 RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6), 224 RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7), 225 RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14), 226 RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15), 227 228 /* CRU_SOFTRST_CON41 */ 229 RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0), 230 RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1), 231 RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2), 232 RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3), 233 RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4), 234 RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5), 235 RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6), 236 RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7), 237 RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9), 238 RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10), 239 240 /* CRU_SOFTRST_CON42 */ 241 RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0), 242 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1), 243 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2), 244 RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3), 245 RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4), 246 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5), 247 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6), 248 RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7), 249 RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9), 250 RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11), 251 RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12), 252 RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13), 253 254 /* CRU_SOFTRST_CON43 */ 255 RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2), 256 RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3), 257 RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4), 258 RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6), 259 RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7), 260 RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8), 261 RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9), 262 RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10), 263 RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11), 264 RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12), 265 RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13), 266 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14), 267 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15), 268 269 /* CRU_SOFTRST_CON44 */ 270 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0), 271 RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4), 272 RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6), 273 RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7), 274 RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8), 275 RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9), 276 RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11), 277 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12), 278 279 /* CRU_SOFTRST_CON45 */ 280 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1), 281 RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2), 282 RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3), 283 RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4), 284 RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5), 285 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6), 286 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8), 287 RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9), 288 RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10), 289 RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11), 290 RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12), 291 RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13), 292 RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14), 293 RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15), 294 295 /* CRU_SOFTRST_CON46 */ 296 RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0), 297}; 298 299void rk3528_rst_init(struct device_node *np, void __iomem *reg_base) 300{ 301 rockchip_register_softrst_lut(np, 302 rk3528_register_offset, 303 ARRAY_SIZE(rk3528_register_offset), 304 reg_base + RK3528_SOFTRST_CON(0), 305 ROCKCHIP_SOFTRST_HIWORD_MASK); 306}
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