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clk-rv1126b.c
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linux-6.19.14/drivers/clk/rockchip/clk-rv1126b.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/clk-provider.h> 9#include <linux/module.h> 10#include <linux/of.h> 11#include <linux/of_address.h> 12#include <linux/of_device.h> 13#include <linux/platform_device.h> 14#include <linux/regmap.h> 15#include <linux/syscore_ops.h> 16#include <dt-bindings/clock/rockchip,rv1126b-cru.h> 17#include "clk.h" 18 19#define RV1126B_FRAC_MAX_PRATE 1200000000 20 21#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16)) 22 23enum rv1126b_plls { 24 gpll, cpll, aupll, dpll 25}; 26 27static struct rockchip_pll_rate_table rv1126b_pll_rates[] = { 28 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 29 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), 30 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), 31 RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137), 32 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), 33 RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355), 34 RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127), 35 RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185), 36 { /* sentinel */ }, 37}; 38 39#define RV1126B_DIV_ACLK_CORE_MASK 0x1f 40#define RV1126B_DIV_ACLK_CORE_SHIFT 0 41#define RV1126B_DIV_PCLK_CORE_MASK 0x1f 42#define RV1126B_DIV_PCLK_CORE_SHIFT 8 43#define RV1126B_CORE_SEL_MASK 0x1 44#define RV1126B_CORE_SEL_SHIFT 1 45 46#define RV1126B_CLKSEL0(_aclk_core) \ 47{ \ 48 .reg = RV1126B_CORECLKSEL_CON(2), \ 49 .val = HIWORD_UPDATE(_aclk_core - 1, RV1126B_DIV_ACLK_CORE_MASK, \ 50 RV1126B_DIV_ACLK_CORE_SHIFT), \ 51} 52 53#define RV1126B_CLKSEL1(_pclk_dbg) \ 54{ \ 55 .reg = RV1126B_CORECLKSEL_CON(2), \ 56 .val = HIWORD_UPDATE(_pclk_dbg - 1, RV1126B_DIV_PCLK_CORE_MASK, \ 57 RV1126B_DIV_PCLK_CORE_SHIFT), \ 58} 59 60#define RV1126B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ 61{ \ 62 .prate = _prate, \ 63 .divs = { \ 64 RV1126B_CLKSEL0(_aclk_core), \ 65 RV1126B_CLKSEL1(_pclk_dbg), \ 66 }, \ 67} 68 69static struct rockchip_cpuclk_rate_table rv1126b_cpuclk_rates[] __initdata = { 70 RV1126B_CPUCLK_RATE(1608000000, 4, 10), 71 RV1126B_CPUCLK_RATE(1512000000, 4, 10), 72 RV1126B_CPUCLK_RATE(1416000000, 4, 10), 73 RV1126B_CPUCLK_RATE(1296000000, 3, 10), 74 RV1126B_CPUCLK_RATE(1200000000, 3, 10), 75 RV1126B_CPUCLK_RATE(1188000000, 3, 8), 76 RV1126B_CPUCLK_RATE(1104000000, 2, 8), 77 RV1126B_CPUCLK_RATE(1008000000, 2, 8), 78 RV1126B_CPUCLK_RATE(816000000, 2, 6), 79 RV1126B_CPUCLK_RATE(600000000, 2, 4), 80 RV1126B_CPUCLK_RATE(594000000, 2, 4), 81 RV1126B_CPUCLK_RATE(408000000, 1, 3), 82 RV1126B_CPUCLK_RATE(396000000, 1, 3), 83}; 84 85PNAME(mux_pll_p) = { "xin24m" }; 86PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; 87PNAME(mux_gpll_aupll_p) = { "gpll", "aupll" }; 88PNAME(mux_gpll_aupll_cpll_p) = { "gpll", "aupll", "cpll" }; 89PNAME(mux_gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" }; 90PNAME(mux_cpll_24m_p) = { "cpll", "xin24m" }; 91PNAME(mux_24m_gpll_aupll_cpll_p) = { "xin24m", "gpll", "aupll", "cpll" }; 92PNAME(mux_24m_gpll_cpll_p) = { "xin24m", "gpll", "cpll" }; 93PNAME(mux_24m_gpll_aupll_p) = { "xin24m", "gpll", "aupll" }; 94PNAME(mux_sclk_uart_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", 95 "clk_cm_frac2", "clk_uart_frac0", "clk_uart_frac1" }; 96PNAME(mclk_sai0_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", 97 "clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1", 98 "clk_audio_int0", "clk_audio_int1", 99 "mclk_sai0_from_io" }; 100PNAME(mclk_sai1_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", 101 "clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1", 102 "clk_audio_int0", "clk_audio_int1", 103 "mclk_sai1_from_io" }; 104PNAME(mclk_sai2_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", 105 "clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1", 106 "clk_audio_int0", "clk_audio_int1", 107 "mclk_sai2_from_io" }; 108PNAME(mux_sai_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", 109 "clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1", 110 "clk_audio_int0", "clk_audio_int1", "mclk_sai0_from_io", 111 "mclk_sai1_from_io", "mclk_sai2_from_io"}; 112PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" }; 113PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" }; 114PNAME(mux_500m_400m_200m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div6" }; 115PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" }; 116PNAME(mux_500m_400m_300m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div4" }; 117PNAME(mux_333m_200m_p) = { "clk_cpll_div3", "clk_gpll_div6" }; 118PNAME(mux_600m_400m_200m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div6" }; 119PNAME(mux_400m_300m_200m_p) = { "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" }; 120PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_cpll_div10" }; 121PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", 122 "xin24m" }; 123PNAME(mux_600m_24m_p) = { "clk_gpll_div2", "xin24m" }; 124PNAME(mux_armclk_p) = { "clk_core_pll", "clk_core_pvtpll" }; 125PNAME(aclk_npu_root_p) = { "clk_npu_pll", "clk_npu_pvtpll" }; 126PNAME(clk_saradc0_p) = { "clk_saradc0_src", "clk_saradc0_rcosc_io" }; 127PNAME(clk_core_vepu_p) = { "clk_vepu_pll", "clk_vepu_pvtpll" }; 128PNAME(clk_core_fec_p) = { "clk_core_fec_src", "clk_vcp_pvtpll" }; 129PNAME(clk_core_aisp_p) = { "clk_aisp_pll", "clk_vcp_pvtpll" }; 130PNAME(clk_core_isp_root_p) = { "clk_isp_pll", "clk_isp_pvtpll" }; 131PNAME(clk_gmac_ptp_ref_p) = { "clk_gmac_ptp_ref_src", "clk_gmac_ptp_from_io" }; 132PNAME(clk_saradc1_p) = { "clk_saradc1_src", "clk_saradc1_rcosc_io" }; 133PNAME(clk_saradc2_p) = { "clk_saradc2_src", "clk_saradc2_rcosc_io" }; 134PNAME(clk_rcosc_src_p) = { "xin24m", "clk_rcosc", "clk_rcosc_div2", 135 "clk_rcosc_div3", "clk_rcosc_div4" }; 136PNAME(busclk_pmu_mux_p) = { "clk_cpll_div10", "clk_rcosc_src" }; 137PNAME(clk_xin_rc_div_p) = { "xin24m", "clk_rcosc_src" }; 138PNAME(clk_32k_p) = { "clk_xin_rc_div", "clk_32k_rtc", "clk_32k_io" }; 139PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" }; 140PNAME(mux_24m_rcosc_buspmu_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src" }; 141PNAME(mux_24m_rcosc_buspmu_32k_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src", 142 "clk_32k" }; 143PNAME(sclk_uart0_p) = { "sclk_uart0_src", "xin24m", "clk_rcosc_src" }; 144PNAME(clk_osc_rcosc_ctrl_p) = { "clk_rcosc_src", "clk_testout_out" }; 145PNAME(lrck_src_asrc_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3", 146 "fs_inter_from_sai0", "fs_inter_from_sai1", 147 "fs_inter_from_sai2", "clkout_pdm"}; 148PNAME(clk_ref_pipephy_p) = { "clk_ref_pipephy_cpll_src", "xin24m" }; 149PNAME(clk_timer0_parents_p) = { "clk_timer_root", "mclk_sai0_from_io", 150 "sclk_sai0_from_io" }; 151PNAME(clk_timer1_parents_p) = { "clk_timer_root", "mclk_sai1_from_io", 152 "sclk_sai1_from_io" }; 153PNAME(clk_timer2_parents_p) = { "clk_timer_root", "mclk_sai2_from_io", 154 "sclk_sai2_from_io" }; 155PNAME(clk_timer3_parents_p) = { "clk_timer_root", "mclk_asrc0", "mclk_asrc1" }; 156PNAME(clk_timer4_parents_p) = { "clk_timer_root", "mclk_asrc2", "mclk_asrc3" }; 157PNAME(clk_macphy_p) = { "xin24m", "clk_cpll_div20" }; 158PNAME(clk_cpll_div10_p) = { "gpll", "clk_aisp_pll_src" }; 159 160static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = { 161 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 162 CLK_IS_CRITICAL, RV1126B_PLL_CON(8), 163 RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates), 164 [aupll] = PLL(pll_rk3328, PLL_AUPLL, "aupll", mux_pll_p, 165 CLK_IS_CRITICAL, RV1126B_PLL_CON(0), 166 RV1126B_MODE_CON, 0, 10, 0, rv1126b_pll_rates), 167 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 168 CLK_IS_CRITICAL, RV1126B_PERIPLL_CON(0), 169 RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates), 170 [dpll] = PLL(pll_rk3328, 0, "dpll", mux_pll_p, 171 CLK_IS_CRITICAL, RV1126B_SUBDDRPLL_CON(0), 172 RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates), 173}; 174 175#define MFLAGS CLK_MUX_HIWORD_MASK 176#define DFLAGS CLK_DIVIDER_HIWORD_MASK 177#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 178 179static struct rockchip_clk_branch rv1126b_rcdiv_pmu_fracmux __initdata = 180 MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 181 RV1126B_PMUCLKSEL_CON(2), 1, 2, MFLAGS); 182 183static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = { 184 185 FACTOR(0, "clk_rcosc_div2", "clk_rcosc", 0, 1, 2), 186 FACTOR(0, "clk_rcosc_div3", "clk_rcosc", 0, 1, 3), 187 FACTOR(0, "clk_rcosc_div4", "clk_rcosc", 0, 1, 4), 188 189 /* Clock Definition */ 190 COMPOSITE_NODIV(CLK_AISP_PLL_SRC, "clk_aisp_pll_src", mux_gpll_aupll_cpll_p, 0, 191 RV1126B_CLKSEL_CON(62), 4, 2, MFLAGS, 192 RV1126B_CLKGATE_CON(5), 4, GFLAGS), 193 DIV(CLK_AISP_PLL, "clk_aisp_pll", "clk_aisp_pll_src", 0, 194 RV1126B_CLKSEL_CON(62), 0, 3, DFLAGS), 195 196 COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", clk_cpll_div10_p, 0, 197 RV1126B_CLKSEL_CON(1), 15, 1, MFLAGS, 5, 5, DFLAGS, 198 RV1126B_CLKGATE_CON(0), 1, GFLAGS), 199 COMPOSITE_NOMUX(CLK_CPLL_DIV20, "clk_cpll_div20", "cpll", 0, 200 RV1126B_CLKSEL_CON(1), 0, 5, DFLAGS, 201 RV1126B_CLKGATE_CON(0), 0, GFLAGS), 202 COMPOSITE_NOMUX(CLK_CPLL_DIV8, "clk_cpll_div8", "cpll", 0, 203 RV1126B_CLKSEL_CON(1), 10, 5, DFLAGS, 204 RV1126B_CLKGATE_CON(0), 2, GFLAGS), 205 COMPOSITE_NOMUX(CLK_GPLL_DIV8, "clk_gpll_div8", "gpll", 0, 206 RV1126B_CLKSEL_CON(2), 0, 5, DFLAGS, 207 RV1126B_CLKGATE_CON(0), 3, GFLAGS), 208 COMPOSITE_NOMUX(CLK_GPLL_DIV6, "clk_gpll_div6", "gpll", 0, 209 RV1126B_CLKSEL_CON(2), 5, 5, DFLAGS, 210 RV1126B_CLKGATE_CON(0), 4, GFLAGS), 211 COMPOSITE_NOMUX(CLK_GPLL_DIV4, "clk_gpll_div4", "gpll", 0, 212 RV1126B_CLKSEL_CON(2), 10, 5, DFLAGS, 213 RV1126B_CLKGATE_CON(0), 5, GFLAGS), 214 COMPOSITE_NOMUX(CLK_CPLL_DIV3, "clk_cpll_div3", "cpll", 0, 215 RV1126B_CLKSEL_CON(3), 0, 5, DFLAGS, 216 RV1126B_CLKGATE_CON(0), 6, GFLAGS), 217 COMPOSITE_NOMUX(CLK_GPLL_DIV3, "clk_gpll_div3", "gpll", 0, 218 RV1126B_CLKSEL_CON(3), 5, 5, DFLAGS, 219 RV1126B_CLKGATE_CON(0), 7, GFLAGS), 220 COMPOSITE_NOMUX(CLK_CPLL_DIV2, "clk_cpll_div2", "cpll", 0, 221 RV1126B_CLKSEL_CON(3), 10, 5, DFLAGS, 222 RV1126B_CLKGATE_CON(0), 8, GFLAGS), 223 COMPOSITE_NOMUX(CLK_GPLL_DIV2, "clk_gpll_div2", "gpll", 0, 224 RV1126B_CLKSEL_CON(4), 0, 5, DFLAGS, 225 RV1126B_CLKGATE_CON(0), 9, GFLAGS), 226 MUX(CLK_CM_FRAC0_SRC, "clk_cm_frac0_src", mux_24m_gpll_aupll_cpll_p, 0, 227 RV1126B_CLKSEL_CON(10), 0, 2, MFLAGS), 228 COMPOSITE_FRAC(CLK_CM_FRAC0, "clk_cm_frac0", "clk_cm_frac0_src", 0, 229 RV1126B_CLKSEL_CON(25), 0, 230 RV1126B_CLKGATE_CON(1), 0, GFLAGS), 231 MUX(CLK_CM_FRAC1_SRC, "clk_cm_frac1_src", mux_24m_gpll_aupll_cpll_p, 0, 232 RV1126B_CLKSEL_CON(10), 2, 2, MFLAGS), 233 COMPOSITE_FRAC(CLK_CM_FRAC1, "clk_cm_frac1", "clk_cm_frac1_src", 0, 234 RV1126B_CLKSEL_CON(26), 0, 235 RV1126B_CLKGATE_CON(1), 1, GFLAGS), 236 MUX(CLK_CM_FRAC2_SRC, "clk_cm_frac2_src", mux_24m_gpll_aupll_cpll_p, 0, 237 RV1126B_CLKSEL_CON(10), 4, 2, MFLAGS), 238 COMPOSITE_FRAC(CLK_CM_FRAC2, "clk_cm_frac2", "clk_cm_frac2_src", 0, 239 RV1126B_CLKSEL_CON(27), 0, 240 RV1126B_CLKGATE_CON(1), 2, GFLAGS), 241 MUX(CLK_UART_FRAC0_SRC, "clk_uart_frac0_src", mux_24m_gpll_cpll_p, 0, 242 RV1126B_CLKSEL_CON(10), 6, 2, MFLAGS), 243 COMPOSITE_FRAC(CLK_UART_FRAC0, "clk_uart_frac0", "clk_uart_frac0_src", 0, 244 RV1126B_CLKSEL_CON(28), 0, 245 RV1126B_CLKGATE_CON(1), 3, GFLAGS), 246 MUX(CLK_UART_FRAC1_SRC, "clk_uart_frac1_src", mux_24m_gpll_cpll_p, 0, 247 RV1126B_CLKSEL_CON(10), 8, 2, MFLAGS), 248 COMPOSITE_FRAC(CLK_UART_FRAC1, "clk_uart_frac1", "clk_uart_frac1_src", 0, 249 RV1126B_CLKSEL_CON(29), 0, 250 RV1126B_CLKGATE_CON(1), 4, GFLAGS), 251 MUX(CLK_AUDIO_FRAC0_SRC, "clk_audio_frac0_src", mux_24m_gpll_aupll_p, 0, 252 RV1126B_CLKSEL_CON(10), 10, 2, MFLAGS), 253 COMPOSITE_FRAC(CLK_AUDIO_FRAC0, "clk_audio_frac0", "clk_audio_frac0_src", 0, 254 RV1126B_CLKSEL_CON(30), 0, 255 RV1126B_CLKGATE_CON(1), 5, GFLAGS), 256 MUX(CLK_AUDIO_FRAC1_SRC, "clk_audio_frac1_src", mux_24m_gpll_aupll_p, 0, 257 RV1126B_CLKSEL_CON(10), 12, 2, MFLAGS), 258 COMPOSITE_FRAC(CLK_AUDIO_FRAC1, "clk_audio_frac1", "clk_audio_frac1_src", 0, 259 RV1126B_CLKSEL_CON(31), 0, 260 RV1126B_CLKGATE_CON(1), 6, GFLAGS), 261 COMPOSITE(CLK_AUDIO_INT0, "clk_audio_int0", mux_24m_gpll_aupll_p, 0, 262 RV1126B_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, 263 RV1126B_CLKGATE_CON(1), 7, GFLAGS), 264 COMPOSITE(CLK_AUDIO_INT1, "clk_audio_int1", mux_24m_gpll_aupll_p, 0, 265 RV1126B_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS, 266 RV1126B_CLKGATE_CON(1), 8, GFLAGS), 267 COMPOSITE(SCLK_UART0_SRC, "sclk_uart0_src", mux_sclk_uart_src_p, 0, 268 RV1126B_CLKSEL_CON(12), 5, 3, MFLAGS, 0, 5, DFLAGS, 269 RV1126B_CLKGATE_CON(1), 9, GFLAGS), 270 COMPOSITE(SCLK_UART1, "sclk_uart1", mux_sclk_uart_src_p, 0, 271 RV1126B_CLKSEL_CON(12), 13, 3, MFLAGS, 8, 5, DFLAGS, 272 RV1126B_CLKGATE_CON(1), 10, GFLAGS), 273 COMPOSITE(SCLK_UART2, "sclk_uart2", mux_sclk_uart_src_p, 0, 274 RV1126B_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, 275 RV1126B_CLKGATE_CON(1), 11, GFLAGS), 276 COMPOSITE(SCLK_UART3, "sclk_uart3", mux_sclk_uart_src_p, 0, 277 RV1126B_CLKSEL_CON(13), 13, 3, MFLAGS, 8, 5, DFLAGS, 278 RV1126B_CLKGATE_CON(1), 12, GFLAGS), 279 COMPOSITE(SCLK_UART4, "sclk_uart4", mux_sclk_uart_src_p, 0, 280 RV1126B_CLKSEL_CON(14), 5, 3, MFLAGS, 0, 5, DFLAGS, 281 RV1126B_CLKGATE_CON(1), 13, GFLAGS), 282 COMPOSITE(SCLK_UART5, "sclk_uart5", mux_sclk_uart_src_p, 0, 283 RV1126B_CLKSEL_CON(14), 13, 3, MFLAGS, 8, 5, DFLAGS, 284 RV1126B_CLKGATE_CON(1), 14, GFLAGS), 285 COMPOSITE(SCLK_UART6, "sclk_uart6", mux_sclk_uart_src_p, 0, 286 RV1126B_CLKSEL_CON(15), 5, 3, MFLAGS, 0, 5, DFLAGS, 287 RV1126B_CLKGATE_CON(2), 0, GFLAGS), 288 COMPOSITE(SCLK_UART7, "sclk_uart7", mux_sclk_uart_src_p, 0, 289 RV1126B_CLKSEL_CON(15), 13, 3, MFLAGS, 8, 5, DFLAGS, 290 RV1126B_CLKGATE_CON(2), 1, GFLAGS), 291 COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai0_src_p, 0, 292 RV1126B_CLKSEL_CON(16), 8, 4, MFLAGS, 0, 8, DFLAGS, 293 RV1126B_CLKGATE_CON(2), 2, GFLAGS), 294 COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai1_src_p, 0, 295 RV1126B_CLKSEL_CON(17), 8, 4, MFLAGS, 0, 8, DFLAGS, 296 RV1126B_CLKGATE_CON(2), 3, GFLAGS), 297 COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai2_src_p, 0, 298 RV1126B_CLKSEL_CON(18), 8, 4, MFLAGS, 0, 8, DFLAGS, 299 RV1126B_CLKGATE_CON(2), 4, GFLAGS), 300 COMPOSITE(MCLK_PDM, "mclk_pdm", mux_sai_src_p, 0, 301 RV1126B_CLKSEL_CON(19), 6, 4, MFLAGS, 0, 5, DFLAGS, 302 RV1126B_CLKGATE_CON(2), 5, GFLAGS), 303 COMPOSITE_NOGATE(0, "clkout_pdm_src", mux_sai_src_p, 0, 304 RV1126B_CLKSEL_CON(20), 8, 4, MFLAGS, 0, 8, DFLAGS), 305 GATE(CLKOUT_PDM, "clkout_pdm", "clkout_pdm_src", 0, 306 RV1126B_CLKGATE_CON(2), 6, GFLAGS), 307 COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mux_sai_src_p, 0, 308 RV1126B_CLKSEL_CON(16), 12, 4, MFLAGS, 309 RV1126B_CLKGATE_CON(2), 7, GFLAGS), 310 COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mux_sai_src_p, 0, 311 RV1126B_CLKSEL_CON(17), 12, 4, MFLAGS, 312 RV1126B_CLKGATE_CON(2), 8, GFLAGS), 313 COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mux_sai_src_p, 0, 314 RV1126B_CLKSEL_CON(18), 12, 4, MFLAGS, 315 RV1126B_CLKGATE_CON(2), 9, GFLAGS), 316 COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mux_sai_src_p, 0, 317 RV1126B_CLKSEL_CON(19), 12, 4, MFLAGS, 318 RV1126B_CLKGATE_CON(2), 10, GFLAGS), 319 COMPOSITE(CLK_ASRC0, "clk_asrc0", mux_gpll_aupll_p, 0, 320 RV1126B_CLKSEL_CON(21), 6, 1, MFLAGS, 0, 5, DFLAGS, 321 RV1126B_CLKGATE_CON(2), 11, GFLAGS), 322 COMPOSITE(CLK_ASRC1, "clk_asrc1", mux_gpll_aupll_p, 0, 323 RV1126B_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS, 324 RV1126B_CLKGATE_CON(2), 12, GFLAGS), 325 COMPOSITE_NOMUX(CLK_CORE_PLL, "clk_core_pll", "gpll", CLK_IS_CRITICAL, 326 RV1126B_CLKSEL_CON(60), 0, 3, DFLAGS, 327 RV1126B_CLKGATE_CON(5), 0, GFLAGS), 328 COMPOSITE_NOMUX(CLK_NPU_PLL, "clk_npu_pll", "gpll", CLK_IS_CRITICAL, 329 RV1126B_CLKSEL_CON(60), 6, 3, DFLAGS, 330 RV1126B_CLKGATE_CON(5), 1, GFLAGS), 331 COMPOSITE(CLK_VEPU_PLL, "clk_vepu_pll", mux_gpll_aupll_cpll_p, 0, 332 RV1126B_CLKSEL_CON(61), 4, 2, MFLAGS, 0, 3, DFLAGS, 333 RV1126B_CLKGATE_CON(5), 2, GFLAGS), 334 COMPOSITE(CLK_ISP_PLL, "clk_isp_pll", mux_gpll_aupll_cpll_p, 0, 335 RV1126B_CLKSEL_CON(61), 10, 2, MFLAGS, 6, 4, DFLAGS, 336 RV1126B_CLKGATE_CON(5), 3, GFLAGS), 337 COMPOSITE(CLK_SARADC0_SRC, "clk_saradc0_src", mux_200m_24m_p, 0, 338 RV1126B_CLKSEL_CON(63), 12, 1, MFLAGS, 0, 3, DFLAGS, 339 RV1126B_CLKGATE_CON(5), 6, GFLAGS), 340 COMPOSITE(CLK_SARADC1_SRC, "clk_saradc1_src", mux_200m_24m_p, 0, 341 RV1126B_CLKSEL_CON(63), 13, 1, MFLAGS, 4, 3, DFLAGS, 342 RV1126B_CLKGATE_CON(5), 7, GFLAGS), 343 COMPOSITE(CLK_SARADC2_SRC, "clk_saradc2_src", mux_200m_24m_p, 0, 344 RV1126B_CLKSEL_CON(63), 14, 1, MFLAGS, 8, 3, DFLAGS, 345 RV1126B_CLKGATE_CON(5), 8, GFLAGS), 346 GATE(HCLK_RKNN, "hclk_rknn", "clk_gpll_div8", CLK_IS_CRITICAL, 347 RV1126B_CLKGATE_CON(5), 10, GFLAGS), 348 GATE(PCLK_NPU_ROOT, "pclk_npu_root", "clk_cpll_div10", CLK_IS_CRITICAL, 349 RV1126B_CLKGATE_CON(5), 11, GFLAGS), 350 COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL, 351 RV1126B_CLKSEL_CON(40), 0, 2, MFLAGS, 352 RV1126B_CLKGATE_CON(5), 12, GFLAGS), 353 GATE(HCLK_VEPU_ROOT, "hclk_vepu_root", "clk_gpll_div8", CLK_IS_CRITICAL, 354 RV1126B_CLKGATE_CON(5), 13, GFLAGS), 355 GATE(PCLK_VEPU_ROOT, "pclk_vepu_root", "clk_cpll_div10", 0, 356 RV1126B_CLKGATE_CON(5), 14, GFLAGS), 357 COMPOSITE(CLK_CORE_RGA_SRC, "clk_core_rga_src", mux_gpll_cpll_p, 0, 358 RV1126B_CLKSEL_CON(40), 5, 1, MFLAGS, 2, 3, DFLAGS, 359 RV1126B_CLKGATE_CON(6), 0, GFLAGS), 360 COMPOSITE_NODIV(ACLK_GMAC_ROOT, "aclk_gmac_root", mux_300m_200m_p, 0, 361 RV1126B_CLKSEL_CON(40), 6, 1, MFLAGS, 362 RV1126B_CLKGATE_CON(6), 1, GFLAGS), 363 COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_500m_400m_300m_p, CLK_IS_CRITICAL, 364 RV1126B_CLKSEL_CON(40), 7, 2, MFLAGS, 365 RV1126B_CLKGATE_CON(6), 2, GFLAGS), 366 GATE(HCLK_VI_ROOT, "hclk_vi_root", "clk_gpll_div8", CLK_IS_CRITICAL, 367 RV1126B_CLKGATE_CON(6), 3, GFLAGS), 368 GATE(PCLK_VI_ROOT, "pclk_vi_root", "clk_cpll_div10", CLK_IS_CRITICAL, 369 RV1126B_CLKGATE_CON(6), 4, GFLAGS), 370 COMPOSITE_NODIV(DCLK_VICAP_ROOT, "dclk_vicap_root", mux_333m_200m_p, 0, 371 RV1126B_CLKSEL_CON(42), 5, 1, MFLAGS, 372 RV1126B_CLKGATE_CON(6), 5, GFLAGS), 373 COMPOSITE(CLK_SYS_DSMC_ROOT, "clk_sys_dsmc_root", mux_24m_gpll_cpll_p, 0, 374 RV1126B_CLKSEL_CON(40), 14, 2, MFLAGS, 9, 5, DFLAGS, 375 RV1126B_CLKGATE_CON(6), 6, GFLAGS), 376 COMPOSITE(ACLK_VDO_ROOT, "aclk_vdo_root", mux_gpll_cpll_p, CLK_IS_CRITICAL, 377 RV1126B_CLKSEL_CON(42), 4, 1, MFLAGS, 0, 4, DFLAGS, 378 RV1126B_CLKGATE_CON(6), 7, GFLAGS), 379 COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", mux_gpll_cpll_p, 0, 380 RV1126B_CLKSEL_CON(42), 10, 1, MFLAGS, 6, 4, DFLAGS, 381 RV1126B_CLKGATE_CON(6), 8, GFLAGS), 382 GATE(HCLK_VDO_ROOT, "hclk_vdo_root", "clk_gpll_div8", CLK_IS_CRITICAL, 383 RV1126B_CLKGATE_CON(6), 9, GFLAGS), 384 GATE(PCLK_VDO_ROOT, "pclk_vdo_root", "clk_cpll_div10", CLK_IS_CRITICAL, 385 RV1126B_CLKGATE_CON(6), 10, GFLAGS), 386 COMPOSITE(DCLK_VOP, "dclk_vop", mux_gpll_cpll_p, 0, 387 RV1126B_CLKSEL_CON(43), 8, 1, MFLAGS, 0, 8, DFLAGS, 388 RV1126B_CLKGATE_CON(6), 12, GFLAGS), 389 COMPOSITE(DCLK_OOC_SRC, "dclk_ooc_src", mux_gpll_cpll_p, 0, 390 RV1126B_CLKSEL_CON(62), 7, 1, MFLAGS, 8, 8, DFLAGS, 391 RV1126B_CLKGATE_CON(6), 13, GFLAGS), 392 GATE(DCLK_DECOM_SRC, "dclk_decom_src", "clk_gpll_div3", 0, 393 RV1126B_CLKGATE_CON(6), 14, GFLAGS), 394 GATE(PCLK_DDR_ROOT, "pclk_ddr_root", "clk_cpll_div10", 0, 395 RV1126B_CLKGATE_CON(7), 0, GFLAGS), 396 COMPOSITE(ACLK_SYSMEM, "aclk_sysmem", mux_gpll_cpll_p, CLK_IS_CRITICAL, 397 RV1126B_CLKSEL_CON(44), 3, 1, MFLAGS, 0, 3, DFLAGS, 398 RV1126B_CLKGATE_CON(7), 1, GFLAGS), 399 COMPOSITE_NODIV(ACLK_TOP_ROOT, "aclk_top_root", mux_600m_400m_200m_p, CLK_IS_CRITICAL, 400 RV1126B_CLKSEL_CON(44), 6, 2, MFLAGS, 401 RV1126B_CLKGATE_CON(7), 3, GFLAGS), 402 COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_400m_300m_200m_p, CLK_IS_CRITICAL, 403 RV1126B_CLKSEL_CON(44), 8, 2, MFLAGS, 404 RV1126B_CLKGATE_CON(7), 4, GFLAGS), 405 COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_p, CLK_IS_CRITICAL, 406 RV1126B_CLKSEL_CON(44), 10, 1, MFLAGS, 407 RV1126B_CLKGATE_CON(7), 5, GFLAGS), 408 GATE(PCLK_BUS_ROOT, "pclk_bus_root", "clk_cpll_div10", CLK_IS_CRITICAL, 409 RV1126B_CLKGATE_CON(7), 6, GFLAGS), 410 COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", mux_gpll_cpll_24m_p, 0, 411 RV1126B_CLKSEL_CON(45), 8, 2, MFLAGS, 0, 8, DFLAGS, 412 RV1126B_CLKGATE_CON(7), 7, GFLAGS), 413 COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", mux_gpll_cpll_24m_p, 0, 414 RV1126B_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 8, DFLAGS, 415 RV1126B_CLKGATE_CON(7), 8, GFLAGS), 416 COMPOSITE(CCLK_EMMC, "cclk_emmc", mux_gpll_cpll_24m_p, 0, 417 RV1126B_CLKSEL_CON(47), 8, 2, MFLAGS, 0, 8, DFLAGS, 418 RV1126B_CLKGATE_CON(7), 9, GFLAGS), 419 COMPOSITE(SCLK_2X_FSPI0, "sclk_2x_fspi0", mux_gpll_cpll_24m_p, 0, 420 RV1126B_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 8, DFLAGS, 421 RV1126B_CLKGATE_CON(7), 10, GFLAGS), 422 COMPOSITE(CLK_GMAC_PTP_REF_SRC, "clk_gmac_ptp_ref_src", mux_cpll_24m_p, 0, 423 RV1126B_CLKSEL_CON(45), 10, 1, MFLAGS, 11, 5, DFLAGS, 424 RV1126B_CLKGATE_CON(7), 11, GFLAGS), 425 GATE(CLK_GMAC_125M, "clk_gmac_125m", "clk_cpll_div8", 0, 426 RV1126B_CLKGATE_CON(7), 12, GFLAGS), 427 COMPOSITE_NODIV(CLK_TIMER_ROOT, "clk_timer_root", mux_100m_24m_p, 0, 428 RV1126B_CLKSEL_CON(46), 11, 1, MFLAGS, 429 RV1126B_CLKGATE_CON(7), 13, GFLAGS), 430 COMPOSITE_NODIV(TCLK_WDT_NS_SRC, "tclk_wdt_ns_src", mux_100m_24m_p, 0, 431 RV1126B_CLKSEL_CON(46), 12, 1, MFLAGS, 432 RV1126B_CLKGATE_CON(8), 0, GFLAGS), 433 COMPOSITE_NODIV(TCLK_WDT_S_SRC, "tclk_wdt_s_src", mux_100m_24m_p, 0, 434 RV1126B_CLKSEL_CON(46), 13, 1, MFLAGS, 435 RV1126B_CLKGATE_CON(8), 1, GFLAGS), 436 COMPOSITE_NODIV(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", mux_100m_24m_p, 0, 437 RV1126B_CLKSEL_CON(46), 14, 1, MFLAGS, 438 RV1126B_CLKGATE_CON(8), 2, GFLAGS), 439 COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_24m_p, 0, 440 RV1126B_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, 441 RV1126B_CLKGATE_CON(8), 4, GFLAGS), 442 COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_24m_p, 0, 443 RV1126B_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, 444 RV1126B_CLKGATE_CON(8), 5, GFLAGS), 445 COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_24m_p, CLK_IS_CRITICAL, 446 RV1126B_CLKSEL_CON(47), 12, 1, MFLAGS, 447 RV1126B_CLKGATE_CON(8), 6, GFLAGS), 448 COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_200m_24m_p, CLK_IS_CRITICAL, 449 RV1126B_CLKSEL_CON(47), 13, 1, MFLAGS, 450 RV1126B_CLKGATE_CON(8), 7, GFLAGS), 451 COMPOSITE_NODIV(CLK_I2C_BUS_SRC, "clk_i2c_bus_src", mux_200m_24m_p, 0, 452 RV1126B_CLKSEL_CON(50), 1, 1, MFLAGS, 453 RV1126B_CLKGATE_CON(8), 9, GFLAGS), 454 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, 455 RV1126B_CLKSEL_CON(50), 2, 2, MFLAGS, 456 RV1126B_CLKGATE_CON(8), 10, GFLAGS), 457 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, 458 RV1126B_CLKSEL_CON(50), 4, 2, MFLAGS, 459 RV1126B_CLKGATE_CON(8), 11, GFLAGS), 460 GATE(BUSCLK_PMU_SRC, "busclk_pmu_src", "clk_cpll_div10", CLK_IS_CRITICAL, 461 RV1126B_CLKGATE_CON(8), 12, GFLAGS), 462 COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_24m_p, 0, 463 RV1126B_CLKSEL_CON(50), 8, 1, MFLAGS, 464 RV1126B_CLKGATE_CON(9), 0, GFLAGS), 465 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_24m_p, 0, 466 RV1126B_CLKSEL_CON(50), 10, 1, MFLAGS, 467 RV1126B_CLKGATE_CON(9), 2, GFLAGS), 468 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_24m_p, 0, 469 RV1126B_CLKSEL_CON(50), 11, 1, MFLAGS, 470 RV1126B_CLKGATE_CON(9), 3, GFLAGS), 471 COMPOSITE_NODIV(CLK_PKA_RKCE_SRC, "clk_pka_rkce_src", mux_300m_200m_p, CLK_IS_CRITICAL, 472 RV1126B_CLKSEL_CON(50), 12, 1, MFLAGS, 473 RV1126B_CLKGATE_CON(9), 4, GFLAGS), 474 COMPOSITE_NODIV(ACLK_RKCE_SRC, "aclk_rkce_src", mux_200m_24m_p, CLK_IS_CRITICAL, 475 RV1126B_CLKSEL_CON(50), 13, 1, MFLAGS, 476 RV1126B_CLKGATE_CON(9), 5, GFLAGS), 477 COMPOSITE_NODIV(ACLK_VCP_ROOT, "aclk_vcp_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL, 478 RV1126B_CLKSEL_CON(48), 12, 2, MFLAGS, 479 RV1126B_CLKGATE_CON(9), 6, GFLAGS), 480 GATE(HCLK_VCP_ROOT, "hclk_vcp_root", "clk_gpll_div8", CLK_IS_CRITICAL, 481 RV1126B_CLKGATE_CON(9), 7, GFLAGS), 482 GATE(PCLK_VCP_ROOT, "pclk_vcp_root", "clk_cpll_div10", CLK_IS_CRITICAL, 483 RV1126B_CLKGATE_CON(9), 8, GFLAGS), 484 COMPOSITE(CLK_CORE_FEC_SRC, "clk_core_fec_src", mux_gpll_cpll_p, 0, 485 RV1126B_CLKSEL_CON(51), 3, 1, MFLAGS, 0, 3, DFLAGS, 486 RV1126B_CLKGATE_CON(9), 9, GFLAGS), 487 GATE(CLK_50M_GMAC_IOBUF_VI, "clk_50m_gmac_iobuf_vi", "clk_cpll_div20", 0, 488 RV1126B_CLKGATE_CON(9), 11, GFLAGS), 489 GATE(PCLK_TOP_ROOT, "pclk_top_root", "clk_cpll_div10", CLK_IS_CRITICAL, 490 RV1126B_CLKGATE_CON(15), 0, GFLAGS), 491 COMPOSITE(CLK_MIPI0_OUT2IO, "clk_mipi0_out2io", mux_600m_24m_p, 0, 492 RV1126B_CLKSEL_CON(67), 11, 1, MFLAGS, 0, 5, DFLAGS, 493 RV1126B_CLKGATE_CON(15), 3, GFLAGS), 494 COMPOSITE(CLK_MIPI1_OUT2IO, "clk_mipi1_out2io", mux_600m_24m_p, 0, 495 RV1126B_CLKSEL_CON(67), 12, 1, MFLAGS, 6, 5, DFLAGS, 496 RV1126B_CLKGATE_CON(15), 4, GFLAGS), 497 COMPOSITE(CLK_MIPI2_OUT2IO, "clk_mipi2_out2io", mux_600m_24m_p, 0, 498 RV1126B_CLKSEL_CON(68), 11, 1, MFLAGS, 0, 5, DFLAGS, 499 RV1126B_CLKGATE_CON(15), 5, GFLAGS), 500 COMPOSITE(CLK_MIPI3_OUT2IO, "clk_mipi3_out2io", mux_600m_24m_p, 0, 501 RV1126B_CLKSEL_CON(68), 12, 1, MFLAGS, 6, 5, DFLAGS, 502 RV1126B_CLKGATE_CON(15), 6, GFLAGS), 503 COMPOSITE(CLK_CIF_OUT2IO, "clk_cif_out2io", mux_600m_24m_p, 0, 504 RV1126B_CLKSEL_CON(69), 5, 1, MFLAGS, 0, 5, DFLAGS, 505 RV1126B_CLKGATE_CON(15), 7, GFLAGS), 506 COMPOSITE(CLK_MAC_OUT2IO, "clk_mac_out2io", mux_gpll_cpll_24m_p, 0, 507 RV1126B_CLKSEL_CON(69), 6, 2, MFLAGS, 8, 7, DFLAGS, 508 RV1126B_CLKGATE_CON(15), 8, GFLAGS), 509 COMPOSITE_NOMUX(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", "mclk_sai0", CLK_SET_RATE_PARENT, 510 RV1126B_CLKSEL_CON(70), 0, 4, DFLAGS, 511 RV1126B_CLKGATE_CON(15), 9, GFLAGS), 512 COMPOSITE_NOMUX(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", "mclk_sai1", CLK_SET_RATE_PARENT, 513 RV1126B_CLKSEL_CON(70), 5, 4, DFLAGS, 514 RV1126B_CLKGATE_CON(15), 10, GFLAGS), 515 COMPOSITE_NOMUX(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", "mclk_sai2", CLK_SET_RATE_PARENT, 516 RV1126B_CLKSEL_CON(70), 10, 4, DFLAGS, 517 RV1126B_CLKGATE_CON(15), 11, GFLAGS), 518 519 /* pd _npu */ 520 MUX(ACLK_RKNN, "aclk_rknn", aclk_npu_root_p, CLK_SET_RATE_PARENT, 521 RV1126B_NPUCLKSEL_CON(0), 1, 1, MFLAGS), 522 523 /* pd_vepu */ 524 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vepu_root", 0, 525 RV1126B_VEPUCLKGATE_CON(0), 7, GFLAGS), 526 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, 527 RV1126B_VEPUCLKGATE_CON(0), 8, GFLAGS), 528 GATE(PCLK_IOC_VCCIO3, "pclk_ioc_vccio3", "pclk_vepu_root", CLK_IS_CRITICAL, 529 RV1126B_VEPUCLKGATE_CON(0), 9, GFLAGS), 530 GATE(PCLK_SARADC0, "pclk_saradc0", "pclk_vepu_root", 0, 531 RV1126B_VEPUCLKGATE_CON(0), 10, GFLAGS), 532 MUX(CLK_SARADC0, "clk_saradc0", clk_saradc0_p, CLK_SET_RATE_PARENT, 533 RV1126B_VEPUCLKSEL_CON(0), 2, 1, MFLAGS), 534 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_vepu_root", 0, 535 RV1126B_VEPUCLKGATE_CON(0), 12, GFLAGS), 536 GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0, 537 RV1126B_VEPUCLKGATE_CON(1), 1, GFLAGS), 538 GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0, 539 RV1126B_VEPUCLKGATE_CON(1), 2, GFLAGS), 540 COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", clk_core_vepu_p, CLK_SET_RATE_PARENT, 541 RV1126B_VEPUCLKSEL_CON(0), 1, 1, MFLAGS, 542 RV1126B_VEPUCLKGATE_CON(1), 3, GFLAGS), 543 544 /* pd_vcp */ 545 GATE(HCLK_FEC, "hclk_fec", "hclk_vcp_root", 0, 546 RV1126B_VCPCLKGATE_CON(1), 0, GFLAGS), 547 GATE(ACLK_FEC, "aclk_fec", "aclk_vcp_root", 0, 548 RV1126B_VCPCLKGATE_CON(1), 1, GFLAGS), 549 COMPOSITE_NODIV(CLK_CORE_FEC, "clk_core_fec", clk_core_fec_p, CLK_SET_RATE_PARENT, 550 RV1126B_VCPCLKSEL_CON(0), 13, 1, MFLAGS, 551 RV1126B_VCPCLKGATE_CON(1), 2, GFLAGS), 552 GATE(HCLK_AVSP, "hclk_avsp", "hclk_vcp_root", 0, 553 RV1126B_VCPCLKGATE_CON(1), 3, GFLAGS), 554 GATE(ACLK_AVSP, "aclk_avsp", "aclk_vcp_root", 0, 555 RV1126B_VCPCLKGATE_CON(1), 4, GFLAGS), 556 GATE(HCLK_AISP, "hclk_aisp", "hclk_vcp_root", 0, 557 RV1126B_VCPCLKGATE_CON(0), 11, GFLAGS), 558 GATE(ACLK_AISP, "aclk_aisp", "aclk_vcp_root", 0, 559 RV1126B_VCPCLKGATE_CON(0), 12, GFLAGS), 560 COMPOSITE_NODIV(CLK_CORE_AISP, "clk_core_aisp", clk_core_aisp_p, CLK_SET_RATE_PARENT, 561 RV1126B_VCPCLKSEL_CON(0), 15, 1, MFLAGS, 562 RV1126B_VCPCLKGATE_CON(0), 13, GFLAGS), 563 564 /* pd_vi */ 565 MUX(CLK_CORE_ISP_ROOT, "clk_core_isp_root", clk_core_isp_root_p, CLK_SET_RATE_PARENT, 566 RV1126B_VICLKSEL_CON(0), 1, 1, MFLAGS), 567 GATE(PCLK_DSMC, "pclk_dsmc", "pclk_vi_root", 0, 568 RV1126B_VICLKGATE_CON(0), 8, GFLAGS), 569 GATE(ACLK_DSMC, "aclk_dsmc", "hclk_vi_root", 0, 570 RV1126B_VICLKGATE_CON(0), 9, GFLAGS), 571 GATE(HCLK_CAN0, "hclk_can0", "hclk_vi_root", 0, 572 RV1126B_VICLKGATE_CON(0), 10, GFLAGS), 573 GATE(HCLK_CAN1, "hclk_can1", "hclk_vi_root", 0, 574 RV1126B_VICLKGATE_CON(0), 11, GFLAGS), 575 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vi_root", 0, 576 RV1126B_VICLKGATE_CON(1), 0, GFLAGS), 577 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, 578 RV1126B_VICLKGATE_CON(1), 1, GFLAGS), 579 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_vi_root", 0, 580 RV1126B_VICLKGATE_CON(1), 2, GFLAGS), 581 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, 582 RV1126B_VICLKGATE_CON(1), 3, GFLAGS), 583 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_vi_root", 0, 584 RV1126B_VICLKGATE_CON(1), 4, GFLAGS), 585 GATE(DBCLK_GPIO5, "dbclk_gpio5", "xin24m", 0, 586 RV1126B_VICLKGATE_CON(1), 5, GFLAGS), 587 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_vi_root", 0, 588 RV1126B_VICLKGATE_CON(1), 6, GFLAGS), 589 GATE(DBCLK_GPIO6, "dbclk_gpio6", "xin24m", 0, 590 RV1126B_VICLKGATE_CON(1), 7, GFLAGS), 591 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_vi_root", 0, 592 RV1126B_VICLKGATE_CON(1), 8, GFLAGS), 593 GATE(DBCLK_GPIO7, "dbclk_gpio7", "xin24m", 0, 594 RV1126B_VICLKGATE_CON(1), 9, GFLAGS), 595 GATE(PCLK_IOC_VCCIO2, "pclk_ioc_vccio2", "pclk_vi_root", CLK_IS_CRITICAL, 596 RV1126B_VICLKGATE_CON(1), 10, GFLAGS), 597 GATE(PCLK_IOC_VCCIO4, "pclk_ioc_vccio4", "pclk_vi_root", CLK_IS_CRITICAL, 598 RV1126B_VICLKGATE_CON(1), 11, GFLAGS), 599 GATE(PCLK_IOC_VCCIO5, "pclk_ioc_vccio5", "pclk_vi_root", CLK_IS_CRITICAL, 600 RV1126B_VICLKGATE_CON(1), 12, GFLAGS), 601 GATE(PCLK_IOC_VCCIO6, "pclk_ioc_vccio6", "pclk_vi_root", CLK_IS_CRITICAL, 602 RV1126B_VICLKGATE_CON(1), 13, GFLAGS), 603 GATE(PCLK_IOC_VCCIO7, "pclk_ioc_vccio7", "pclk_vi_root", CLK_IS_CRITICAL, 604 RV1126B_VICLKGATE_CON(1), 14, GFLAGS), 605 GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0, 606 RV1126B_VICLKGATE_CON(2), 0, GFLAGS), 607 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0, 608 RV1126B_VICLKGATE_CON(2), 1, GFLAGS), 609 GATE(CLK_CORE_ISP, "clk_core_isp", "clk_core_isp_root", 0, 610 RV1126B_VICLKGATE_CON(2), 2, GFLAGS), 611 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, 612 RV1126B_VICLKGATE_CON(2), 3, GFLAGS), 613 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, 614 RV1126B_VICLKGATE_CON(2), 4, GFLAGS), 615 GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap_root", 0, 616 RV1126B_VICLKGATE_CON(2), 5, GFLAGS), 617 GATE(ISP0CLK_VICAP, "isp0clk_vicap", "clk_core_isp_root", 0, 618 RV1126B_VICLKGATE_CON(2), 6, GFLAGS), 619 GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0, 620 RV1126B_VICLKGATE_CON(2), 7, GFLAGS), 621 GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0, 622 RV1126B_VICLKGATE_CON(2), 8, GFLAGS), 623 GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_core_isp_root", 0, 624 RV1126B_VICLKGATE_CON(2), 9, GFLAGS), 625 GATE(HCLK_VPSL, "hclk_vpsl", "hclk_vi_root", 0, 626 RV1126B_VICLKGATE_CON(2), 10, GFLAGS), 627 GATE(ACLK_VPSL, "aclk_vpsl", "aclk_vi_root", 0, 628 RV1126B_VICLKGATE_CON(2), 11, GFLAGS), 629 GATE(CLK_CORE_VPSL, "clk_core_vpsl", "clk_core_isp_root", 0, 630 RV1126B_VICLKGATE_CON(2), 12, GFLAGS), 631 GATE(PCLK_CSI2HOST0, "pclk_csi2host0", "pclk_vi_root", 0, 632 RV1126B_VICLKGATE_CON(3), 0, GFLAGS), 633 GATE(DCLK_CSI2HOST0, "dclk_csi2host0", "dclk_vicap_root", 0, 634 RV1126B_VICLKGATE_CON(3), 1, GFLAGS), 635 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi_root", 0, 636 RV1126B_VICLKGATE_CON(3), 2, GFLAGS), 637 GATE(DCLK_CSI2HOST1, "dclk_csi2host1", "dclk_vicap_root", 0, 638 RV1126B_VICLKGATE_CON(3), 3, GFLAGS), 639 GATE(PCLK_CSI2HOST2, "pclk_csi2host2", "pclk_vi_root", 0, 640 RV1126B_VICLKGATE_CON(3), 4, GFLAGS), 641 GATE(DCLK_CSI2HOST2, "dclk_csi2host2", "dclk_vicap_root", 0, 642 RV1126B_VICLKGATE_CON(3), 5, GFLAGS), 643 GATE(PCLK_CSI2HOST3, "pclk_csi2host3", "pclk_vi_root", 0, 644 RV1126B_VICLKGATE_CON(3), 6, GFLAGS), 645 GATE(DCLK_CSI2HOST3, "dclk_csi2host3", "dclk_vicap_root", 0, 646 RV1126B_VICLKGATE_CON(3), 7, GFLAGS), 647 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vi_root", 0, 648 RV1126B_VICLKGATE_CON(3), 8, GFLAGS), 649 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_root", 0, 650 RV1126B_VICLKGATE_CON(3), 9, GFLAGS), 651 GATE(PCLK_GMAC, "pclk_gmac", "pclk_vi_root", 0, 652 RV1126B_VICLKGATE_CON(3), 10, GFLAGS), 653 MUX(CLK_GMAC_PTP_REF, "clk_gmac_ptp_ref", clk_gmac_ptp_ref_p, CLK_SET_RATE_PARENT, 654 RV1126B_VICLKSEL_CON(0), 14, 1, MFLAGS), 655 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi_root", 0, 656 RV1126B_VICLKGATE_CON(3), 11, GFLAGS), 657 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi_root", 0, 658 RV1126B_VICLKGATE_CON(3), 12, GFLAGS), 659 GATE(PCLK_MACPHY, "pclk_macphy", "pclk_vi_root", 0, 660 RV1126B_VICLKGATE_CON(3), 13, GFLAGS), 661 GATE(PCLK_SARADC1, "pclk_saradc1", "pclk_vi_root", 0, 662 RV1126B_VICLKGATE_CON(4), 0, GFLAGS), 663 MUX(CLK_SARADC1, "clk_saradc1", clk_saradc1_p, CLK_SET_RATE_PARENT, 664 RV1126B_VICLKSEL_CON(0), 2, 1, MFLAGS), 665 GATE(PCLK_SARADC2, "pclk_saradc2", "pclk_vi_root", 0, 666 RV1126B_VICLKGATE_CON(4), 2, GFLAGS), 667 MUX(CLK_SARADC2, "clk_saradc2", clk_saradc2_p, CLK_SET_RATE_PARENT, 668 RV1126B_VICLKSEL_CON(0), 3, 1, MFLAGS), 669 COMPOSITE_NODIV(CLK_MACPHY, "clk_macphy", clk_macphy_p, 0, 670 RV1126B_VICLKSEL_CON(1), 1, 1, MFLAGS, 671 RV1126B_VICLKGATE_CON(0), 12, GFLAGS), 672 673 /* pd_vdo */ 674 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_root", 0, 675 RV1126B_VDOCLKGATE_CON(0), 7, GFLAGS), 676 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdo_root", 0, 677 RV1126B_VDOCLKGATE_CON(0), 8, GFLAGS), 678 GATE(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", "aclk_rkvdec_root", 0, 679 RV1126B_VDOCLKGATE_CON(0), 9, GFLAGS), 680 GATE(ACLK_VOP, "aclk_vop", "aclk_vdo_root", 0, 681 RV1126B_VDOCLKGATE_CON(0), 10, GFLAGS), 682 GATE(HCLK_VOP, "hclk_vop", "hclk_vdo_root", 0, 683 RV1126B_VDOCLKGATE_CON(0), 11, GFLAGS), 684 GATE(ACLK_OOC, "aclk_ooc", "aclk_vdo_root", 0, 685 RV1126B_VDOCLKGATE_CON(0), 13, GFLAGS), 686 GATE(HCLK_OOC, "hclk_ooc", "hclk_vdo_root", 0, 687 RV1126B_VDOCLKGATE_CON(0), 14, GFLAGS), 688 GATE(HCLK_RKJPEG, "hclk_rkjpeg", "hclk_vdo_root", 0, 689 RV1126B_VDOCLKGATE_CON(1), 3, GFLAGS), 690 GATE(ACLK_RKJPEG, "aclk_rkjpeg", "aclk_vdo_root", 0, 691 RV1126B_VDOCLKGATE_CON(1), 4, GFLAGS), 692 GATE(ACLK_RKMMU_DECOM, "aclk_rkmmu_decom", "aclk_vdo_root", 0, 693 RV1126B_VDOCLKGATE_CON(1), 5, GFLAGS), 694 GATE(HCLK_RKMMU_DECOM, "hclk_rkmmu_decom", "hclk_vdo_root", 0, 695 RV1126B_VDOCLKGATE_CON(1), 6, GFLAGS), 696 GATE(DCLK_DECOM, "dclk_decom", "dclk_decom_src", 0, 697 RV1126B_VDOCLKGATE_CON(1), 8, GFLAGS), 698 GATE(ACLK_DECOM, "aclk_decom", "aclk_vdo_root", 0, 699 RV1126B_VDOCLKGATE_CON(1), 9, GFLAGS), 700 GATE(PCLK_DECOM, "pclk_decom", "pclk_vdo_root", 0, 701 RV1126B_VDOCLKGATE_CON(1), 10, GFLAGS), 702 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vdo_root", 0, 703 RV1126B_VDOCLKGATE_CON(1), 12, GFLAGS), 704 GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_vdo_root", 0, 705 RV1126B_VDOCLKGATE_CON(1), 13, GFLAGS), 706 707 /* pd_ddr */ 708 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL, 709 RV1126B_DDRCLKGATE_CON(0), 2, GFLAGS), 710 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IS_CRITICAL, 711 RV1126B_DDRCLKGATE_CON(0), 3, GFLAGS), 712 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0, 713 RV1126B_DDRCLKGATE_CON(0), 4, GFLAGS), 714 GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL, 715 RV1126B_DDRCLKGATE_CON(0), 5, GFLAGS), 716 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL, 717 RV1126B_DDRCLKGATE_CON(0), 8, GFLAGS), 718 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_ddr_root", CLK_IS_CRITICAL, 719 RV1126B_DDRCLKGATE_CON(0), 9, GFLAGS), 720 721 /* pd_pmu*/ 722 COMPOSITE_NODIV(CLK_RCOSC_SRC, "clk_rcosc_src", clk_rcosc_src_p, 0, 723 RV1126B_PMUCLKSEL_CON(1), 0, 3, MFLAGS, 724 RV1126B_PMUCLKGATE_CON(0), 0, GFLAGS), 725 COMPOSITE_NOGATE(BUSCLK_PMU_MUX, "busclk_pmu_mux", busclk_pmu_mux_p, 0, 726 RV1126B_PMUCLKSEL_CON(1), 3, 1, MFLAGS, 4, 2, DFLAGS), 727 GATE(BUSCLK_PMU_ROOT, "busclk_pmu_root", "busclk_pmu_mux", 0, 728 RV1126B_PMUCLKGATE_CON(0), 1, GFLAGS), 729 GATE(BUSCLK_PMU1_ROOT, "busclk_pmu1_root", "busclk_pmu_mux", CLK_IS_CRITICAL, 730 RV1126B_PMUCLKGATE_CON(3), 11, GFLAGS), 731 GATE(PCLK_PMU, "pclk_pmu", "busclk_pmu_root", CLK_IS_CRITICAL, 732 RV1126B_PMUCLKGATE_CON(0), 6, GFLAGS), 733 MUX(0, "xin_rc_src", clk_xin_rc_div_p, 0, 734 RV1126B_PMUCLKSEL_CON(2), 0, 1, MFLAGS), 735 COMPOSITE_FRACMUX_NOGATE(CLK_XIN_RC_DIV, "clk_xin_rc_div", "xin_rc_src", CLK_SET_RATE_PARENT, 736 RV1126B_PMUCLKSEL_CON(8), 0, 737 &rv1126b_rcdiv_pmu_fracmux), 738 GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "busclk_pmu_root", 0, 739 RV1126B_PMUCLKGATE_CON(0), 7, GFLAGS), 740 COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0, 741 RV1126B_PMUCLKSEL_CON(2), 4, 1, MFLAGS, 742 RV1126B_PMUCLKGATE_CON(0), 8, GFLAGS), 743 GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "busclk_pmu_root", CLK_IS_CRITICAL, 744 RV1126B_PMUCLKGATE_CON(0), 10, GFLAGS), 745 COMPOSITE(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", mux_cpll_24m_p, CLK_IS_CRITICAL, 746 RV1126B_PMUCLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, 747 RV1126B_PMUCLKGATE_CON(0), 11, GFLAGS), 748 GATE(CLK_PMU_32K_HP_TIMER, "clk_pmu_32k_hp_timer", "clk_32k", CLK_IS_CRITICAL, 749 RV1126B_PMUCLKGATE_CON(0), 13, GFLAGS), 750 GATE(PCLK_PWM1, "pclk_pwm1", "busclk_pmu_root", 0, 751 RV1126B_PMUCLKGATE_CON(1), 0, GFLAGS), 752 COMPOSITE(CLK_PWM1, "clk_pwm1", mux_24m_rcosc_buspmu_p, 0, 753 RV1126B_PMUCLKSEL_CON(2), 8, 2, MFLAGS, 6, 2, DFLAGS, 754 RV1126B_PMUCLKGATE_CON(1), 1, GFLAGS), 755 GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0, 756 RV1126B_PMUCLKGATE_CON(1), 2, GFLAGS), 757 GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_32k", 0, 758 RV1126B_PMUCLKGATE_CON(1), 3, GFLAGS), 759 GATE(PCLK_I2C2, "pclk_i2c2", "busclk_pmu_root", 0, 760 RV1126B_PMUCLKGATE_CON(1), 6, GFLAGS), 761 COMPOSITE(CLK_I2C2, "clk_i2c2", mux_24m_rcosc_buspmu_p, 0, 762 RV1126B_PMUCLKSEL_CON(2), 14, 2, MFLAGS, 12, 2, DFLAGS, 763 RV1126B_PMUCLKGATE_CON(1), 7, GFLAGS), 764 GATE(PCLK_UART0, "pclk_uart0", "busclk_pmu_root", 0, 765 RV1126B_PMUCLKGATE_CON(1), 8, GFLAGS), 766 COMPOSITE_NODIV(SCLK_UART0, "sclk_uart0", sclk_uart0_p, CLK_SET_RATE_PARENT, 767 RV1126B_PMUCLKSEL_CON(3), 0, 2, MFLAGS, 768 RV1126B_PMUCLKGATE_CON(1), 11, GFLAGS), 769 GATE(PCLK_RCOSC_CTRL, "pclk_rcosc_ctrl", "busclk_pmu_root", CLK_IS_CRITICAL, 770 RV1126B_PMUCLKGATE_CON(2), 0, GFLAGS), 771 COMPOSITE_NODIV(CLK_OSC_RCOSC_CTRL, "clk_osc_rcosc_ctrl", clk_osc_rcosc_ctrl_p, CLK_IS_CRITICAL, 772 RV1126B_PMUCLKSEL_CON(3), 2, 1, MFLAGS, 773 RV1126B_PMUCLKGATE_CON(2), 1, GFLAGS), 774 GATE(CLK_REF_RCOSC_CTRL, "clk_ref_rcosc_ctrl", "xin24m", CLK_IS_CRITICAL, 775 RV1126B_PMUCLKGATE_CON(2), 2, GFLAGS), 776 GATE(PCLK_IOC_PMUIO0, "pclk_ioc_pmuio0", "busclk_pmu_root", CLK_IS_CRITICAL, 777 RV1126B_PMUCLKGATE_CON(2), 3, GFLAGS), 778 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0, 779 RV1126B_PMUCLKGATE_CON(2), 6, GFLAGS), 780 GATE(CLK_PREROLL, "clk_preroll", "busclk_pmu_root", 0, 781 RV1126B_PMUCLKGATE_CON(2), 7, GFLAGS), 782 GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0, 783 RV1126B_PMUCLKGATE_CON(2), 8, GFLAGS), 784 GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "busclk_pmu_root", CLK_IS_CRITICAL, 785 RV1126B_PMUCLKGATE_CON(2), 9, GFLAGS), 786 GATE(PCLK_WDT_LPMCU, "pclk_wdt_lpmcu", "busclk_pmu_root", 0, 787 RV1126B_PMUCLKGATE_CON(3), 0, GFLAGS), 788 COMPOSITE_NODIV(TCLK_WDT_LPMCU, "tclk_wdt_lpmcu", mux_24m_rcosc_buspmu_32k_p, 0, 789 RV1126B_PMUCLKSEL_CON(3), 6, 2, MFLAGS, 790 RV1126B_PMUCLKGATE_CON(3), 1, GFLAGS), 791 GATE(CLK_LPMCU, "clk_lpmcu", "busclk_pmu_root", 0, 792 RV1126B_PMUCLKGATE_CON(3), 2, GFLAGS), 793 GATE(CLK_LPMCU_RTC, "clk_lpmcu_rtc", "xin24m", 0, 794 RV1126B_PMUCLKGATE_CON(3), 3, GFLAGS), 795 GATE(PCLK_LPMCU_MAILBOX, "pclk_lpmcu_mailbox", "busclk_pmu_root", 0, 796 RV1126B_PMUCLKGATE_CON(3), 4, GFLAGS), 797 798 /* pd_pmu1 */ 799 GATE(PCLK_SPI2AHB, "pclk_spi2ahb", "busclk_pmu_root", 0, 800 RV1126B_PMU1CLKGATE_CON(0), 0, GFLAGS), 801 GATE(HCLK_SPI2AHB, "hclk_spi2ahb", "busclk_pmu_root", 0, 802 RV1126B_PMU1CLKGATE_CON(0), 1, GFLAGS), 803 GATE(HCLK_FSPI1, "hclk_fspi1", "busclk_pmu_root", 0, 804 RV1126B_PMU1CLKGATE_CON(0), 2, GFLAGS), 805 GATE(HCLK_XIP_FSPI1, "hclk_xip_fspi1", "busclk_pmu_root", 0, 806 RV1126B_PMU1CLKGATE_CON(0), 3, GFLAGS), 807 COMPOSITE(SCLK_1X_FSPI1, "sclk_1x_fspi1", mux_24m_rcosc_buspmu_p, 0, 808 RV1126B_PMU1CLKSEL_CON(0), 0, 2, MFLAGS, 2, 3, DFLAGS, 809 RV1126B_PMU1CLKGATE_CON(0), 4, GFLAGS), 810 GATE(PCLK_IOC_PMUIO1, "pclk_ioc_pmuio1", "busclk_pmu_root", CLK_IS_CRITICAL, 811 RV1126B_PMU1CLKGATE_CON(0), 5, GFLAGS), 812 GATE(PCLK_AUDIO_ADC_PMU, "pclk_audio_adc_pmu", "busclk_pmu_root", 0, 813 RV1126B_PMU1CLKGATE_CON(0), 8, GFLAGS), 814 815 COMPOSITE(MCLK_LPSAI, "mclk_lpsai", mux_24m_rcosc_buspmu_p, 0, 816 RV1126B_PMU1CLKSEL_CON(0), 6, 2, MFLAGS, 8, 5, DFLAGS, 817 RV1126B_PMU1CLKGATE_CON(1), 3, GFLAGS), 818 GATE(MCLK_AUDIO_ADC_PMU, "mclk_audio_adc_pmu", "mclk_lpsai", CLK_IS_CRITICAL, 819 RV1126B_PMU1CLKGATE_CON(0), 9, GFLAGS), 820 FACTOR(MCLK_AUDIO_ADC_DIV4_PMU, "mclk_audio_adc_div4_pmu", "mclk_audio_adc_pmu", 0, 1, 4), 821 822 /* pd_bus */ 823 GATE(ACLK_GIC400, "aclk_gic400", "hclk_bus_root", CLK_IS_CRITICAL, 824 RV1126B_BUSCLKGATE_CON(0), 8, GFLAGS), 825 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0, 826 RV1126B_BUSCLKGATE_CON(0), 10, GFLAGS), 827 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "tclk_wdt_ns_src", 0, 828 RV1126B_BUSCLKGATE_CON(0), 11, GFLAGS), 829 GATE(PCLK_WDT_HPMCU, "pclk_wdt_hpmcu", "pclk_bus_root", 0, 830 RV1126B_BUSCLKGATE_CON(1), 0, GFLAGS), 831 GATE(HCLK_CACHE, "hclk_cache", "aclk_bus_root", 0, 832 RV1126B_BUSCLKGATE_CON(1), 2, GFLAGS), 833 GATE(PCLK_HPMCU_MAILBOX, "pclk_hpmcu_mailbox", "pclk_bus_root", 0, 834 RV1126B_BUSCLKGATE_CON(1), 3, GFLAGS), 835 GATE(PCLK_HPMCU_INTMUX, "pclk_hpmcu_intmux", "pclk_bus_root", 0, 836 RV1126B_BUSCLKGATE_CON(1), 4, GFLAGS), 837 GATE(CLK_HPMCU, "clk_hpmcu", "aclk_bus_root", 0, 838 RV1126B_BUSCLKGATE_CON(1), 5, GFLAGS), 839 GATE(CLK_HPMCU_RTC, "clk_hpmcu_rtc", "xin24m", 0, 840 RV1126B_BUSCLKGATE_CON(1), 10, GFLAGS), 841 GATE(PCLK_RKDMA, "pclk_rkdma", "pclk_bus_root", 0, 842 RV1126B_BUSCLKGATE_CON(1), 11, GFLAGS), 843 GATE(ACLK_RKDMA, "aclk_rkdma", "aclk_bus_root", 0, 844 RV1126B_BUSCLKGATE_CON(1), 12, GFLAGS), 845 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_root", 0, 846 RV1126B_BUSCLKGATE_CON(2), 0, GFLAGS), 847 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0, 848 RV1126B_BUSCLKGATE_CON(2), 1, GFLAGS), 849 GATE(HCLK_RGA, "hclk_rga", "hclk_bus_root", 0, 850 RV1126B_BUSCLKGATE_CON(2), 2, GFLAGS), 851 GATE(ACLK_RGA, "aclk_rga", "aclk_bus_root", 0, 852 RV1126B_BUSCLKGATE_CON(2), 3, GFLAGS), 853 GATE(CLK_CORE_RGA, "clk_core_rga", "clk_core_rga_src", 0, 854 RV1126B_BUSCLKGATE_CON(2), 4, GFLAGS), 855 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0, 856 RV1126B_BUSCLKGATE_CON(2), 5, GFLAGS), 857 COMPOSITE_NODIV(CLK_TIMER0, "clk_timer0", clk_timer0_parents_p, 0, 858 RV1126B_BUSCLKSEL_CON(2), 0, 2, MFLAGS, 859 RV1126B_BUSCLKGATE_CON(2), 6, GFLAGS), 860 COMPOSITE_NODIV(CLK_TIMER1, "clk_timer1", clk_timer1_parents_p, 0, 861 RV1126B_BUSCLKSEL_CON(2), 2, 2, MFLAGS, 862 RV1126B_BUSCLKGATE_CON(2), 7, GFLAGS), 863 COMPOSITE_NODIV(CLK_TIMER2, "clk_timer2", clk_timer2_parents_p, 0, 864 RV1126B_BUSCLKSEL_CON(2), 4, 2, MFLAGS, 865 RV1126B_BUSCLKGATE_CON(2), 8, GFLAGS), 866 COMPOSITE_NODIV(CLK_TIMER3, "clk_timer3", clk_timer3_parents_p, 0, 867 RV1126B_BUSCLKSEL_CON(2), 6, 2, MFLAGS, 868 RV1126B_BUSCLKGATE_CON(2), 9, GFLAGS), 869 COMPOSITE_NODIV(CLK_TIMER4, "clk_timer4", clk_timer4_parents_p, 0, 870 RV1126B_BUSCLKSEL_CON(2), 8, 2, MFLAGS, 871 RV1126B_BUSCLKGATE_CON(2), 10, GFLAGS), 872 GATE(HCLK_RKRNG_S_NS, "hclk_rkrng_s_ns", "hclk_bus_root", 0, 873 RV1126B_BUSCLKGATE_CON(2), 14, GFLAGS), 874 GATE(HCLK_RKRNG_NS, "hclk_rkrng_ns", "hclk_rkrng_s_ns", 0, 875 RV1126B_BUSCLKGATE_CON(2), 15, GFLAGS), 876 GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", CLK_IS_CRITICAL, 877 RV1126B_BUSCLKGATE_CON(2), 11, GFLAGS), 878 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_root", 0, 879 RV1126B_BUSCLKGATE_CON(3), 0, GFLAGS), 880 GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_bus_src", 0, 881 RV1126B_BUSCLKGATE_CON(3), 1, GFLAGS), 882 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0, 883 RV1126B_BUSCLKGATE_CON(3), 2, GFLAGS), 884 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_bus_src", 0, 885 RV1126B_BUSCLKGATE_CON(3), 3, GFLAGS), 886 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0, 887 RV1126B_BUSCLKGATE_CON(3), 4, GFLAGS), 888 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c_bus_src", 0, 889 RV1126B_BUSCLKGATE_CON(3), 5, GFLAGS), 890 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0, 891 RV1126B_BUSCLKGATE_CON(3), 6, GFLAGS), 892 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c_bus_src", 0, 893 RV1126B_BUSCLKGATE_CON(3), 7, GFLAGS), 894 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0, 895 RV1126B_BUSCLKGATE_CON(3), 8, GFLAGS), 896 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c_bus_src", 0, 897 RV1126B_BUSCLKGATE_CON(3), 9, GFLAGS), 898 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0, 899 RV1126B_BUSCLKGATE_CON(3), 10, GFLAGS), 900 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0, 901 RV1126B_BUSCLKGATE_CON(3), 12, GFLAGS), 902 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0, 903 RV1126B_BUSCLKGATE_CON(4), 0, GFLAGS), 904 GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0, 905 RV1126B_BUSCLKGATE_CON(4), 1, GFLAGS), 906 GATE(CLK_RC_PWM0, "clk_rc_pwm0", "xin24m", 0, 907 RV1126B_BUSCLKGATE_CON(4), 2, GFLAGS), 908 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0, 909 RV1126B_BUSCLKGATE_CON(4), 3, GFLAGS), 910 GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0, 911 RV1126B_BUSCLKGATE_CON(4), 4, GFLAGS), 912 GATE(CLK_RC_PWM2, "clk_rc_pwm2", "xin24m", 0, 913 RV1126B_BUSCLKGATE_CON(4), 5, GFLAGS), 914 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus_root", 0, 915 RV1126B_BUSCLKGATE_CON(4), 6, GFLAGS), 916 GATE(CLK_OSC_PWM3, "clk_osc_pwm3", "xin24m", 0, 917 RV1126B_BUSCLKGATE_CON(4), 7, GFLAGS), 918 GATE(CLK_RC_PWM3, "clk_rc_pwm3", "xin24m", 0, 919 RV1126B_BUSCLKGATE_CON(4), 8, GFLAGS), 920 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_root", 0, 921 RV1126B_BUSCLKGATE_CON(4), 9, GFLAGS), 922 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0, 923 RV1126B_BUSCLKGATE_CON(4), 10, GFLAGS), 924 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0, 925 RV1126B_BUSCLKGATE_CON(4), 11, GFLAGS), 926 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0, 927 RV1126B_BUSCLKGATE_CON(4), 12, GFLAGS), 928 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0, 929 RV1126B_BUSCLKGATE_CON(4), 13, GFLAGS), 930 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0, 931 RV1126B_BUSCLKGATE_CON(4), 14, GFLAGS), 932 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0, 933 RV1126B_BUSCLKGATE_CON(4), 15, GFLAGS), 934 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", CLK_IS_CRITICAL, 935 RV1126B_BUSCLKGATE_CON(5), 0, GFLAGS), 936 GATE(CLK_TSADC, "clk_tsadc", "xin24m", CLK_IS_CRITICAL, 937 RV1126B_BUSCLKGATE_CON(5), 1, GFLAGS), 938 GATE(HCLK_SAI0, "hclk_sai0", "hclk_bus_root", 0, 939 RV1126B_BUSCLKGATE_CON(5), 2, GFLAGS), 940 GATE(HCLK_SAI1, "hclk_sai1", "hclk_bus_root", 0, 941 RV1126B_BUSCLKGATE_CON(5), 4, GFLAGS), 942 GATE(HCLK_SAI2, "hclk_sai2", "hclk_bus_root", 0, 943 RV1126B_BUSCLKGATE_CON(5), 6, GFLAGS), 944 GATE(HCLK_RKDSM, "hclk_rkdsm", "hclk_bus_root", 0, 945 RV1126B_BUSCLKGATE_CON(5), 8, GFLAGS), 946 GATE(MCLK_RKDSM, "mclk_rkdsm", "mclk_sai2", 0, 947 RV1126B_BUSCLKGATE_CON(5), 9, GFLAGS), 948 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_root", 0, 949 RV1126B_BUSCLKGATE_CON(5), 10, GFLAGS), 950 GATE(HCLK_ASRC0, "hclk_asrc0", "hclk_bus_root", 0, 951 RV1126B_BUSCLKGATE_CON(5), 11, GFLAGS), 952 GATE(HCLK_ASRC1, "hclk_asrc1", "hclk_bus_root", 0, 953 RV1126B_BUSCLKGATE_CON(5), 12, GFLAGS), 954 GATE(PCLK_AUDIO_ADC_BUS, "pclk_audio_adc_bus", "pclk_bus_root", 0, 955 RV1126B_BUSCLKGATE_CON(5), 13, GFLAGS), 956 GATE(MCLK_AUDIO_ADC_BUS, "mclk_audio_adc_bus", "mclk_sai2", 0, 957 RV1126B_BUSCLKGATE_CON(5), 14, GFLAGS), 958 FACTOR(MCLK_AUDIO_ADC_DIV4_BUS, "mclk_audio_adc_div4_bus", "mclk_audio_adc_bus", 0, 1, 4), 959 GATE(PCLK_RKCE, "pclk_rkce", "pclk_bus_root", CLK_IS_CRITICAL, 960 RV1126B_BUSCLKGATE_CON(6), 0, GFLAGS), 961 GATE(HCLK_NS_RKCE, "hclk_ns_rkce", "hclk_bus_root", 0, 962 RV1126B_BUSCLKGATE_CON(6), 1, GFLAGS), 963 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_bus_root", 0, 964 RV1126B_BUSCLKGATE_CON(6), 2, GFLAGS), 965 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, 966 RV1126B_BUSCLKGATE_CON(6), 3, GFLAGS), 967 COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0, 968 RV1126B_BUSCLKSEL_CON(2), 12, 3, DFLAGS, 969 RV1126B_BUSCLKGATE_CON(6), 4, GFLAGS), 970 GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_bus_root", 0, 971 RV1126B_BUSCLKGATE_CON(6), 6, GFLAGS), 972 GATE(CLK_TSADC_PHYCTRL, "clk_tsadc_phyctrl", "xin24m", CLK_IS_CRITICAL, 973 RV1126B_BUSCLKGATE_CON(6), 8, GFLAGS), 974 MUX(LRCK_SRC_ASRC0, "lrck_src_asrc0", lrck_src_asrc_p, 0, 975 RV1126B_BUSCLKSEL_CON(3), 0, 3, MFLAGS), 976 MUX(LRCK_DST_ASRC0, "lrck_dst_asrc0", lrck_src_asrc_p, 0, 977 RV1126B_BUSCLKSEL_CON(3), 4, 3, MFLAGS), 978 MUX(LRCK_SRC_ASRC1, "lrck_src_asrc1", lrck_src_asrc_p, 0, 979 RV1126B_BUSCLKSEL_CON(3), 8, 3, MFLAGS), 980 MUX(LRCK_DST_ASRC1, "lrck_dst_asrc1", lrck_src_asrc_p, 0, 981 RV1126B_BUSCLKSEL_CON(3), 12, 3, MFLAGS), 982 GATE(ACLK_NSRKCE, "aclk_nsrkce", "aclk_rkce_src", 0, 983 RV1126B_BUSCLKGATE_CON(2), 12, GFLAGS), 984 GATE(CLK_PKA_NSRKCE, "clk_pka_nsrkce", "clk_pka_rkce_src", 0, 985 RV1126B_BUSCLKGATE_CON(2), 13, GFLAGS), 986 987 /* pd_peri */ 988 DIV(PCLK_RTC_ROOT, "pclk_rtc_root", "pclk_peri_root", 0, 989 RV1126B_PERICLKSEL_CON(0), 0, 2, DFLAGS), 990 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri_root", 0, 991 RV1126B_PERICLKGATE_CON(0), 5, GFLAGS), 992 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, 993 RV1126B_PERICLKGATE_CON(0), 6, GFLAGS), 994 GATE(PCLK_IOC_VCCIO1, "pclk_ioc_vccio1", "pclk_peri_root", CLK_IS_CRITICAL, 995 RV1126B_PERICLKGATE_CON(0), 7, GFLAGS), 996 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri_root", 0, 997 RV1126B_PERICLKGATE_CON(0), 8, GFLAGS), 998 GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0, 999 RV1126B_PERICLKGATE_CON(0), 9, GFLAGS), 1000 GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0, 1001 RV1126B_PERICLKGATE_CON(0), 10, GFLAGS), 1002 GATE(HCLK_USB2HOST, "hclk_usb2host", "aclk_peri_root", 0, 1003 RV1126B_PERICLKGATE_CON(0), 11, GFLAGS), 1004 GATE(HCLK_ARB_USB2HOST, "hclk_arb_usb2host", "aclk_peri_root", 0, 1005 RV1126B_PERICLKGATE_CON(0), 12, GFLAGS), 1006 GATE(PCLK_RTC_TEST, "pclk_rtc_test", "pclk_rtc_root", 0, 1007 RV1126B_PERICLKGATE_CON(0), 13, GFLAGS), 1008 GATE(HCLK_EMMC, "hclk_emmc", "aclk_peri_root", 0, 1009 RV1126B_PERICLKGATE_CON(1), 0, GFLAGS), 1010 GATE(HCLK_FSPI0, "hclk_fspi0", "aclk_peri_root", 0, 1011 RV1126B_PERICLKGATE_CON(1), 1, GFLAGS), 1012 GATE(HCLK_XIP_FSPI0, "hclk_xip_fspi0", "aclk_peri_root", 0, 1013 RV1126B_PERICLKGATE_CON(1), 2, GFLAGS), 1014 GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri_root", 0, 1015 RV1126B_PERICLKGATE_CON(1), 8, GFLAGS), 1016 GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri_root", 0, 1017 RV1126B_PERICLKGATE_CON(1), 10, GFLAGS), 1018 COMPOSITE_NOMUX(CLK_REF_PIPEPHY_CPLL_SRC, "clk_ref_pipephy_cpll_src", "cpll", 0, 1019 RV1126B_PERICLKSEL_CON(1), 0, 6, DFLAGS, 1020 RV1126B_PERICLKGATE_CON(1), 14, GFLAGS), 1021 MUX(CLK_REF_PIPEPHY, "clk_ref_pipephy", clk_ref_pipephy_p, 0, 1022 RV1126B_PERICLKSEL_CON(1), 12, 1, MFLAGS), 1023}; 1024 1025static struct rockchip_clk_branch rv1126b_armclk __initdata = 1026 MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1027 RV1126B_CORECLKSEL_CON(0), 1, 1, MFLAGS); 1028 1029static void __init rv1126b_clk_init(struct device_node *np) 1030{ 1031 struct rockchip_clk_provider *ctx; 1032 void __iomem *reg_base; 1033 unsigned long clk_nr_clks; 1034 1035 clk_nr_clks = rockchip_clk_find_max_clk_id(rv1126b_clk_branches, 1036 ARRAY_SIZE(rv1126b_clk_branches)) + 1; 1037 1038 reg_base = of_iomap(np, 0); 1039 if (!reg_base) { 1040 pr_err("%s: could not map cru region\n", __func__); 1041 return; 1042 } 1043 1044 ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); 1045 if (IS_ERR(ctx)) { 1046 pr_err("%s: rockchip clk init failed\n", __func__); 1047 iounmap(reg_base); 1048 return; 1049 } 1050 1051 rockchip_clk_register_plls(ctx, rv1126b_pll_clks, 1052 ARRAY_SIZE(rv1126b_pll_clks), 1053 0); 1054 1055 rockchip_clk_register_branches(ctx, rv1126b_clk_branches, 1056 ARRAY_SIZE(rv1126b_clk_branches)); 1057 1058 rockchip_clk_register_armclk_multi_pll(ctx, &rv1126b_armclk, 1059 rv1126b_cpuclk_rates, 1060 ARRAY_SIZE(rv1126b_cpuclk_rates)); 1061 1062 rv1126b_rst_init(np, reg_base); 1063 1064 rockchip_register_restart_notifier(ctx, RV1126B_GLB_SRST_FST, NULL); 1065 1066 rockchip_clk_of_add_provider(np, ctx); 1067 1068 /* pvtpll src init */ 1069 writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_CORECLKSEL_CON(0)); 1070 writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_NPUCLKSEL_CON(0)); 1071 writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VICLKSEL_CON(0)); 1072 writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VEPUCLKSEL_CON(0)); 1073 writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VCPCLKSEL_CON(0)); 1074} 1075 1076CLK_OF_DECLARE(rv1126b_cru, "rockchip,rv1126b-cru", rv1126b_clk_init); 1077 1078struct clk_rv1126b_inits { 1079 void (*inits)(struct device_node *np); 1080}; 1081 1082static const struct clk_rv1126b_inits clk_rv1126b_init = { 1083 .inits = rv1126b_clk_init, 1084}; 1085 1086static const struct of_device_id clk_rv1126b_match_table[] = { 1087 { 1088 .compatible = "rockchip,rv1126b-cru", 1089 .data = &clk_rv1126b_init, 1090 }, 1091 { } 1092}; 1093 1094static int clk_rv1126b_probe(struct platform_device *pdev) 1095{ 1096 const struct clk_rv1126b_inits *init_data; 1097 struct device *dev = &pdev->dev; 1098 1099 init_data = device_get_match_data(dev); 1100 if (!init_data) 1101 return -EINVAL; 1102 1103 if (init_data->inits) 1104 init_data->inits(dev->of_node); 1105 1106 return 0; 1107} 1108 1109static struct platform_driver clk_rv1126b_driver = { 1110 .probe = clk_rv1126b_probe, 1111 .driver = { 1112 .name = "clk-rv1126b", 1113 .of_match_table = clk_rv1126b_match_table, 1114 .suppress_bind_attrs = true, 1115 }, 1116}; 1117builtin_platform_driver_probe(clk_rv1126b_driver, clk_rv1126b_probe);
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