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clk-rk3588.c
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linux-6.19.14/drivers/clk/rockchip/clk-rk3588.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7#include <linux/clk-provider.h> 8#include <linux/of.h> 9#include <linux/of_address.h> 10#include <linux/platform_device.h> 11#include <linux/syscore_ops.h> 12#include <dt-bindings/clock/rockchip,rk3588-cru.h> 13#include "clk.h" 14 15#define RK3588_GRF_SOC_STATUS0 0x600 16#define RK3588_PHYREF_ALT_GATE 0xc38 17 18enum rk3588_plls { 19 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, 20}; 21 22static struct rockchip_pll_rate_table rk3588_pll_rates[] = { 23 /* _mhz, _p, _m, _s, _k */ 24 RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), 25 RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), 26 RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), 27 RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), 28 RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), 29 RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), 30 RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), 31 RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), 32 RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), 33 RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), 34 RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), 35 RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), 36 RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), 37 RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), 38 RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), 39 RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), 40 RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), 41 RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), 42 RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), 43 RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), 44 RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), 45 RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), 46 RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), 47 RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), 48 RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), 49 RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), 50 RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), 51 RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), 52 RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), 53 RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), 54 RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), 55 RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), 56 RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), 57 RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), 58 RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), 59 RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), 60 RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), 61 RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), 62 RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), 63 RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), 64 RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), 65 RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), 66 RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), 67 RK3588_PLL_RATE(1500000000, 2, 250, 1, 0), 68 RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), 69 RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), 70 RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), 71 RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), 72 RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), 73 RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), 74 RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), 75 RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), 76 RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), 77 RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), 78 RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), 79 RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), 80 RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), 81 RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), 82 RK3588_PLL_RATE(900000000, 2, 300, 2, 0), 83 RK3588_PLL_RATE(850000000, 3, 425, 2, 0), 84 RK3588_PLL_RATE(816000000, 2, 272, 2, 0), 85 RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), 86 RK3588_PLL_RATE(786000000, 1, 131, 2, 0), 87 RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), 88 RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), 89 RK3588_PLL_RATE(600000000, 2, 200, 2, 0), 90 RK3588_PLL_RATE(594000000, 2, 198, 2, 0), 91 RK3588_PLL_RATE(408000000, 2, 272, 3, 0), 92 RK3588_PLL_RATE(312000000, 2, 208, 3, 0), 93 RK3588_PLL_RATE(216000000, 2, 288, 4, 0), 94 RK3588_PLL_RATE(100000000, 3, 400, 5, 0), 95 RK3588_PLL_RATE(96000000, 2, 256, 5, 0), 96 { /* sentinel */ }, 97}; 98 99#define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3 100#define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13 101#define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3 102#define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5 103#define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f 104#define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1 105#define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3 106#define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12 107#define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5 108#define RK3588_CLK_DSU_SEL_DF_MASK 0x1 109#define RK3588_CLK_DSU_SEL_DF_SHIFT 15 110#define RK3588_CLK_DSU_DF_SRC_MASK 0x3 111#define RK3588_CLK_DSU_DF_SRC_SHIFT 12 112#define RK3588_CLK_DSU_DF_DIV_MASK 0x1f 113#define RK3588_CLK_DSU_DF_DIV_SHIFT 7 114#define RK3588_ACLKM_DSU_DIV_MASK 0x1f 115#define RK3588_ACLKM_DSU_DIV_SHIFT 1 116#define RK3588_ACLKS_DSU_DIV_MASK 0x1f 117#define RK3588_ACLKS_DSU_DIV_SHIFT 6 118#define RK3588_ACLKMP_DSU_DIV_MASK 0x1f 119#define RK3588_ACLKMP_DSU_DIV_SHIFT 11 120#define RK3588_PERIPH_DSU_DIV_MASK 0x1f 121#define RK3588_PERIPH_DSU_DIV_SHIFT 0 122#define RK3588_ATCLK_DSU_DIV_MASK 0x1f 123#define RK3588_ATCLK_DSU_DIV_SHIFT 0 124#define RK3588_GICCLK_DSU_DIV_MASK 0x1f 125#define RK3588_GICCLK_DSU_DIV_SHIFT 5 126 127#define RK3588_CORE_B0_SEL(_apllcore) \ 128{ \ 129 .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \ 130 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ 131 RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ 132 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ 133 RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ 134} 135 136#define RK3588_CORE_B1_SEL(_apllcore) \ 137{ \ 138 .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \ 139 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ 140 RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ 141} 142 143#define RK3588_CORE_B2_SEL(_apllcore) \ 144{ \ 145 .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \ 146 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ 147 RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ 148 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ 149 RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ 150} 151 152#define RK3588_CORE_B3_SEL(_apllcore) \ 153{ \ 154 .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \ 155 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ 156 RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ 157} 158 159#define RK3588_CORE_L_SEL0(_offs, _apllcore) \ 160{ \ 161 .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \ 162 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ 163 RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \ 164 HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ 165 RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \ 166} 167 168#define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \ 169{ \ 170 .reg = RK3588_DSU_CLKSEL_CON(0), \ 171 .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \ 172 RK3588_CLK_DSU_DF_SRC_SHIFT) | \ 173 HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \ 174 RK3588_CLK_DSU_DF_DIV_SHIFT), \ 175} 176 177#define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \ 178{ \ 179 .reg = RK3588_DSU_CLKSEL_CON(1), \ 180 .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \ 181 RK3588_ACLKM_DSU_DIV_SHIFT) | \ 182 HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \ 183 RK3588_ACLKMP_DSU_DIV_SHIFT) | \ 184 HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \ 185 RK3588_ACLKS_DSU_DIV_SHIFT), \ 186} 187 188#define RK3588_CORE_L_SEL3(_periph) \ 189{ \ 190 .reg = RK3588_DSU_CLKSEL_CON(2), \ 191 .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \ 192 RK3588_PERIPH_DSU_DIV_SHIFT), \ 193} 194 195#define RK3588_CORE_L_SEL4(_gicclk, _atclk) \ 196{ \ 197 .reg = RK3588_DSU_CLKSEL_CON(3), \ 198 .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \ 199 RK3588_GICCLK_DSU_DIV_SHIFT) | \ 200 HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \ 201 RK3588_ATCLK_DSU_DIV_SHIFT), \ 202} 203 204#define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \ 205{ \ 206 .prate = _prate##U, \ 207 .pre_muxs = { \ 208 RK3588_CORE_B0_SEL(0), \ 209 RK3588_CORE_B1_SEL(0), \ 210 }, \ 211 .post_muxs = { \ 212 RK3588_CORE_B0_SEL(_apllcore), \ 213 RK3588_CORE_B1_SEL(_apllcore), \ 214 }, \ 215} 216 217#define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \ 218{ \ 219 .prate = _prate##U, \ 220 .pre_muxs = { \ 221 RK3588_CORE_B2_SEL(0), \ 222 RK3588_CORE_B3_SEL(0), \ 223 }, \ 224 .post_muxs = { \ 225 RK3588_CORE_B2_SEL(_apllcore), \ 226 RK3588_CORE_B3_SEL(_apllcore), \ 227 }, \ 228} 229 230#define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \ 231{ \ 232 .prate = _prate##U, \ 233 .pre_muxs = { \ 234 RK3588_CORE_L_SEL0(0, 0), \ 235 RK3588_CORE_L_SEL0(1, 0), \ 236 RK3588_CORE_L_SEL1(3, 2), \ 237 RK3588_CORE_L_SEL2(2, 3, 3), \ 238 RK3588_CORE_L_SEL3(4), \ 239 RK3588_CORE_L_SEL4(4, 4), \ 240 }, \ 241 .post_muxs = { \ 242 RK3588_CORE_L_SEL0(0, _apllcore), \ 243 RK3588_CORE_L_SEL0(1, _apllcore), \ 244 RK3588_CORE_L_SEL1(_seldsu, _divdsu), \ 245 }, \ 246} 247 248static struct rockchip_clk_provider *early_ctx; 249 250static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { 251 RK3588_CPUB01CLK_RATE(2496000000, 1), 252 RK3588_CPUB01CLK_RATE(2400000000, 1), 253 RK3588_CPUB01CLK_RATE(2304000000, 1), 254 RK3588_CPUB01CLK_RATE(2208000000, 1), 255 RK3588_CPUB01CLK_RATE(2184000000, 1), 256 RK3588_CPUB01CLK_RATE(2088000000, 1), 257 RK3588_CPUB01CLK_RATE(2040000000, 1), 258 RK3588_CPUB01CLK_RATE(2016000000, 1), 259 RK3588_CPUB01CLK_RATE(1992000000, 1), 260 RK3588_CPUB01CLK_RATE(1896000000, 1), 261 RK3588_CPUB01CLK_RATE(1800000000, 1), 262 RK3588_CPUB01CLK_RATE(1704000000, 0), 263 RK3588_CPUB01CLK_RATE(1608000000, 0), 264 RK3588_CPUB01CLK_RATE(1584000000, 0), 265 RK3588_CPUB01CLK_RATE(1560000000, 0), 266 RK3588_CPUB01CLK_RATE(1536000000, 0), 267 RK3588_CPUB01CLK_RATE(1512000000, 0), 268 RK3588_CPUB01CLK_RATE(1488000000, 0), 269 RK3588_CPUB01CLK_RATE(1464000000, 0), 270 RK3588_CPUB01CLK_RATE(1440000000, 0), 271 RK3588_CPUB01CLK_RATE(1416000000, 0), 272 RK3588_CPUB01CLK_RATE(1392000000, 0), 273 RK3588_CPUB01CLK_RATE(1368000000, 0), 274 RK3588_CPUB01CLK_RATE(1344000000, 0), 275 RK3588_CPUB01CLK_RATE(1320000000, 0), 276 RK3588_CPUB01CLK_RATE(1296000000, 0), 277 RK3588_CPUB01CLK_RATE(1272000000, 0), 278 RK3588_CPUB01CLK_RATE(1248000000, 0), 279 RK3588_CPUB01CLK_RATE(1224000000, 0), 280 RK3588_CPUB01CLK_RATE(1200000000, 0), 281 RK3588_CPUB01CLK_RATE(1104000000, 0), 282 RK3588_CPUB01CLK_RATE(1008000000, 0), 283 RK3588_CPUB01CLK_RATE(912000000, 0), 284 RK3588_CPUB01CLK_RATE(816000000, 0), 285 RK3588_CPUB01CLK_RATE(696000000, 0), 286 RK3588_CPUB01CLK_RATE(600000000, 0), 287 RK3588_CPUB01CLK_RATE(408000000, 0), 288 RK3588_CPUB01CLK_RATE(312000000, 0), 289 RK3588_CPUB01CLK_RATE(216000000, 0), 290 RK3588_CPUB01CLK_RATE(96000000, 0), 291}; 292 293static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = { 294 .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0), 295 .div_core_shift[0] = 8, 296 .div_core_mask[0] = 0x1f, 297 .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1), 298 .div_core_shift[1] = 0, 299 .div_core_mask[1] = 0x1f, 300 .num_cores = 2, 301 .mux_core_alt = 1, 302 .mux_core_main = 2, 303 .mux_core_shift = 6, 304 .mux_core_mask = 0x3, 305}; 306 307static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = { 308 RK3588_CPUB23CLK_RATE(2496000000, 1), 309 RK3588_CPUB23CLK_RATE(2400000000, 1), 310 RK3588_CPUB23CLK_RATE(2304000000, 1), 311 RK3588_CPUB23CLK_RATE(2208000000, 1), 312 RK3588_CPUB23CLK_RATE(2184000000, 1), 313 RK3588_CPUB23CLK_RATE(2088000000, 1), 314 RK3588_CPUB23CLK_RATE(2040000000, 1), 315 RK3588_CPUB23CLK_RATE(2016000000, 1), 316 RK3588_CPUB23CLK_RATE(1992000000, 1), 317 RK3588_CPUB23CLK_RATE(1896000000, 1), 318 RK3588_CPUB23CLK_RATE(1800000000, 1), 319 RK3588_CPUB23CLK_RATE(1704000000, 0), 320 RK3588_CPUB23CLK_RATE(1608000000, 0), 321 RK3588_CPUB23CLK_RATE(1584000000, 0), 322 RK3588_CPUB23CLK_RATE(1560000000, 0), 323 RK3588_CPUB23CLK_RATE(1536000000, 0), 324 RK3588_CPUB23CLK_RATE(1512000000, 0), 325 RK3588_CPUB23CLK_RATE(1488000000, 0), 326 RK3588_CPUB23CLK_RATE(1464000000, 0), 327 RK3588_CPUB23CLK_RATE(1440000000, 0), 328 RK3588_CPUB23CLK_RATE(1416000000, 0), 329 RK3588_CPUB23CLK_RATE(1392000000, 0), 330 RK3588_CPUB23CLK_RATE(1368000000, 0), 331 RK3588_CPUB23CLK_RATE(1344000000, 0), 332 RK3588_CPUB23CLK_RATE(1320000000, 0), 333 RK3588_CPUB23CLK_RATE(1296000000, 0), 334 RK3588_CPUB23CLK_RATE(1272000000, 0), 335 RK3588_CPUB23CLK_RATE(1248000000, 0), 336 RK3588_CPUB23CLK_RATE(1224000000, 0), 337 RK3588_CPUB23CLK_RATE(1200000000, 0), 338 RK3588_CPUB23CLK_RATE(1104000000, 0), 339 RK3588_CPUB23CLK_RATE(1008000000, 0), 340 RK3588_CPUB23CLK_RATE(912000000, 0), 341 RK3588_CPUB23CLK_RATE(816000000, 0), 342 RK3588_CPUB23CLK_RATE(696000000, 0), 343 RK3588_CPUB23CLK_RATE(600000000, 0), 344 RK3588_CPUB23CLK_RATE(408000000, 0), 345 RK3588_CPUB23CLK_RATE(312000000, 0), 346 RK3588_CPUB23CLK_RATE(216000000, 0), 347 RK3588_CPUB23CLK_RATE(96000000, 0), 348}; 349 350static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = { 351 .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0), 352 .div_core_shift[0] = 8, 353 .div_core_mask[0] = 0x1f, 354 .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1), 355 .div_core_shift[1] = 0, 356 .div_core_mask[1] = 0x1f, 357 .num_cores = 2, 358 .mux_core_alt = 1, 359 .mux_core_main = 2, 360 .mux_core_shift = 6, 361 .mux_core_mask = 0x3, 362}; 363 364static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = { 365 RK3588_CPULCLK_RATE(2208000000, 1, 3, 1), 366 RK3588_CPULCLK_RATE(2184000000, 1, 3, 1), 367 RK3588_CPULCLK_RATE(2088000000, 1, 3, 1), 368 RK3588_CPULCLK_RATE(2040000000, 1, 3, 1), 369 RK3588_CPULCLK_RATE(2016000000, 1, 3, 1), 370 RK3588_CPULCLK_RATE(1992000000, 1, 3, 1), 371 RK3588_CPULCLK_RATE(1896000000, 1, 3, 1), 372 RK3588_CPULCLK_RATE(1800000000, 1, 3, 1), 373 RK3588_CPULCLK_RATE(1704000000, 0, 3, 1), 374 RK3588_CPULCLK_RATE(1608000000, 0, 3, 1), 375 RK3588_CPULCLK_RATE(1584000000, 0, 2, 1), 376 RK3588_CPULCLK_RATE(1560000000, 0, 2, 1), 377 RK3588_CPULCLK_RATE(1536000000, 0, 2, 1), 378 RK3588_CPULCLK_RATE(1512000000, 0, 2, 1), 379 RK3588_CPULCLK_RATE(1488000000, 0, 2, 1), 380 RK3588_CPULCLK_RATE(1464000000, 0, 2, 1), 381 RK3588_CPULCLK_RATE(1440000000, 0, 2, 1), 382 RK3588_CPULCLK_RATE(1416000000, 0, 2, 1), 383 RK3588_CPULCLK_RATE(1392000000, 0, 2, 1), 384 RK3588_CPULCLK_RATE(1368000000, 0, 2, 1), 385 RK3588_CPULCLK_RATE(1344000000, 0, 2, 1), 386 RK3588_CPULCLK_RATE(1320000000, 0, 2, 1), 387 RK3588_CPULCLK_RATE(1296000000, 0, 2, 1), 388 RK3588_CPULCLK_RATE(1272000000, 0, 2, 1), 389 RK3588_CPULCLK_RATE(1248000000, 0, 2, 1), 390 RK3588_CPULCLK_RATE(1224000000, 0, 2, 1), 391 RK3588_CPULCLK_RATE(1200000000, 0, 2, 1), 392 RK3588_CPULCLK_RATE(1104000000, 0, 2, 1), 393 RK3588_CPULCLK_RATE(1008000000, 0, 2, 1), 394 RK3588_CPULCLK_RATE(912000000, 0, 2, 1), 395 RK3588_CPULCLK_RATE(816000000, 0, 2, 1), 396 RK3588_CPULCLK_RATE(696000000, 0, 2, 1), 397 RK3588_CPULCLK_RATE(600000000, 0, 2, 1), 398 RK3588_CPULCLK_RATE(408000000, 0, 2, 1), 399 RK3588_CPULCLK_RATE(312000000, 0, 2, 1), 400 RK3588_CPULCLK_RATE(216000000, 0, 2, 1), 401 RK3588_CPULCLK_RATE(96000000, 0, 2, 1), 402}; 403 404static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = { 405 .core_reg[0] = RK3588_DSU_CLKSEL_CON(6), 406 .div_core_shift[0] = 0, 407 .div_core_mask[0] = 0x1f, 408 .core_reg[1] = RK3588_DSU_CLKSEL_CON(6), 409 .div_core_shift[1] = 7, 410 .div_core_mask[1] = 0x1f, 411 .core_reg[2] = RK3588_DSU_CLKSEL_CON(7), 412 .div_core_shift[2] = 0, 413 .div_core_mask[2] = 0x1f, 414 .core_reg[3] = RK3588_DSU_CLKSEL_CON(7), 415 .div_core_shift[3] = 7, 416 .div_core_mask[3] = 0x1f, 417 .num_cores = 4, 418 .mux_core_reg = RK3588_DSU_CLKSEL_CON(5), 419 .mux_core_alt = 1, 420 .mux_core_main = 2, 421 .mux_core_shift = 14, 422 .mux_core_mask = 0x3, 423}; 424 425PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 426PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" }; 427PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",}; 428PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",}; 429PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" }; 430PNAME(gpll_24m_p) = { "gpll", "xin24m" }; 431PNAME(gpll_aupll_p) = { "gpll", "aupll" }; 432PNAME(gpll_lpll_p) = { "gpll", "lpll" }; 433PNAME(gpll_cpll_p) = { "gpll", "cpll" }; 434PNAME(gpll_spll_p) = { "gpll", "spll" }; 435PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"}; 436PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"}; 437PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"}; 438PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"}; 439PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; 440PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; 441PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" }; 442PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" }; 443PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" }; 444PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" }; 445PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" }; 446PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" }; 447PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" }; 448PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" }; 449PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" }; 450PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" }; 451PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" }; 452PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" }; 453PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" }; 454PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" }; 455PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" }; 456PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; 457PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; 458PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; 459PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" }; 460PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" }; 461PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" }; 462PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; 463PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" }; 464PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" }; 465PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" }; 466PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" }; 467PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; 468PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; 469PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" }; 470PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" }; 471PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" }; 472PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" }; 473PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" }; 474PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" }; 475PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" }; 476PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" }; 477PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" }; 478PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" }; 479PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" }; 480PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" }; 481PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" }; 482PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" }; 483PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" }; 484PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" }; 485PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" }; 486PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" }; 487PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" }; 488PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" }; 489PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 490PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 491PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 492PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 493PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 494PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 495PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 496PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 497PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 498PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" }; 499PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" }; 500PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" }; 501PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" }; 502PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" }; 503PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 504PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 505PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 506PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; 507PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" }; 508PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" }; 509PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; 510PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "xin32k", "clk_pmu1_100m_src" }; 511PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; 512PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" }; 513PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" }; 514PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" }; 515PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 516PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" }; 517PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" }; 518PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" }; 519 520#define MFLAGS CLK_MUX_HIWORD_MASK 521#define DFLAGS CLK_DIVIDER_HIWORD_MASK 522#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 523 524static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata = 525 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, 526 RK3588_CLKSEL_CON(26), 0, 2, MFLAGS); 527 528static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata = 529 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, 530 RK3588_CLKSEL_CON(28), 0, 2, MFLAGS); 531 532static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata = 533 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, 534 RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS); 535 536static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata = 537 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, 538 RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS); 539 540static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata = 541 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, 542 RK3588_CLKSEL_CON(30), 0, 2, MFLAGS); 543 544static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata = 545 MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT, 546 RK3588_CLKSEL_CON(32), 0, 2, MFLAGS); 547 548static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata = 549 MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT, 550 RK3588_CLKSEL_CON(120), 0, 2, MFLAGS); 551 552static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata = 553 MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT, 554 RK3588_CLKSEL_CON(142), 0, 2, MFLAGS); 555 556static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata = 557 MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT, 558 RK3588_CLKSEL_CON(146), 0, 2, MFLAGS); 559 560static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata = 561 MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT, 562 RK3588_CLKSEL_CON(148), 0, 2, MFLAGS); 563 564static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata = 565 MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT, 566 RK3588_CLKSEL_CON(131), 0, 2, MFLAGS); 567 568static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata = 569 MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT, 570 RK3588_CLKSEL_CON(122), 0, 2, MFLAGS); 571 572static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata = 573 MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT, 574 RK3588_CLKSEL_CON(155), 0, 2, MFLAGS); 575 576static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata = 577 MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT, 578 RK3588_CLKSEL_CON(157), 0, 2, MFLAGS); 579 580static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata = 581 MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT, 582 RK3588_CLKSEL_CON(34), 0, 2, MFLAGS); 583 584static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata = 585 MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT, 586 RK3588_CLKSEL_CON(36), 0, 2, MFLAGS); 587 588static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata = 589 MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT, 590 RK3588_CLKSEL_CON(124), 0, 2, MFLAGS); 591 592static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata = 593 MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT, 594 RK3588_CLKSEL_CON(150), 0, 2, MFLAGS); 595 596static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata = 597 MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT, 598 RK3588_CLKSEL_CON(152), 0, 2, MFLAGS); 599 600static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata = 601 MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT, 602 RK3588_CLKSEL_CON(126), 0, 2, MFLAGS); 603 604static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata = 605 MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT, 606 RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS); 607 608static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata = 609 MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, 610 RK3588_CLKSEL_CON(43), 0, 2, MFLAGS); 611 612static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata = 613 MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, 614 RK3588_CLKSEL_CON(45), 0, 2, MFLAGS); 615 616static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata = 617 MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, 618 RK3588_CLKSEL_CON(47), 0, 2, MFLAGS); 619 620static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata = 621 MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, 622 RK3588_CLKSEL_CON(49), 0, 2, MFLAGS); 623 624static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata = 625 MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, 626 RK3588_CLKSEL_CON(51), 0, 2, MFLAGS); 627 628static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata = 629 MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, 630 RK3588_CLKSEL_CON(53), 0, 2, MFLAGS); 631 632static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata = 633 MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, 634 RK3588_CLKSEL_CON(55), 0, 2, MFLAGS); 635 636static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata = 637 MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, 638 RK3588_CLKSEL_CON(57), 0, 2, MFLAGS); 639 640static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata = 641 MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, 642 RK3588_CLKSEL_CON(59), 0, 2, MFLAGS); 643 644static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = 645 MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT, 646 RK3588_CLKSEL_CON(140), 0, 1, MFLAGS); 647 648static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { 649 [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, 650 CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), 651 RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 652 [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, 653 CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), 654 RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 655 [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, 656 CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), 657 RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 658 [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, 659 0, RK3588_PLL_CON(88), 660 RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates), 661 [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, 662 0, RK3588_PLL_CON(96), 663 RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates), 664 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, 665 CLK_IGNORE_UNUSED, RK3588_PLL_CON(104), 666 RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates), 667 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, 668 CLK_IGNORE_UNUSED, RK3588_PLL_CON(112), 669 RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates), 670 [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p, 671 0, RK3588_PLL_CON(120), 672 RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 673 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, 674 CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128), 675 RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), 676}; 677 678static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { 679 /* 680 * CRU Clock-Architecture 681 */ 682 /* fixed */ 683 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 684 685 /* top */ 686 COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, 687 RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, 688 RK3588_CLKGATE_CON(0), 0, GFLAGS), 689 COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, 690 RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, 691 RK3588_CLKGATE_CON(0), 1, GFLAGS), 692 COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, 693 RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, 694 RK3588_CLKGATE_CON(0), 2, GFLAGS), 695 COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, 696 RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, 697 RK3588_CLKGATE_CON(0), 3, GFLAGS), 698 COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, 699 RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, 700 RK3588_CLKGATE_CON(0), 4, GFLAGS), 701 COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, 702 RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, 703 RK3588_CLKGATE_CON(0), 5, GFLAGS), 704 COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, 705 RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, 706 RK3588_CLKGATE_CON(0), 6, GFLAGS), 707 COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, 708 RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, 709 RK3588_CLKGATE_CON(0), 7, GFLAGS), 710 COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, 711 RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, 712 RK3588_CLKGATE_CON(0), 8, GFLAGS), 713 COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, 714 RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, 715 RK3588_CLKGATE_CON(0), 9, GFLAGS), 716 COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, 717 RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, 718 RK3588_CLKGATE_CON(0), 10, GFLAGS), 719 COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0, 720 RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, 721 RK3588_CLKGATE_CON(0), 11, GFLAGS), 722 COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, 723 RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, 724 RK3588_CLKGATE_CON(0), 12, GFLAGS), 725 COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, 726 RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, 727 RK3588_CLKGATE_CON(0), 13, GFLAGS), 728 COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, 729 RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, 730 RK3588_CLKGATE_CON(0), 14, GFLAGS), 731 COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, 732 RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, 733 RK3588_CLKGATE_CON(0), 15, GFLAGS), 734 COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, 735 RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, 736 RK3588_CLKGATE_CON(1), 10, GFLAGS), 737 COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, 738 RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, 739 RK3588_CLKGATE_CON(1), 11, GFLAGS), 740 COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, 741 RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, 742 RK3588_CLKGATE_CON(1), 12, GFLAGS), 743 COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 744 RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, 745 RK3588_CLKGATE_CON(1), 13, GFLAGS), 746 COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, 747 RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, 748 RK3588_CLKGATE_CON(1), 14, GFLAGS), 749 COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, 750 RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, 751 RK3588_CLKGATE_CON(1), 0, GFLAGS), 752 COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 753 RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, 754 RK3588_CLKGATE_CON(1), 1, GFLAGS), 755 COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, 756 RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, 757 RK3588_CLKGATE_CON(1), 2, GFLAGS), 758 COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, 759 RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, 760 RK3588_CLKGATE_CON(5), 9, GFLAGS), 761 COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, 762 RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, 763 RK3588_CLKGATE_CON(5), 10, GFLAGS), 764 COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, 765 RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, 766 RK3588_CLKGATE_CON(5), 11, GFLAGS), 767 COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, 768 RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, 769 RK3588_CLKGATE_CON(5), 12, GFLAGS), 770 COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, 771 RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, 772 RK3588_CLKGATE_CON(5), 13, GFLAGS), 773 COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, 774 RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, 775 RK3588_CLKGATE_CON(5), 3, GFLAGS), 776 COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, CLK_IS_CRITICAL, 777 RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, 778 RK3588_CLKGATE_CON(5), 4, GFLAGS), 779 COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, CLK_IS_CRITICAL, 780 RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, 781 RK3588_CLKGATE_CON(5), 5, GFLAGS), 782 COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, 783 RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, 784 RK3588_CLKGATE_CON(5), 6, GFLAGS), 785 GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, 786 RK3588_CLKGATE_CON(3), 14, GFLAGS), 787 GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, 788 RK3588_CLKGATE_CON(4), 3, GFLAGS), 789 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, 790 RK3588_CLKGATE_CON(1), 6, GFLAGS), 791 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, 792 RK3588_CLKGATE_CON(1), 8, GFLAGS), 793 GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, 794 RK3588_CLKGATE_CON(5), 0, GFLAGS), 795 796 /* bigcore0 */ 797 COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, 798 CLK_IS_CRITICAL, 799 RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS, 800 RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS), 801 GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0, 802 RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS), 803 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0, 804 RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS), 805 GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0, 806 RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS), 807 808 /* bigcore1 */ 809 COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, 810 CLK_IS_CRITICAL, 811 RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS, 812 RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS), 813 GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0, 814 RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS), 815 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0, 816 RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS), 817 GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0, 818 RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS), 819 820 /* dsu */ 821 COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, 822 RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS, 823 RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS), 824 COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, 825 RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 826 RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS), 827 COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, 828 RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 829 RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS), 830 COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL, 831 RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 832 RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS), 833 COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL, 834 RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 835 RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS), 836 COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL, 837 RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 838 RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS), 839 COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL, 840 RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 841 RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS), 842 COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL, 843 RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 844 RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS), 845 COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL, 846 RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 847 RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS), 848 COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 849 RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS, 850 RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS), 851 COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, 852 RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, 853 RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS), 854 COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 855 RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS, 856 RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS), 857 GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0, 858 RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS), 859 GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL, 860 RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS), 861 GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL, 862 RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS), 863 GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED, 864 RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS), 865 GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED, 866 RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS), 867 GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0, 868 RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS), 869 GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0, 870 RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS), 871 872 /* audio */ 873 COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, 874 RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, 875 RK3588_CLKGATE_CON(7), 0, GFLAGS), 876 COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, 877 RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, 878 RK3588_CLKGATE_CON(7), 1, GFLAGS), 879 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0, 880 RK3588_CLKGATE_CON(7), 12, GFLAGS), 881 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0, 882 RK3588_CLKGATE_CON(7), 13, GFLAGS), 883 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0, 884 RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS, 885 RK3588_CLKGATE_CON(7), 14, GFLAGS), 886 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", 887 CLK_SET_RATE_PARENT, 888 RK3588_CLKSEL_CON(29), 0, 889 RK3588_CLKGATE_CON(7), 15, GFLAGS, 890 &rk3588_i2s2_2ch_fracmux), 891 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, 892 RK3588_CLKGATE_CON(8), 0, GFLAGS), 893 MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT, 894 RK3588_CLKSEL_CON(30), 2, 1, MFLAGS), 895 896 COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0, 897 RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, 898 RK3588_CLKGATE_CON(8), 1, GFLAGS), 899 COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", 900 CLK_SET_RATE_PARENT, 901 RK3588_CLKSEL_CON(31), 0, 902 RK3588_CLKGATE_CON(8), 2, GFLAGS, 903 &rk3588_i2s3_2ch_fracmux), 904 GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0, 905 RK3588_CLKGATE_CON(8), 3, GFLAGS), 906 GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0, 907 RK3588_CLKGATE_CON(8), 4, GFLAGS), 908 MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT, 909 RK3588_CLKSEL_CON(32), 2, 1, MFLAGS), 910 GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0, 911 RK3588_CLKGATE_CON(7), 11, GFLAGS), 912 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0, 913 RK3588_CLKGATE_CON(7), 4, GFLAGS), 914 915 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0, 916 RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS, 917 RK3588_CLKGATE_CON(7), 5, GFLAGS), 918 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", 919 CLK_SET_RATE_PARENT, 920 RK3588_CLKSEL_CON(25), 0, 921 RK3588_CLKGATE_CON(7), 6, GFLAGS, 922 &rk3588_i2s0_8ch_tx_fracmux), 923 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, 924 RK3588_CLKGATE_CON(7), 7, GFLAGS), 925 926 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0, 927 RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS, 928 RK3588_CLKGATE_CON(7), 8, GFLAGS), 929 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", 930 CLK_SET_RATE_PARENT, 931 RK3588_CLKSEL_CON(27), 0, 932 RK3588_CLKGATE_CON(7), 9, GFLAGS, 933 &rk3588_i2s0_8ch_rx_fracmux), 934 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, 935 RK3588_CLKGATE_CON(7), 10, GFLAGS), 936 MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT, 937 RK3588_CLKSEL_CON(28), 2, 2, MFLAGS), 938 939 GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, 940 RK3588_CLKGATE_CON(9), 6, GFLAGS), 941 COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0, 942 RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS, 943 RK3588_CLKGATE_CON(9), 7, GFLAGS), 944 945 GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0, 946 RK3588_CLKGATE_CON(8), 14, GFLAGS), 947 COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0, 948 RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS, 949 RK3588_CLKGATE_CON(8), 15, GFLAGS), 950 COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", 951 CLK_SET_RATE_PARENT, 952 RK3588_CLKSEL_CON(33), 0, 953 RK3588_CLKGATE_CON(9), 0, GFLAGS, 954 &rk3588_spdif0_fracmux), 955 GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0, 956 RK3588_CLKGATE_CON(9), 1, GFLAGS), 957 958 GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0, 959 RK3588_CLKGATE_CON(9), 2, GFLAGS), 960 COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0, 961 RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS, 962 RK3588_CLKGATE_CON(9), 3, GFLAGS), 963 COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", 964 CLK_SET_RATE_PARENT, 965 RK3588_CLKSEL_CON(35), 0, 966 RK3588_CLKGATE_CON(9), 4, GFLAGS, 967 &rk3588_spdif1_fracmux), 968 GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0, 969 RK3588_CLKGATE_CON(9), 5, GFLAGS), 970 971 COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0, 972 RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS, 973 RK3588_CLKGATE_CON(68), 0, GFLAGS), 974 COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0, 975 RK3588_CLKSEL_CON(163), 7, 2, MFLAGS, 976 RK3588_CLKGATE_CON(68), 3, GFLAGS), 977 978 /* bus */ 979 COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, 980 RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, 981 RK3588_CLKGATE_CON(10), 0, GFLAGS), 982 983 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0, 984 RK3588_CLKGATE_CON(16), 11, GFLAGS), 985 GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, 986 RK3588_CLKGATE_CON(16), 12, GFLAGS), 987 GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, 988 RK3588_CLKGATE_CON(16), 13, GFLAGS), 989 GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, 990 RK3588_CLKGATE_CON(19), 3, GFLAGS), 991 GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, 992 RK3588_CLKGATE_CON(19), 4, GFLAGS), 993 GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, 994 RK3588_CLKGATE_CON(19), 5, GFLAGS), 995 996 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0, 997 RK3588_CLKGATE_CON(15), 3, GFLAGS), 998 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, 999 RK3588_CLKSEL_CON(59), 12, 2, MFLAGS, 1000 RK3588_CLKGATE_CON(15), 4, GFLAGS), 1001 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, 1002 RK3588_CLKGATE_CON(15), 5, GFLAGS), 1003 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0, 1004 RK3588_CLKGATE_CON(15), 6, GFLAGS), 1005 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, 1006 RK3588_CLKSEL_CON(59), 14, 2, MFLAGS, 1007 RK3588_CLKGATE_CON(15), 7, GFLAGS), 1008 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, 1009 RK3588_CLKGATE_CON(15), 8, GFLAGS), 1010 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0, 1011 RK3588_CLKGATE_CON(15), 9, GFLAGS), 1012 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0, 1013 RK3588_CLKSEL_CON(60), 0, 2, MFLAGS, 1014 RK3588_CLKGATE_CON(15), 10, GFLAGS), 1015 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, 1016 RK3588_CLKGATE_CON(15), 11, GFLAGS), 1017 1018 GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0, 1019 RK3588_CLKGATE_CON(15), 12, GFLAGS), 1020 GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0, 1021 RK3588_CLKGATE_CON(15), 13, GFLAGS), 1022 COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0, 1023 RK3588_CLKSEL_CON(60), 2, 1, MFLAGS, 1024 RK3588_CLKGATE_CON(15), 14, GFLAGS), 1025 GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0, 1026 RK3588_CLKGATE_CON(15), 15, GFLAGS), 1027 GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0, 1028 RK3588_CLKGATE_CON(16), 0, GFLAGS), 1029 GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0, 1030 RK3588_CLKGATE_CON(16), 1, GFLAGS), 1031 GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0, 1032 RK3588_CLKGATE_CON(16), 2, GFLAGS), 1033 GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0, 1034 RK3588_CLKGATE_CON(16), 3, GFLAGS), 1035 GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0, 1036 RK3588_CLKGATE_CON(16), 4, GFLAGS), 1037 GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0, 1038 RK3588_CLKGATE_CON(16), 5, GFLAGS), 1039 GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0, 1040 RK3588_CLKGATE_CON(16), 6, GFLAGS), 1041 GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0, 1042 RK3588_CLKGATE_CON(16), 7, GFLAGS), 1043 GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0, 1044 RK3588_CLKGATE_CON(16), 8, GFLAGS), 1045 GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0, 1046 RK3588_CLKGATE_CON(16), 9, GFLAGS), 1047 GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0, 1048 RK3588_CLKGATE_CON(16), 10, GFLAGS), 1049 1050 GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0, 1051 RK3588_CLKGATE_CON(15), 0, GFLAGS), 1052 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, 1053 RK3588_CLKGATE_CON(15), 1, GFLAGS), 1054 1055 GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0, 1056 RK3588_CLKGATE_CON(11), 8, GFLAGS), 1057 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, 1058 RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS, 1059 RK3588_CLKGATE_CON(11), 9, GFLAGS), 1060 GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0, 1061 RK3588_CLKGATE_CON(11), 10, GFLAGS), 1062 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, 1063 RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS, 1064 RK3588_CLKGATE_CON(11), 11, GFLAGS), 1065 GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0, 1066 RK3588_CLKGATE_CON(11), 12, GFLAGS), 1067 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, 1068 RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS, 1069 RK3588_CLKGATE_CON(11), 13, GFLAGS), 1070 1071 GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, 1072 RK3588_CLKGATE_CON(17), 6, GFLAGS), 1073 GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0, 1074 RK3588_CLKGATE_CON(17), 7, GFLAGS), 1075 COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, 1076 RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS, 1077 RK3588_CLKGATE_CON(17), 8, GFLAGS), 1078 GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, 1079 RK3588_CLKGATE_CON(10), 5, GFLAGS), 1080 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, 1081 RK3588_CLKGATE_CON(10), 6, GFLAGS), 1082 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, 1083 RK3588_CLKGATE_CON(10), 7, GFLAGS), 1084 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, 1085 RK3588_CLKGATE_CON(10), 3, GFLAGS), 1086 1087 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0, 1088 RK3588_CLKGATE_CON(16), 14, GFLAGS), 1089 COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0, 1090 RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS, 1091 RK3588_CLKGATE_CON(16), 15, GFLAGS), 1092 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0, 1093 RK3588_CLKGATE_CON(17), 0, GFLAGS), 1094 COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0, 1095 RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS, 1096 RK3588_CLKGATE_CON(17), 1, GFLAGS), 1097 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0, 1098 RK3588_CLKGATE_CON(17), 2, GFLAGS), 1099 COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0, 1100 RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS, 1101 RK3588_CLKGATE_CON(17), 3, GFLAGS), 1102 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0, 1103 RK3588_CLKGATE_CON(17), 4, GFLAGS), 1104 COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0, 1105 RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS, 1106 RK3588_CLKGATE_CON(17), 5, GFLAGS), 1107 1108 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0, 1109 RK3588_CLKGATE_CON(10), 8, GFLAGS), 1110 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0, 1111 RK3588_CLKGATE_CON(10), 9, GFLAGS), 1112 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0, 1113 RK3588_CLKGATE_CON(10), 10, GFLAGS), 1114 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0, 1115 RK3588_CLKGATE_CON(10), 11, GFLAGS), 1116 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0, 1117 RK3588_CLKGATE_CON(10), 12, GFLAGS), 1118 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0, 1119 RK3588_CLKGATE_CON(10), 13, GFLAGS), 1120 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0, 1121 RK3588_CLKGATE_CON(10), 14, GFLAGS), 1122 GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0, 1123 RK3588_CLKGATE_CON(10), 15, GFLAGS), 1124 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0, 1125 RK3588_CLKSEL_CON(38), 6, 1, MFLAGS, 1126 RK3588_CLKGATE_CON(11), 0, GFLAGS), 1127 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0, 1128 RK3588_CLKSEL_CON(38), 7, 1, MFLAGS, 1129 RK3588_CLKGATE_CON(11), 1, GFLAGS), 1130 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0, 1131 RK3588_CLKSEL_CON(38), 8, 1, MFLAGS, 1132 RK3588_CLKGATE_CON(11), 2, GFLAGS), 1133 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0, 1134 RK3588_CLKSEL_CON(38), 9, 1, MFLAGS, 1135 RK3588_CLKGATE_CON(11), 3, GFLAGS), 1136 COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0, 1137 RK3588_CLKSEL_CON(38), 10, 1, MFLAGS, 1138 RK3588_CLKGATE_CON(11), 4, GFLAGS), 1139 COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0, 1140 RK3588_CLKSEL_CON(38), 11, 1, MFLAGS, 1141 RK3588_CLKGATE_CON(11), 5, GFLAGS), 1142 COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0, 1143 RK3588_CLKSEL_CON(38), 12, 1, MFLAGS, 1144 RK3588_CLKGATE_CON(11), 6, GFLAGS), 1145 COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0, 1146 RK3588_CLKSEL_CON(38), 13, 1, MFLAGS, 1147 RK3588_CLKGATE_CON(11), 7, GFLAGS), 1148 1149 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0, 1150 RK3588_CLKGATE_CON(18), 9, GFLAGS), 1151 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, 1152 RK3588_CLKGATE_CON(18), 10, GFLAGS), 1153 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, 1154 RK3588_CLKGATE_CON(18), 11, GFLAGS), 1155 GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, 1156 RK3588_CLKGATE_CON(18), 13, GFLAGS), 1157 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, 1158 RK3588_CLKGATE_CON(18), 12, GFLAGS), 1159 1160 GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0, 1161 RK3588_CLKGATE_CON(11), 14, GFLAGS), 1162 COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, 1163 RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS, 1164 RK3588_CLKGATE_CON(11), 15, GFLAGS), 1165 1166 GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0, 1167 RK3588_CLKGATE_CON(14), 6, GFLAGS), 1168 GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0, 1169 RK3588_CLKGATE_CON(14), 7, GFLAGS), 1170 GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0, 1171 RK3588_CLKGATE_CON(14), 8, GFLAGS), 1172 GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0, 1173 RK3588_CLKGATE_CON(14), 9, GFLAGS), 1174 GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0, 1175 RK3588_CLKGATE_CON(14), 10, GFLAGS), 1176 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0, 1177 RK3588_CLKSEL_CON(59), 2, 2, MFLAGS, 1178 RK3588_CLKGATE_CON(14), 11, GFLAGS), 1179 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0, 1180 RK3588_CLKSEL_CON(59), 4, 2, MFLAGS, 1181 RK3588_CLKGATE_CON(14), 12, GFLAGS), 1182 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0, 1183 RK3588_CLKSEL_CON(59), 6, 2, MFLAGS, 1184 RK3588_CLKGATE_CON(14), 13, GFLAGS), 1185 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0, 1186 RK3588_CLKSEL_CON(59), 8, 2, MFLAGS, 1187 RK3588_CLKGATE_CON(14), 14, GFLAGS), 1188 COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0, 1189 RK3588_CLKSEL_CON(59), 10, 2, MFLAGS, 1190 RK3588_CLKGATE_CON(14), 15, GFLAGS), 1191 1192 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED, 1193 RK3588_CLKGATE_CON(18), 6, GFLAGS), 1194 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0, 1195 RK3588_CLKGATE_CON(12), 0, GFLAGS), 1196 COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0, 1197 RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS, 1198 RK3588_CLKGATE_CON(12), 1, GFLAGS), 1199 1200 GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0, 1201 RK3588_CLKGATE_CON(12), 2, GFLAGS), 1202 GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0, 1203 RK3588_CLKGATE_CON(12), 3, GFLAGS), 1204 GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0, 1205 RK3588_CLKGATE_CON(12), 4, GFLAGS), 1206 GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0, 1207 RK3588_CLKGATE_CON(12), 5, GFLAGS), 1208 GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0, 1209 RK3588_CLKGATE_CON(12), 6, GFLAGS), 1210 GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0, 1211 RK3588_CLKGATE_CON(12), 7, GFLAGS), 1212 GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0, 1213 RK3588_CLKGATE_CON(12), 8, GFLAGS), 1214 GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0, 1215 RK3588_CLKGATE_CON(12), 9, GFLAGS), 1216 GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0, 1217 RK3588_CLKGATE_CON(12), 10, GFLAGS), 1218 1219 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, 1220 RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS, 1221 RK3588_CLKGATE_CON(12), 11, GFLAGS), 1222 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 1223 RK3588_CLKSEL_CON(42), 0, 1224 RK3588_CLKGATE_CON(12), 12, GFLAGS, 1225 &rk3588_uart1_fracmux), 1226 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, 1227 RK3588_CLKGATE_CON(12), 13, GFLAGS), 1228 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, 1229 RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS, 1230 RK3588_CLKGATE_CON(12), 14, GFLAGS), 1231 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 1232 RK3588_CLKSEL_CON(44), 0, 1233 RK3588_CLKGATE_CON(12), 15, GFLAGS, 1234 &rk3588_uart2_fracmux), 1235 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, 1236 RK3588_CLKGATE_CON(13), 0, GFLAGS), 1237 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, 1238 RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS, 1239 RK3588_CLKGATE_CON(13), 1, GFLAGS), 1240 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 1241 RK3588_CLKSEL_CON(46), 0, 1242 RK3588_CLKGATE_CON(13), 2, GFLAGS, 1243 &rk3588_uart3_fracmux), 1244 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, 1245 RK3588_CLKGATE_CON(13), 3, GFLAGS), 1246 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, 1247 RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS, 1248 RK3588_CLKGATE_CON(13), 4, GFLAGS), 1249 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 1250 RK3588_CLKSEL_CON(48), 0, 1251 RK3588_CLKGATE_CON(13), 5, GFLAGS, 1252 &rk3588_uart4_fracmux), 1253 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, 1254 RK3588_CLKGATE_CON(13), 6, GFLAGS), 1255 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, 1256 RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS, 1257 RK3588_CLKGATE_CON(13), 7, GFLAGS), 1258 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 1259 RK3588_CLKSEL_CON(50), 0, 1260 RK3588_CLKGATE_CON(13), 8, GFLAGS, 1261 &rk3588_uart5_fracmux), 1262 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, 1263 RK3588_CLKGATE_CON(13), 9, GFLAGS), 1264 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, 1265 RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS, 1266 RK3588_CLKGATE_CON(13), 10, GFLAGS), 1267 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, 1268 RK3588_CLKSEL_CON(52), 0, 1269 RK3588_CLKGATE_CON(13), 11, GFLAGS, 1270 &rk3588_uart6_fracmux), 1271 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, 1272 RK3588_CLKGATE_CON(13), 12, GFLAGS), 1273 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, 1274 RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS, 1275 RK3588_CLKGATE_CON(13), 13, GFLAGS), 1276 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, 1277 RK3588_CLKSEL_CON(54), 0, 1278 RK3588_CLKGATE_CON(13), 14, GFLAGS, 1279 &rk3588_uart7_fracmux), 1280 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, 1281 RK3588_CLKGATE_CON(13), 15, GFLAGS), 1282 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, 1283 RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS, 1284 RK3588_CLKGATE_CON(14), 0, GFLAGS), 1285 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, 1286 RK3588_CLKSEL_CON(56), 0, 1287 RK3588_CLKGATE_CON(14), 1, GFLAGS, 1288 &rk3588_uart8_fracmux), 1289 GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, 1290 RK3588_CLKGATE_CON(14), 2, GFLAGS), 1291 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, 1292 RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS, 1293 RK3588_CLKGATE_CON(14), 3, GFLAGS), 1294 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, 1295 RK3588_CLKSEL_CON(58), 0, 1296 RK3588_CLKGATE_CON(14), 4, GFLAGS, 1297 &rk3588_uart9_fracmux), 1298 GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, 1299 RK3588_CLKGATE_CON(14), 5, GFLAGS), 1300 1301 /* center */ 1302 COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, 1303 CLK_IS_CRITICAL, 1304 RK3588_CLKSEL_CON(165), 0, 2, MFLAGS, 1305 RK3588_CLKGATE_CON(69), 0, GFLAGS), 1306 COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, 1307 CLK_IS_CRITICAL, 1308 RK3588_CLKSEL_CON(165), 2, 2, MFLAGS, 1309 RK3588_CLKGATE_CON(69), 1, GFLAGS), 1310 COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, 1311 CLK_IS_CRITICAL, 1312 RK3588_CLKSEL_CON(165), 4, 2, MFLAGS, 1313 RK3588_CLKGATE_CON(69), 2, GFLAGS), 1314 COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, 1315 CLK_IS_CRITICAL, 1316 RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 1317 RK3588_CLKGATE_CON(69), 3, GFLAGS), 1318 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL, 1319 RK3588_CLKGATE_CON(69), 5, GFLAGS), 1320 GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL, 1321 RK3588_CLKGATE_CON(69), 6, GFLAGS), 1322 COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, 1323 CLK_IS_CRITICAL, 1324 RK3588_CLKSEL_CON(165), 8, 2, MFLAGS, 1325 RK3588_CLKGATE_CON(69), 8, GFLAGS), 1326 COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, 1327 CLK_IS_CRITICAL, 1328 RK3588_CLKSEL_CON(165), 10, 2, MFLAGS, 1329 RK3588_CLKGATE_CON(69), 9, GFLAGS), 1330 GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL, 1331 RK3588_CLKGATE_CON(69), 14, GFLAGS), 1332 COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED, 1333 RK3588_CLKSEL_CON(165), 12, 1, MFLAGS, 1334 RK3588_CLKGATE_CON(69), 15, GFLAGS), 1335 GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, 1336 RK3588_CLKGATE_CON(70), 0, GFLAGS), 1337 GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, 1338 RK3588_CLKGATE_CON(70), 1, GFLAGS), 1339 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, 1340 RK3588_CLKGATE_CON(70), 2, GFLAGS), 1341 COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, 1342 RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, 1343 RK3588_CLKGATE_CON(70), 4, GFLAGS), 1344 GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, 1345 RK3588_CLKGATE_CON(70), 7, GFLAGS), 1346 GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, 1347 RK3588_CLKGATE_CON(70), 8, GFLAGS), 1348 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL, 1349 RK3588_CLKGATE_CON(70), 9, GFLAGS), 1350 GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL, 1351 RK3588_CLKGATE_CON(70), 10, GFLAGS), 1352 1353 /* gpu */ 1354 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0, 1355 RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS, 1356 RK3588_CLKGATE_CON(66), 1, GFLAGS), 1357 GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0, 1358 RK3588_CLKGATE_CON(66), 4, GFLAGS), 1359 GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0, 1360 RK3588_CLKGATE_CON(66), 6, GFLAGS), 1361 COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0, 1362 RK3588_CLKSEL_CON(159), 0, 5, DFLAGS, 1363 RK3588_CLKGATE_CON(66), 7, GFLAGS), 1364 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, 1365 RK3588_CLKGATE_CON(67), 0, GFLAGS), 1366 GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0, 1367 RK3588_CLKGATE_CON(67), 1, GFLAGS), 1368 1369 /* isp1 */ 1370 COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0, 1371 RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS, 1372 RK3588_CLKGATE_CON(26), 0, GFLAGS), 1373 COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0, 1374 RK3588_CLKSEL_CON(67), 7, 2, MFLAGS, 1375 RK3588_CLKGATE_CON(26), 1, GFLAGS), 1376 COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0, 1377 RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS, 1378 RK3588_CLKGATE_CON(26), 2, GFLAGS), 1379 GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0, 1380 RK3588_CLKGATE_CON(26), 3, GFLAGS), 1381 GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0, 1382 RK3588_CLKGATE_CON(26), 4, GFLAGS), 1383 1384 /* npu */ 1385 COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, 1386 RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, 1387 RK3588_CLKGATE_CON(29), 0, GFLAGS), 1388 COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, 1389 RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, 1390 RK3588_CLKGATE_CON(29), 1, GFLAGS), 1391 COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, 1392 RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, 1393 RK3588_CLKGATE_CON(29), 4, GFLAGS), 1394 GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0, 1395 RK3588_CLKGATE_CON(27), 0, GFLAGS), 1396 GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0, 1397 RK3588_CLKGATE_CON(27), 2, GFLAGS), 1398 GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0, 1399 RK3588_CLKGATE_CON(28), 0, GFLAGS), 1400 GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0, 1401 RK3588_CLKGATE_CON(28), 2, GFLAGS), 1402 COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, 1403 RK3588_CLKSEL_CON(74), 5, 2, MFLAGS, 1404 RK3588_CLKGATE_CON(30), 1, GFLAGS), 1405 GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, 1406 RK3588_CLKGATE_CON(30), 3, GFLAGS), 1407 COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, 1408 RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS, 1409 RK3588_CLKGATE_CON(30), 5, GFLAGS), 1410 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0, 1411 RK3588_CLKGATE_CON(29), 12, GFLAGS), 1412 GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED, 1413 RK3588_CLKGATE_CON(29), 13, GFLAGS), 1414 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, 1415 RK3588_CLKGATE_CON(29), 14, GFLAGS), 1416 GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0, 1417 RK3588_CLKGATE_CON(29), 15, GFLAGS), 1418 GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0, 1419 RK3588_CLKGATE_CON(30), 6, GFLAGS), 1420 GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0, 1421 RK3588_CLKGATE_CON(30), 8, GFLAGS), 1422 GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0, 1423 RK3588_CLKGATE_CON(29), 6, GFLAGS), 1424 COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0, 1425 RK3588_CLKSEL_CON(74), 3, 1, MFLAGS, 1426 RK3588_CLKGATE_CON(29), 7, GFLAGS), 1427 GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, 1428 RK3588_CLKGATE_CON(29), 8, GFLAGS), 1429 GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, 1430 RK3588_CLKGATE_CON(29), 9, GFLAGS), 1431 GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0, 1432 RK3588_CLKGATE_CON(29), 10, GFLAGS), 1433 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, 1434 RK3588_CLKGATE_CON(29), 11, GFLAGS), 1435 1436 /* nvm */ 1437 COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, 1438 RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, 1439 RK3588_CLKGATE_CON(31), 0, GFLAGS), 1440 COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, 1441 RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, 1442 RK3588_CLKGATE_CON(31), 1, GFLAGS), 1443 GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, 1444 RK3588_CLKGATE_CON(31), 5, GFLAGS), 1445 COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0, 1446 RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS, 1447 RK3588_CLKGATE_CON(31), 6, GFLAGS), 1448 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, 1449 RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS, 1450 RK3588_CLKGATE_CON(31), 7, GFLAGS), 1451 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, 1452 RK3588_CLKGATE_CON(31), 8, GFLAGS), 1453 1454 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0, 1455 RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS, 1456 RK3588_CLKGATE_CON(31), 9, GFLAGS), 1457 1458 /* php */ 1459 COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0, 1460 RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, 1461 RK3588_CLKGATE_CON(34), 10, GFLAGS), 1462 COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0, 1463 RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, 1464 RK3588_CLKGATE_CON(34), 11, GFLAGS), 1465 COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0, 1466 RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS, 1467 RK3588_CLKGATE_CON(35), 5, GFLAGS), 1468 COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0, 1469 RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS, 1470 RK3588_CLKGATE_CON(35), 6, GFLAGS), 1471 1472 COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, 1473 RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, 1474 RK3588_CLKGATE_CON(32), 6, GFLAGS), 1475 COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, 1476 RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, 1477 RK3588_CLKGATE_CON(32), 7, GFLAGS), 1478 COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, 1479 RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, 1480 RK3588_CLKGATE_CON(32), 0, GFLAGS), 1481 GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, 1482 RK3588_CLKGATE_CON(34), 6, GFLAGS), 1483 GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, 1484 RK3588_CLKGATE_CON(32), 8, GFLAGS), 1485 GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, 1486 RK3588_CLKGATE_CON(34), 7, GFLAGS), 1487 GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, 1488 RK3588_CLKGATE_CON(34), 8, GFLAGS), 1489 GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0, 1490 RK3588_CLKGATE_CON(32), 13, GFLAGS), 1491 GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0, 1492 RK3588_CLKGATE_CON(32), 14, GFLAGS), 1493 GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0, 1494 RK3588_CLKGATE_CON(32), 15, GFLAGS), 1495 GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0, 1496 RK3588_CLKGATE_CON(33), 0, GFLAGS), 1497 GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0, 1498 RK3588_CLKGATE_CON(33), 1, GFLAGS), 1499 GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0, 1500 RK3588_CLKGATE_CON(33), 2, GFLAGS), 1501 GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0, 1502 RK3588_CLKGATE_CON(33), 3, GFLAGS), 1503 GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0, 1504 RK3588_CLKGATE_CON(33), 4, GFLAGS), 1505 GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0, 1506 RK3588_CLKGATE_CON(33), 5, GFLAGS), 1507 GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0, 1508 RK3588_CLKGATE_CON(33), 6, GFLAGS), 1509 GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0, 1510 RK3588_CLKGATE_CON(33), 7, GFLAGS), 1511 GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0, 1512 RK3588_CLKGATE_CON(33), 8, GFLAGS), 1513 GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0, 1514 RK3588_CLKGATE_CON(33), 9, GFLAGS), 1515 GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0, 1516 RK3588_CLKGATE_CON(33), 10, GFLAGS), 1517 GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0, 1518 RK3588_CLKGATE_CON(33), 11, GFLAGS), 1519 GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0, 1520 RK3588_CLKGATE_CON(33), 12, GFLAGS), 1521 GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0, 1522 RK3588_CLKGATE_CON(33), 13, GFLAGS), 1523 GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0, 1524 RK3588_CLKGATE_CON(33), 14, GFLAGS), 1525 GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0, 1526 RK3588_CLKGATE_CON(33), 15, GFLAGS), 1527 GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0, 1528 RK3588_CLKGATE_CON(34), 0, GFLAGS), 1529 GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0, 1530 RK3588_CLKGATE_CON(34), 1, GFLAGS), 1531 GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0, 1532 RK3588_CLKGATE_CON(34), 2, GFLAGS), 1533 GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0, 1534 RK3588_CLKGATE_CON(34), 3, GFLAGS), 1535 GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0, 1536 RK3588_CLKGATE_CON(34), 4, GFLAGS), 1537 GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0, 1538 RK3588_CLKGATE_CON(34), 5, GFLAGS), 1539 GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0, 1540 RK3588_CLKGATE_CON(37), 0, GFLAGS), 1541 GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0, 1542 RK3588_CLKGATE_CON(37), 1, GFLAGS), 1543 GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0, 1544 RK3588_CLKGATE_CON(37), 2, GFLAGS), 1545 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0, 1546 RK3588_CLKGATE_CON(32), 3, GFLAGS), 1547 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0, 1548 RK3588_CLKGATE_CON(32), 4, GFLAGS), 1549 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, 1550 RK3588_CLKGATE_CON(32), 10, GFLAGS), 1551 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, 1552 RK3588_CLKGATE_CON(32), 11, GFLAGS), 1553 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0, 1554 RK3588_CLKGATE_CON(37), 4, GFLAGS), 1555 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0, 1556 RK3588_CLKGATE_CON(37), 5, GFLAGS), 1557 GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0, 1558 RK3588_CLKGATE_CON(37), 6, GFLAGS), 1559 GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0, 1560 RK3588_CLKGATE_CON(37), 7, GFLAGS), 1561 GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0, 1562 RK3588_CLKGATE_CON(37), 8, GFLAGS), 1563 GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0, 1564 RK3588_CLKGATE_CON(37), 9, GFLAGS), 1565 COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, 1566 RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS, 1567 RK3588_CLKGATE_CON(37), 10, GFLAGS), 1568 COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, 1569 RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS, 1570 RK3588_CLKGATE_CON(37), 11, GFLAGS), 1571 COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0, 1572 RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS, 1573 RK3588_CLKGATE_CON(37), 12, GFLAGS), 1574 GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0, 1575 RK3588_CLKGATE_CON(35), 7, GFLAGS), 1576 GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0, 1577 RK3588_CLKGATE_CON(35), 8, GFLAGS), 1578 GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0, 1579 RK3588_CLKGATE_CON(35), 9, GFLAGS), 1580 COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0, 1581 RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS, 1582 RK3588_CLKGATE_CON(35), 10, GFLAGS), 1583 GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0, 1584 RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS), 1585 GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0, 1586 RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS), 1587 GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0, 1588 RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS), 1589 GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0, 1590 RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS), 1591 1592 /* rga */ 1593 COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0, 1594 RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS, 1595 RK3588_CLKGATE_CON(76), 6, GFLAGS), 1596 COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0, 1597 RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS, 1598 RK3588_CLKGATE_CON(76), 0, GFLAGS), 1599 COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0, 1600 RK3588_CLKSEL_CON(174), 7, 2, MFLAGS, 1601 RK3588_CLKGATE_CON(76), 1, GFLAGS), 1602 GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, 1603 RK3588_CLKGATE_CON(76), 4, GFLAGS), 1604 GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, 1605 RK3588_CLKGATE_CON(76), 5, GFLAGS), 1606 1607 /* vdec */ 1608 COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0, 1609 RK3588_CLKSEL_CON(89), 0, 2, MFLAGS, 1610 RK3588_CLKGATE_CON(40), 0, GFLAGS), 1611 COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0, 1612 RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS, 1613 RK3588_CLKGATE_CON(40), 1, GFLAGS), 1614 COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0, 1615 RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS, 1616 RK3588_CLKGATE_CON(40), 2, GFLAGS), 1617 COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0, 1618 RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS, 1619 RK3588_CLKGATE_CON(40), 7, GFLAGS), 1620 COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0, 1621 RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS, 1622 RK3588_CLKGATE_CON(40), 8, GFLAGS), 1623 COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0, 1624 RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS, 1625 RK3588_CLKGATE_CON(40), 9, GFLAGS), 1626 COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0, 1627 RK3588_CLKSEL_CON(93), 0, 2, MFLAGS, 1628 RK3588_CLKGATE_CON(41), 0, GFLAGS), 1629 COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0, 1630 RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS, 1631 RK3588_CLKGATE_CON(41), 1, GFLAGS), 1632 COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0, 1633 RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS, 1634 RK3588_CLKGATE_CON(41), 6, GFLAGS), 1635 COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0, 1636 RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS, 1637 RK3588_CLKGATE_CON(41), 7, GFLAGS), 1638 COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0, 1639 RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS, 1640 RK3588_CLKGATE_CON(41), 8, GFLAGS), 1641 1642 /* sdio */ 1643 COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0, 1644 RK3588_CLKSEL_CON(172), 0, 2, MFLAGS, 1645 RK3588_CLKGATE_CON(75), 0, GFLAGS), 1646 COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, 1647 RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS, 1648 RK3588_CLKGATE_CON(75), 3, GFLAGS), 1649 MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1), 1650 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1), 1651 1652 /* usb */ 1653 COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0, 1654 RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS, 1655 RK3588_CLKGATE_CON(42), 0, GFLAGS), 1656 COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0, 1657 RK3588_CLKSEL_CON(96), 6, 2, MFLAGS, 1658 RK3588_CLKGATE_CON(42), 1, GFLAGS), 1659 GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0, 1660 RK3588_CLKGATE_CON(42), 5, GFLAGS), 1661 GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0, 1662 RK3588_CLKGATE_CON(42), 6, GFLAGS), 1663 GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0, 1664 RK3588_CLKGATE_CON(42), 8, GFLAGS), 1665 GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0, 1666 RK3588_CLKGATE_CON(42), 9, GFLAGS), 1667 1668 /* vdpu */ 1669 COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, 1670 RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, 1671 RK3588_CLKGATE_CON(44), 0, GFLAGS), 1672 COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, 1673 RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, 1674 RK3588_CLKGATE_CON(44), 1, GFLAGS), 1675 COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, 1676 RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, 1677 RK3588_CLKGATE_CON(44), 2, GFLAGS), 1678 COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, 1679 RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, 1680 RK3588_CLKGATE_CON(44), 3, GFLAGS), 1681 GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0, 1682 RK3588_CLKGATE_CON(45), 4, GFLAGS), 1683 COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0, 1684 RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS, 1685 RK3588_CLKGATE_CON(45), 6, GFLAGS), 1686 GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0, 1687 RK3588_CLKGATE_CON(44), 11, GFLAGS), 1688 GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0, 1689 RK3588_CLKGATE_CON(44), 13, GFLAGS), 1690 GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0, 1691 RK3588_CLKGATE_CON(44), 15, GFLAGS), 1692 GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0, 1693 RK3588_CLKGATE_CON(45), 1, GFLAGS), 1694 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0, 1695 RK3588_CLKGATE_CON(45), 3, GFLAGS), 1696 GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0, 1697 RK3588_CLKGATE_CON(45), 7, GFLAGS), 1698 GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0, 1699 RK3588_CLKGATE_CON(45), 8, GFLAGS), 1700 COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0, 1701 RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS, 1702 RK3588_CLKGATE_CON(45), 9, GFLAGS), 1703 GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0, 1704 RK3588_CLKGATE_CON(45), 10, GFLAGS), 1705 GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0, 1706 RK3588_CLKGATE_CON(45), 11, GFLAGS), 1707 COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0, 1708 RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS, 1709 RK3588_CLKGATE_CON(45), 12, GFLAGS), 1710 GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0, 1711 RK3588_CLKGATE_CON(44), 9, GFLAGS), 1712 1713 /* venc */ 1714 COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, 1715 RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, 1716 RK3588_CLKGATE_CON(48), 0, GFLAGS), 1717 COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, 1718 RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, 1719 RK3588_CLKGATE_CON(48), 1, GFLAGS), 1720 COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0, 1721 RK3588_CLKSEL_CON(102), 0, 2, MFLAGS, 1722 RK3588_CLKGATE_CON(47), 0, GFLAGS), 1723 COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, 1724 RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, 1725 RK3588_CLKGATE_CON(47), 1, GFLAGS), 1726 GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, 1727 RK3588_CLKGATE_CON(47), 4, GFLAGS), 1728 GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, 1729 RK3588_CLKGATE_CON(47), 5, GFLAGS), 1730 COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, 1731 RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, 1732 RK3588_CLKGATE_CON(47), 6, GFLAGS), 1733 COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0, 1734 RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS, 1735 RK3588_CLKGATE_CON(48), 6, GFLAGS), 1736 1737 /* vi */ 1738 COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, 1739 RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, 1740 RK3588_CLKGATE_CON(49), 0, GFLAGS), 1741 COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, 1742 RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, 1743 RK3588_CLKGATE_CON(49), 1, GFLAGS), 1744 COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, 1745 RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, 1746 RK3588_CLKGATE_CON(49), 2, GFLAGS), 1747 COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, 1748 RK3588_CLKSEL_CON(108), 14, 2, MFLAGS, 1749 RK3588_CLKGATE_CON(51), 10, GFLAGS), 1750 GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, 1751 RK3588_CLKGATE_CON(51), 11, GFLAGS), 1752 GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0, 1753 RK3588_CLKGATE_CON(51), 12, GFLAGS), 1754 GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, 1755 RK3588_CLKGATE_CON(50), 4, GFLAGS), 1756 GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, 1757 RK3588_CLKGATE_CON(50), 5, GFLAGS), 1758 GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, 1759 RK3588_CLKGATE_CON(50), 6, GFLAGS), 1760 GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, 1761 RK3588_CLKGATE_CON(50), 7, GFLAGS), 1762 GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, 1763 RK3588_CLKGATE_CON(50), 8, GFLAGS), 1764 GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0, 1765 RK3588_CLKGATE_CON(50), 9, GFLAGS), 1766 GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0, 1767 RK3588_CLKGATE_CON(49), 14, GFLAGS), 1768 GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0, 1769 RK3588_CLKGATE_CON(49), 15, GFLAGS), 1770 COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0, 1771 RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, 1772 RK3588_CLKGATE_CON(50), 0, GFLAGS), 1773 GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0, 1774 RK3588_CLKGATE_CON(50), 1, GFLAGS), 1775 GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0, 1776 RK3588_CLKGATE_CON(50), 2, GFLAGS), 1777 COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0, 1778 RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS, 1779 RK3588_CLKGATE_CON(50), 3, GFLAGS), 1780 COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0, 1781 RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, 1782 RK3588_CLKGATE_CON(49), 9, GFLAGS), 1783 GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0, 1784 RK3588_CLKGATE_CON(49), 10, GFLAGS), 1785 GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0, 1786 RK3588_CLKGATE_CON(49), 11, GFLAGS), 1787 GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0, 1788 RK3588_CLKGATE_CON(49), 12, GFLAGS), 1789 GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0, 1790 RK3588_CLKGATE_CON(49), 13, GFLAGS), 1791 COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, 1792 RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, 1793 RK3588_CLKGATE_CON(49), 6, GFLAGS), 1794 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, 1795 RK3588_CLKGATE_CON(49), 7, GFLAGS), 1796 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, 1797 RK3588_CLKGATE_CON(49), 8, GFLAGS), 1798 1799 /* vo0 */ 1800 COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0, 1801 RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS, 1802 RK3588_CLKGATE_CON(55), 0, GFLAGS), 1803 COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0, 1804 RK3588_CLKSEL_CON(116), 6, 2, MFLAGS, 1805 RK3588_CLKGATE_CON(55), 1, GFLAGS), 1806 COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0, 1807 RK3588_CLKSEL_CON(116), 8, 2, MFLAGS, 1808 RK3588_CLKGATE_CON(55), 2, GFLAGS), 1809 COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0, 1810 RK3588_CLKSEL_CON(116), 10, 2, MFLAGS, 1811 RK3588_CLKGATE_CON(55), 3, GFLAGS), 1812 COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0, 1813 RK3588_CLKSEL_CON(116), 12, 2, MFLAGS, 1814 RK3588_CLKGATE_CON(55), 4, GFLAGS), 1815 GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, 1816 RK3588_CLKGATE_CON(56), 4, GFLAGS), 1817 GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, 1818 RK3588_CLKGATE_CON(56), 5, GFLAGS), 1819 GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, 1820 RK3588_CLKGATE_CON(56), 6, GFLAGS), 1821 GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, 1822 RK3588_CLKGATE_CON(56), 7, GFLAGS), 1823 GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, 1824 RK3588_CLKGATE_CON(56), 8, GFLAGS), 1825 GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, 1826 RK3588_CLKGATE_CON(56), 9, GFLAGS), 1827 GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, 1828 RK3588_CLKGATE_CON(55), 11, GFLAGS), 1829 GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, 1830 RK3588_CLKGATE_CON(55), 14, GFLAGS), 1831 GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, 1832 RK3588_CLKGATE_CON(56), 0, GFLAGS), 1833 GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, 1834 RK3588_CLKGATE_CON(56), 1, GFLAGS), 1835 COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, 1836 RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, 1837 RK3588_CLKGATE_CON(56), 11, GFLAGS), 1838 COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", 1839 CLK_SET_RATE_PARENT, 1840 RK3588_CLKSEL_CON(119), 0, 1841 RK3588_CLKGATE_CON(56), 12, GFLAGS, 1842 &rk3588_i2s4_8ch_tx_fracmux), 1843 GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, 1844 RK3588_CLKGATE_CON(56), 13, GFLAGS), 1845 COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0, 1846 RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, 1847 RK3588_CLKGATE_CON(56), 15, GFLAGS), 1848 COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", 1849 CLK_SET_RATE_PARENT, 1850 RK3588_CLKSEL_CON(121), 0, 1851 RK3588_CLKGATE_CON(57), 0, GFLAGS, 1852 &rk3588_i2s8_8ch_tx_fracmux), 1853 GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, 1854 RK3588_CLKGATE_CON(57), 1, GFLAGS), 1855 COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0, 1856 RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, 1857 RK3588_CLKGATE_CON(57), 3, GFLAGS), 1858 COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", 1859 CLK_SET_RATE_PARENT, 1860 RK3588_CLKSEL_CON(123), 0, 1861 RK3588_CLKGATE_CON(57), 4, GFLAGS, 1862 &rk3588_spdif2_dp0_fracmux), 1863 GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0, 1864 RK3588_CLKGATE_CON(57), 5, GFLAGS), 1865 GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0, 1866 RK3588_CLKGATE_CON(57), 6, GFLAGS), 1867 COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0, 1868 RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, 1869 RK3588_CLKGATE_CON(57), 8, GFLAGS), 1870 COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", 1871 CLK_SET_RATE_PARENT, 1872 RK3588_CLKSEL_CON(125), 0, 1873 RK3588_CLKGATE_CON(57), 9, GFLAGS, 1874 &rk3588_spdif5_dp1_fracmux), 1875 GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0, 1876 RK3588_CLKGATE_CON(57), 10, GFLAGS), 1877 GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0, 1878 RK3588_CLKGATE_CON(57), 11, GFLAGS), 1879 COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0, 1880 RK3588_CLKSEL_CON(117), 0, 8, DFLAGS, 1881 RK3588_CLKGATE_CON(56), 2, GFLAGS), 1882 COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0, 1883 RK3588_CLKSEL_CON(117), 8, 8, DFLAGS, 1884 RK3588_CLKGATE_CON(56), 3, GFLAGS), 1885 1886 /* vo1 */ 1887 COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, 1888 RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, 1889 RK3588_CLKGATE_CON(65), 9, GFLAGS), 1890 COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, 1891 RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, 1892 RK3588_CLKGATE_CON(59), 0, GFLAGS), 1893 COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, 1894 RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, 1895 RK3588_CLKGATE_CON(59), 1, GFLAGS), 1896 COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, 1897 RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, 1898 RK3588_CLKGATE_CON(59), 2, GFLAGS), 1899 COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, 1900 RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, 1901 RK3588_CLKGATE_CON(59), 3, GFLAGS), 1902 COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, 1903 RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, 1904 RK3588_CLKGATE_CON(59), 4, GFLAGS), 1905 COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, 1906 RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, 1907 RK3588_CLKGATE_CON(59), 5, GFLAGS), 1908 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, 1909 RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, 1910 RK3588_CLKGATE_CON(52), 0, GFLAGS), 1911 COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, 1912 RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, 1913 RK3588_CLKGATE_CON(52), 1, GFLAGS), 1914 COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, 1915 RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, 1916 RK3588_CLKGATE_CON(52), 2, GFLAGS), 1917 COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, 1918 RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, 1919 RK3588_CLKGATE_CON(52), 3, GFLAGS), 1920 COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, 1921 RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, 1922 RK3588_CLKGATE_CON(74), 0, GFLAGS), 1923 COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 1924 RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, 1925 RK3588_CLKGATE_CON(74), 2, GFLAGS), 1926 MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, 1927 RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), 1928 GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, 1929 RK3588_CLKGATE_CON(62), 0, GFLAGS), 1930 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, 1931 RK3588_CLKGATE_CON(62), 1, GFLAGS), 1932 COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, 1933 RK3588_CLKSEL_CON(140), 1, 2, MFLAGS, 1934 RK3588_CLKGATE_CON(62), 2, GFLAGS), 1935 GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0, 1936 RK3588_CLKGATE_CON(62), 3, GFLAGS), 1937 GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0, 1938 RK3588_CLKGATE_CON(62), 4, GFLAGS), 1939 COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0, 1940 RK3588_CLKSEL_CON(140), 3, 2, MFLAGS, 1941 RK3588_CLKGATE_CON(62), 5, GFLAGS), 1942 GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0, 1943 RK3588_CLKGATE_CON(60), 4, GFLAGS), 1944 GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, 1945 RK3588_CLKGATE_CON(60), 7, GFLAGS), 1946 GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0, 1947 RK3588_CLKGATE_CON(61), 9, GFLAGS), 1948 GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0, 1949 RK3588_CLKGATE_CON(61), 10, GFLAGS), 1950 GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0, 1951 RK3588_CLKGATE_CON(61), 11, GFLAGS), 1952 COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0, 1953 RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS, 1954 RK3588_CLKGATE_CON(61), 12, GFLAGS), 1955 COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", 1956 CLK_SET_RATE_PARENT, 1957 RK3588_CLKSEL_CON(139), 0, 1958 RK3588_CLKGATE_CON(61), 13, GFLAGS, 1959 &rk3588_hdmirx_aud_fracmux), 1960 GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0, 1961 RK3588_CLKGATE_CON(61), 14, GFLAGS), 1962 GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0, 1963 RK3588_CLKGATE_CON(60), 11, GFLAGS), 1964 COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, 1965 RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS, 1966 RK3588_CLKGATE_CON(60), 15, GFLAGS), 1967 GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0, 1968 RK3588_CLKGATE_CON(61), 0, GFLAGS), 1969 GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0, 1970 RK3588_CLKGATE_CON(61), 2, GFLAGS), 1971 COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0, 1972 RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS, 1973 RK3588_CLKGATE_CON(61), 6, GFLAGS), 1974 GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0, 1975 RK3588_CLKGATE_CON(61), 7, GFLAGS), 1976 GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0, 1977 RK3588_CLKGATE_CON(60), 9, GFLAGS), 1978 GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, 1979 RK3588_CLKGATE_CON(60), 10, GFLAGS), 1980 GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, 1981 RK3588_CLKGATE_CON(59), 14, GFLAGS), 1982 GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, 1983 RK3588_CLKGATE_CON(59), 15, GFLAGS), 1984 GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0, 1985 RK3588_CLKGATE_CON(65), 8, GFLAGS), 1986 COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0, 1987 RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, 1988 RK3588_CLKGATE_CON(65), 5, GFLAGS), 1989 COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", 1990 CLK_SET_RATE_PARENT, 1991 RK3588_CLKSEL_CON(156), 0, 1992 RK3588_CLKGATE_CON(65), 6, GFLAGS, 1993 &rk3588_i2s10_8ch_rx_fracmux), 1994 GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, 1995 RK3588_CLKGATE_CON(65), 7, GFLAGS), 1996 COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0, 1997 RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, 1998 RK3588_CLKGATE_CON(60), 1, GFLAGS), 1999 COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", 2000 CLK_SET_RATE_PARENT, 2001 RK3588_CLKSEL_CON(130), 0, 2002 RK3588_CLKGATE_CON(60), 2, GFLAGS, 2003 &rk3588_i2s7_8ch_rx_fracmux), 2004 GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, 2005 RK3588_CLKGATE_CON(60), 3, GFLAGS), 2006 COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0, 2007 RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, 2008 RK3588_CLKGATE_CON(65), 1, GFLAGS), 2009 COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", 2010 CLK_SET_RATE_PARENT, 2011 RK3588_CLKSEL_CON(154), 0, 2012 RK3588_CLKGATE_CON(65), 2, GFLAGS, 2013 &rk3588_i2s9_8ch_rx_fracmux), 2014 GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, 2015 RK3588_CLKGATE_CON(65), 3, GFLAGS), 2016 COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, 2017 RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, 2018 RK3588_CLKGATE_CON(62), 6, GFLAGS), 2019 COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0, 2020 RK3588_CLKSEL_CON(141), 0, 2021 RK3588_CLKGATE_CON(62), 7, GFLAGS, 2022 &rk3588_i2s5_8ch_tx_fracmux), 2023 GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, 2024 RK3588_CLKGATE_CON(62), 8, GFLAGS), 2025 COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, 2026 RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, 2027 RK3588_CLKGATE_CON(62), 13, GFLAGS), 2028 COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", 2029 CLK_SET_RATE_PARENT, 2030 RK3588_CLKSEL_CON(145), 0, 2031 RK3588_CLKGATE_CON(62), 14, GFLAGS, 2032 &rk3588_i2s6_8ch_tx_fracmux), 2033 GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0, 2034 RK3588_CLKGATE_CON(62), 15, GFLAGS), 2035 COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0, 2036 RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, 2037 RK3588_CLKGATE_CON(63), 0, GFLAGS), 2038 COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0, 2039 RK3588_CLKSEL_CON(147), 0, 2040 RK3588_CLKGATE_CON(63), 1, GFLAGS, 2041 &rk3588_i2s6_8ch_rx_fracmux), 2042 GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0, 2043 RK3588_CLKGATE_CON(63), 2, GFLAGS), 2044 MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT, 2045 RK3588_CLKSEL_CON(148), 2, 2, MFLAGS), 2046 COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0, 2047 RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, 2048 RK3588_CLKGATE_CON(63), 5, GFLAGS), 2049 COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", 2050 CLK_SET_RATE_PARENT, 2051 RK3588_CLKSEL_CON(149), 0, 2052 RK3588_CLKGATE_CON(63), 6, GFLAGS, 2053 &rk3588_spdif3_fracmux), 2054 GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, 2055 RK3588_CLKGATE_CON(63), 7, GFLAGS), 2056 COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0, 2057 RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, 2058 RK3588_CLKGATE_CON(63), 9, GFLAGS), 2059 COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", 2060 CLK_SET_RATE_PARENT, 2061 RK3588_CLKSEL_CON(151), 0, 2062 RK3588_CLKGATE_CON(63), 10, GFLAGS, 2063 &rk3588_spdif4_fracmux), 2064 GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, 2065 RK3588_CLKGATE_CON(63), 11, GFLAGS), 2066 COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0, 2067 RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS, 2068 RK3588_CLKGATE_CON(63), 13, GFLAGS), 2069 COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0, 2070 RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS, 2071 RK3588_CLKGATE_CON(63), 15, GFLAGS), 2072 COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0, 2073 RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS, 2074 RK3588_CLKGATE_CON(64), 1, GFLAGS), 2075 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, 2076 RK3588_CLKGATE_CON(73), 12, GFLAGS), 2077 GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0, 2078 RK3588_CLKGATE_CON(73), 13, GFLAGS), 2079 GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0, 2080 RK3588_CLKGATE_CON(72), 5, GFLAGS), 2081 GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0, 2082 RK3588_CLKGATE_CON(72), 6, GFLAGS), 2083 GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0, 2084 RK3588_CLKGATE_CON(72), 2, GFLAGS), 2085 GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0, 2086 RK3588_CLKGATE_CON(72), 4, GFLAGS), 2087 GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, 2088 RK3588_CLKGATE_CON(52), 8, GFLAGS), 2089 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0, 2090 RK3588_CLKGATE_CON(52), 9, GFLAGS), 2091 COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0, 2092 RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS, 2093 RK3588_CLKGATE_CON(52), 10, GFLAGS), 2094 COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, 2095 RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, 2096 RK3588_CLKGATE_CON(52), 11, GFLAGS), 2097 COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2098 RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, 2099 RK3588_CLKGATE_CON(52), 12, GFLAGS), 2100 COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 2101 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2102 RK3588_CLKSEL_CON(112), 7, 2, MFLAGS, 2103 RK3588_CLKGATE_CON(52), 13, GFLAGS), 2104 COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 2105 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2106 RK3588_CLKSEL_CON(112), 9, 2, MFLAGS, 2107 RK3588_CLKGATE_CON(53), 0, GFLAGS), 2108 COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, 2109 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2110 RK3588_CLKSEL_CON(112), 11, 2, MFLAGS, 2111 RK3588_CLKGATE_CON(53), 1, GFLAGS), 2112 COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0, 2113 RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS, 2114 RK3588_CLKGATE_CON(53), 2, GFLAGS), 2115 GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0, 2116 RK3588_CLKGATE_CON(53), 4, GFLAGS), 2117 GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0, 2118 RK3588_CLKGATE_CON(53), 5, GFLAGS), 2119 COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0, 2120 RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS, 2121 RK3588_CLKGATE_CON(53), 6, GFLAGS), 2122 COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0, 2123 RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS, 2124 RK3588_CLKGATE_CON(53), 7, GFLAGS), 2125 GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED, 2126 RK3588_CLKGATE_CON(53), 8, GFLAGS), 2127 GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0, 2128 RK3588_CLKGATE_CON(53), 10, GFLAGS), 2129 GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED, 2130 RK3588_CLKGATE_CON(2), 8, GFLAGS), 2131 GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED, 2132 RK3588_CLKGATE_CON(2), 15, GFLAGS), 2133 2134 GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0, 2135 RK3588_CLKGATE_CON(77), 0, GFLAGS), 2136 GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0, 2137 RK3588_CLKGATE_CON(77), 1, GFLAGS), 2138 GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0, 2139 RK3588_CLKGATE_CON(77), 2, GFLAGS), 2140 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0, 2141 RK3588_CLKSEL_CON(176), 0, 6, DFLAGS, 2142 RK3588_CLKGATE_CON(77), 3, GFLAGS), 2143 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0, 2144 RK3588_CLKSEL_CON(176), 6, 6, DFLAGS, 2145 RK3588_CLKGATE_CON(77), 4, GFLAGS), 2146 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0, 2147 RK3588_CLKSEL_CON(177), 0, 6, DFLAGS, 2148 RK3588_CLKGATE_CON(77), 5, GFLAGS), 2149 MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT, 2150 RK3588_CLKSEL_CON(177), 6, 1, MFLAGS), 2151 MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT, 2152 RK3588_CLKSEL_CON(177), 7, 1, MFLAGS), 2153 MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT, 2154 RK3588_CLKSEL_CON(177), 8, 1, MFLAGS), 2155 2156 /* pmu */ 2157 COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, 2158 RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, 2159 RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), 2160 COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, 2161 RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, 2162 RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), 2163 COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, 2164 RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, 2165 RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), 2166 COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, 2167 RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, 2168 RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), 2169 COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, 2170 RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, 2171 RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), 2172 COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, 2173 RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, 2174 RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), 2175 COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, 2176 RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, 2177 RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), 2178 GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, 2179 RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), 2180 COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, 2181 RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, 2182 RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), 2183 GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL, 2184 RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS), 2185 GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, 2186 RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS), 2187 GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL, 2188 RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS), 2189 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, 2190 RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS), 2191 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, 2192 RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS, 2193 RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS), 2194 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0, 2195 RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS), 2196 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0, 2197 RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS, 2198 RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS), 2199 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0, 2200 RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS), 2201 COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0, 2202 RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS, 2203 RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS), 2204 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", 2205 CLK_SET_RATE_PARENT, 2206 RK3588_PMU_CLKSEL_CON(6), 0, 2207 RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS, 2208 &rk3588_i2s1_8ch_tx_fracmux), 2209 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, 2210 RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS), 2211 COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0, 2212 RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS, 2213 RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS), 2214 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", 2215 CLK_SET_RATE_PARENT, 2216 RK3588_PMU_CLKSEL_CON(8), 0, 2217 RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS, 2218 &rk3588_i2s1_8ch_rx_fracmux), 2219 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, 2220 RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), 2221 MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT, 2222 RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), 2223 GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, 2224 RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), 2225 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED, 2226 RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS), 2227 GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL, 2228 RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS), 2229 GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, 2230 RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS), 2231 COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0, 2232 RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS, 2233 RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS), 2234 GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, 2235 RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS), 2236 GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL, 2237 RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS), 2238 COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, 2239 RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, 2240 RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS), 2241 GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED, 2242 RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS), 2243 GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0, 2244 RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS), 2245 COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0, 2246 RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS, 2247 RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS), 2248 GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0, 2249 RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS), 2250 GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0, 2251 RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS), 2252 COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0, 2253 RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS, 2254 RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS), 2255 GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0, 2256 RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS), 2257 GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0, 2258 RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS), 2259 COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0, 2260 RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS, 2261 RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS), 2262 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, 2263 RK3588_PMU_CLKSEL_CON(4), 0, 2264 RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS, 2265 &rk3588_uart0_fracmux), 2266 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, 2267 RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS), 2268 GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0, 2269 RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS), 2270 GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0, 2271 RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS), 2272 COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, 2273 RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, 2274 RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS), 2275 COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0, 2276 RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS, 2277 RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS), 2278 COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, 2279 CLK_IS_CRITICAL, 2280 RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS, 2281 RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS), 2282 COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, 2283 CLK_IS_CRITICAL, 2284 RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS, 2285 RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS), 2286 2287 GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0, 2288 RK3588_PHYREF_ALT_GATE, 0, GFLAGS), 2289 GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0, 2290 RK3588_PHYREF_ALT_GATE, 1, GFLAGS), 2291 GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0, 2292 RK3588_PHYREF_ALT_GATE, 2, GFLAGS), 2293 GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0, 2294 RK3588_PHYREF_ALT_GATE, 3, GFLAGS), 2295 2296 GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, 2297 RK3588_CLKGATE_CON(63), 12, GFLAGS), 2298 GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, 2299 RK3588_CLKGATE_CON(63), 14, GFLAGS), 2300 GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, 2301 RK3588_CLKGATE_CON(64), 0, GFLAGS), 2302 GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, 2303 RK3588_CLKGATE_CON(63), 8, GFLAGS), 2304 GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, 2305 RK3588_CLKGATE_CON(63), 4, GFLAGS), 2306 GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, 2307 RK3588_CLKGATE_CON(63), 3, GFLAGS), 2308 GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, 2309 RK3588_CLKGATE_CON(62), 12, GFLAGS), 2310 GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, 2311 RK3588_CLKGATE_CON(65), 0, GFLAGS), 2312 GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, 2313 RK3588_CLKGATE_CON(60), 0, GFLAGS), 2314 GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, 2315 RK3588_CLKGATE_CON(65), 4, GFLAGS), 2316 GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, 2317 RK3588_CLKGATE_CON(60), 5, GFLAGS), 2318 GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, 2319 RK3588_CLKGATE_CON(60), 6, GFLAGS), 2320 GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, 2321 RK3588_CLKGATE_CON(57), 7, GFLAGS), 2322 GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, 2323 RK3588_CLKGATE_CON(57), 2, GFLAGS), 2324 GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, 2325 RK3588_CLKGATE_CON(56), 14, GFLAGS), 2326 GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, 2327 RK3588_CLKGATE_CON(56), 10, GFLAGS), 2328 GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, 2329 RK3588_CLKGATE_CON(55), 12, GFLAGS), 2330 GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, 2331 RK3588_CLKGATE_CON(55), 13, GFLAGS), 2332 GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, 2333 RK3588_CLKGATE_CON(48), 4, GFLAGS), 2334 GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, 2335 RK3588_CLKGATE_CON(48), 5, GFLAGS), 2336 GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, 2337 RK3588_CLKGATE_CON(44), 8, GFLAGS), 2338 GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, 2339 RK3588_CLKGATE_CON(45), 5, GFLAGS), 2340 GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, 2341 RK3588_CLKGATE_CON(44), 10, GFLAGS), 2342 GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, 2343 RK3588_CLKGATE_CON(44), 12, GFLAGS), 2344 GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, 2345 RK3588_CLKGATE_CON(44), 14, GFLAGS), 2346 GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, 2347 RK3588_CLKGATE_CON(45), 0, GFLAGS), 2348 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, 2349 RK3588_CLKGATE_CON(45), 2, GFLAGS), 2350 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, 2351 RK3588_CLKGATE_CON(42), 7, GFLAGS), 2352 GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, 2353 RK3588_CLKGATE_CON(42), 10, GFLAGS), 2354 GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, 2355 RK3588_CLKGATE_CON(42), 11, GFLAGS), 2356 GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, 2357 RK3588_CLKGATE_CON(42), 12, GFLAGS), 2358 GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, 2359 RK3588_CLKGATE_CON(42), 13, GFLAGS), 2360 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, 2361 RK3588_CLKGATE_CON(42), 4, GFLAGS), 2362 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), 2363 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), 2364 GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, 2365 RK3588_CLKGATE_CON(75), 2, GFLAGS), 2366 GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, 2367 RK3588_CLKGATE_CON(41), 2, GFLAGS), 2368 GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, 2369 RK3588_CLKGATE_CON(41), 3, GFLAGS), 2370 GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, 2371 RK3588_CLKGATE_CON(40), 3, GFLAGS), 2372 GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, 2373 RK3588_CLKGATE_CON(40), 4, GFLAGS), 2374 GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, 2375 RK3588_CLKGATE_CON(39), 0, GFLAGS), 2376 GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, 2377 RK3588_CLKGATE_CON(39), 1, GFLAGS), 2378 GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, 2379 RK3588_CLKGATE_CON(38), 3, GFLAGS), 2380 GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, 2381 RK3588_CLKGATE_CON(38), 4, GFLAGS), 2382 GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, 2383 RK3588_CLKGATE_CON(38), 5, GFLAGS), 2384 GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, 2385 RK3588_CLKGATE_CON(38), 6, GFLAGS), 2386 GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, 2387 RK3588_CLKGATE_CON(38), 7, GFLAGS), 2388 GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, 2389 RK3588_CLKGATE_CON(38), 8, GFLAGS), 2390 GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, 2391 RK3588_CLKGATE_CON(38), 9, GFLAGS), 2392 GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, 2393 RK3588_CLKGATE_CON(38), 13, GFLAGS), 2394 GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, 2395 RK3588_CLKGATE_CON(38), 14, GFLAGS), 2396 GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, 2397 RK3588_CLKGATE_CON(38), 15, GFLAGS), 2398 GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, 2399 RK3588_CLKGATE_CON(31), 10, GFLAGS), 2400 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, 2401 RK3588_CLKGATE_CON(31), 11, GFLAGS), 2402 GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, 2403 RK3588_CLKGATE_CON(31), 4, GFLAGS), 2404 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, 2405 RK3588_CLKGATE_CON(26), 5, GFLAGS), 2406 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, 2407 RK3588_CLKGATE_CON(26), 7, GFLAGS), 2408 GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, 2409 RK3588_CLKGATE_CON(68), 5, GFLAGS), 2410 GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, 2411 RK3588_CLKGATE_CON(68), 2, GFLAGS), 2412}; 2413 2414static struct rockchip_clk_branch rk3588_clk_branches[] = { 2415 GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), 2416 GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), 2417 GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), 2418 GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), 2419 GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), 2420 GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), 2421 GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), 2422 GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), 2423 GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), 2424 GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), 2425 GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), 2426 GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), 2427 GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), 2428 GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), 2429 GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), 2430 GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), 2431 GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), 2432 GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), 2433 GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), 2434 GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), 2435 GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), 2436 GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), 2437}; 2438 2439static void __init rk3588_clk_early_init(struct device_node *np) 2440{ 2441 struct rockchip_clk_provider *ctx; 2442 unsigned long clk_nr_clks, max_clk_id1, max_clk_id2; 2443 void __iomem *reg_base; 2444 2445 max_clk_id1 = rockchip_clk_find_max_clk_id(rk3588_clk_branches, 2446 ARRAY_SIZE(rk3588_clk_branches)); 2447 max_clk_id2 = rockchip_clk_find_max_clk_id(rk3588_early_clk_branches, 2448 ARRAY_SIZE(rk3588_early_clk_branches)); 2449 clk_nr_clks = max(max_clk_id1, max_clk_id2) + 1; 2450 2451 reg_base = of_iomap(np, 0); 2452 if (!reg_base) { 2453 pr_err("%s: could not map cru region\n", __func__); 2454 return; 2455 } 2456 2457 ctx = rockchip_clk_init_early(np, reg_base, clk_nr_clks); 2458 if (IS_ERR(ctx)) { 2459 pr_err("%s: rockchip clk init failed\n", __func__); 2460 iounmap(reg_base); 2461 return; 2462 } 2463 early_ctx = ctx; 2464 2465 rockchip_clk_register_plls(ctx, rk3588_pll_clks, 2466 ARRAY_SIZE(rk3588_pll_clks), 2467 RK3588_GRF_SOC_STATUS0); 2468 2469 rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", 2470 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), 2471 &rk3588_cpulclk_data, rk3588_cpulclk_rates, 2472 ARRAY_SIZE(rk3588_cpulclk_rates)); 2473 rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01", 2474 mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p), 2475 &rk3588_cpub0clk_data, rk3588_cpub0clk_rates, 2476 ARRAY_SIZE(rk3588_cpub0clk_rates)); 2477 rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23", 2478 mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p), 2479 &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, 2480 ARRAY_SIZE(rk3588_cpub1clk_rates)); 2481 2482 rockchip_clk_register_branches(ctx, rk3588_early_clk_branches, 2483 ARRAY_SIZE(rk3588_early_clk_branches)); 2484 2485 rockchip_clk_of_add_provider(np, ctx); 2486} 2487CLK_OF_DECLARE_DRIVER(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_early_init); 2488 2489static int clk_rk3588_probe(struct platform_device *pdev) 2490{ 2491 struct rockchip_clk_provider *ctx = early_ctx; 2492 struct device *dev = &pdev->dev; 2493 struct device_node *np = dev->of_node; 2494 2495 rockchip_clk_register_late_branches(dev, ctx, rk3588_clk_branches, 2496 ARRAY_SIZE(rk3588_clk_branches)); 2497 2498 rockchip_clk_finalize(ctx); 2499 2500 rk3588_rst_init(np, ctx->reg_base); 2501 rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); 2502 2503 /* 2504 * Re-add clock provider, so that the newly added clocks are also 2505 * re-parented and get their defaults configured. 2506 */ 2507 of_clk_del_provider(np); 2508 rockchip_clk_of_add_provider(np, ctx); 2509 2510 return 0; 2511} 2512 2513static const struct of_device_id clk_rk3588_match_table[] = { 2514 { 2515 .compatible = "rockchip,rk3588-cru", 2516 }, 2517 { } 2518}; 2519 2520static struct platform_driver clk_rk3588_driver = { 2521 .probe = clk_rk3588_probe, 2522 .driver = { 2523 .name = "clk-rk3588", 2524 .of_match_table = clk_rk3588_match_table, 2525 .suppress_bind_attrs = true, 2526 }, 2527}; 2528 2529static int __init rockchip_clk_rk3588_drv_register(void) 2530{ 2531 return platform_driver_register(&clk_rk3588_driver); 2532} 2533core_initcall(rockchip_clk_rk3588_drv_register);
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