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clk-rk3562.c
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linux-6.19.14/drivers/clk/rockchip/clk-rk3562.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 * Author: Finley Xiao <finley.xiao@rock-chips.com> 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/module.h> 10#include <linux/of.h> 11#include <linux/of_device.h> 12#include <linux/of_address.h> 13#include <linux/platform_device.h> 14#include <linux/syscore_ops.h> 15#include <dt-bindings/clock/rockchip,rk3562-cru.h> 16#include "clk.h" 17 18#define RK3562_GRF_SOC_STATUS0 0x430 19#define ROCKCHIP_PLL_ALLOW_POWER_DOWN BIT(2) 20 21enum rk3562_plls { 22 apll, gpll, vpll, hpll, cpll, dpll, 23}; 24 25static struct rockchip_pll_rate_table rk3562_pll_rates[] = { 26 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 27 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 28 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 29 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 30 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 31 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 32 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 33 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), 42 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), 43 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), 44 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), 45 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), 46 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), 47 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), 48 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), 49 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), 50 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), 51 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), 52 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), 53 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), 54 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), 55 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), 56 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), 57 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), 58 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), 59 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), 60 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), 61 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 62 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), 63 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 64 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 65 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), 66 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), 67 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), 68 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), 69 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), 70 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), 71 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 72 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), 73 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 74 RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), 75 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), 76 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), 77 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), 78 RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), 79 { /* sentinel */ }, 80}; 81 82PNAME(mux_pll_p) = { "xin24m" }; 83PNAME(gpll_cpll_p) = { "gpll", "cpll" }; 84PNAME(gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" }; 85PNAME(gpll_cpll_pvtpll_dmyapll_p) = { "gpll", "cpll", "log_pvtpll", "dummy_apll" }; 86PNAME(gpll_cpll_hpll_xin24m_p) = { "gpll", "cpll", "hpll", "xin24m" }; 87PNAME(gpll_cpll_vpll_dmyhpll_p) = { "gpll", "cpll", "vpll", "dummy_hpll" }; 88PNAME(gpll_dmyhpll_vpll_apll_p) = { "gpll", "dummy_hpll", "vpll", "apll" }; 89PNAME(gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; 90PNAME(gpll_cpll_xin24m_dmyapll_p) = { "gpll", "cpll", "xin24m", "dummy_apll" }; 91PNAME(gpll_cpll_xin24m_dmyhpll_p) = { "gpll", "cpll", "xin24m", "dummy_hpll" }; 92PNAME(vpll_dmyhpll_gpll_cpll_p) = { "vpll", "dummy_hpll", "gpll", "cpll" }; 93PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; 94PNAME(mux_50m_xin24m_p) = { "clk_matrix_50m_src", "xin24m" }; 95PNAME(mux_100m_50m_xin24m_p) = { "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; 96PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" }; 97PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" }; 98PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" }; 99PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; 100PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" }; 101PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" }; 102PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_from_io" }; 103PNAME(mclk_sai1_out2io_p) = { "mclk_sai1", "xin_osc0_half" }; 104PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_from_io" }; 105PNAME(mclk_sai2_out2io_p) = { "mclk_sai2", "xin_osc0_half" }; 106PNAME(clk_spdif_p) = { "clk_spdif_src", "clk_spdif_frac", "xin_osc0_half" }; 107PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 108PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 109PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 110PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 111PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 112PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 113PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 114PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 115PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 116PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_32k_pvtm" }; 117PNAME(clk_pmu1_uart0_p) = { "clk_pmu1_uart0_src", "clk_pmu1_uart0_frac", "xin24m" }; 118PNAME(clk_pipephy_ref_p) = { "clk_pipephy_div", "clk_pipephy_xin24m" }; 119PNAME(clk_usbphy_ref_p) = { "clk_usb2phy_xin24m", "clk_24m_sscsrc" }; 120PNAME(clk_mipidsi_ref_p) = { "clk_mipidsiphy_xin24m", "clk_24m_sscsrc" }; 121 122static struct rockchip_pll_clock rk3562_pll_clks[] __initdata = { 123 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 124 0, RK3562_PLL_CON(0), 125 RK3562_MODE_CON, 0, 0, 126 ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), 127 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 128 0, RK3562_PLL_CON(24), 129 RK3562_MODE_CON, 2, 3, 0, rk3562_pll_rates), 130 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, 131 0, RK3562_PLL_CON(32), 132 RK3562_MODE_CON, 6, 4, 133 ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), 134 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, 135 0, RK3562_PLL_CON(40), 136 RK3562_MODE_CON, 8, 5, 137 ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), 138 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 139 0, RK3562_PMU1_PLL_CON(0), 140 RK3562_PMU1_MODE_CON, 0, 2, 0, rk3562_pll_rates), 141 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 142 CLK_IS_CRITICAL, RK3562_SUBDDR_PLL_CON(0), 143 RK3562_SUBDDR_MODE_CON, 0, 1, 0, NULL), 144}; 145 146#define MFLAGS CLK_MUX_HIWORD_MASK 147#define DFLAGS CLK_DIVIDER_HIWORD_MASK 148#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 149 150static struct rockchip_clk_branch rk3562_clk_sai0_fracmux __initdata = 151 MUX(CLK_SAI0, "clk_sai0", clk_sai0_p, CLK_SET_RATE_PARENT, 152 RK3562_PERI_CLKSEL_CON(3), 6, 2, MFLAGS); 153 154static struct rockchip_clk_branch rk3562_clk_sai1_fracmux __initdata = 155 MUX(CLK_SAI1, "clk_sai1", clk_sai1_p, CLK_SET_RATE_PARENT, 156 RK3562_PERI_CLKSEL_CON(5), 6, 2, MFLAGS); 157 158static struct rockchip_clk_branch rk3562_clk_sai2_fracmux __initdata = 159 MUX(CLK_SAI2, "clk_sai2", clk_sai2_p, CLK_SET_RATE_PARENT, 160 RK3562_PERI_CLKSEL_CON(8), 6, 2, MFLAGS); 161 162static struct rockchip_clk_branch rk3562_clk_spdif_fracmux __initdata = 163 MUX(CLK_SPDIF, "clk_spdif", clk_spdif_p, CLK_SET_RATE_PARENT, 164 RK3562_PERI_CLKSEL_CON(15), 6, 2, MFLAGS); 165 166static struct rockchip_clk_branch rk3562_clk_uart1_fracmux __initdata = 167 MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, 168 RK3562_PERI_CLKSEL_CON(21), 14, 2, MFLAGS); 169 170static struct rockchip_clk_branch rk3562_clk_uart2_fracmux __initdata = 171 MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, 172 RK3562_PERI_CLKSEL_CON(23), 14, 2, MFLAGS); 173 174static struct rockchip_clk_branch rk3562_clk_uart3_fracmux __initdata = 175 MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, 176 RK3562_PERI_CLKSEL_CON(25), 14, 2, MFLAGS); 177 178static struct rockchip_clk_branch rk3562_clk_uart4_fracmux __initdata = 179 MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, 180 RK3562_PERI_CLKSEL_CON(27), 14, 2, MFLAGS); 181 182static struct rockchip_clk_branch rk3562_clk_uart5_fracmux __initdata = 183 MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, 184 RK3562_PERI_CLKSEL_CON(29), 14, 2, MFLAGS); 185 186static struct rockchip_clk_branch rk3562_clk_uart6_fracmux __initdata = 187 MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, 188 RK3562_PERI_CLKSEL_CON(31), 14, 2, MFLAGS); 189 190static struct rockchip_clk_branch rk3562_clk_uart7_fracmux __initdata = 191 MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, 192 RK3562_PERI_CLKSEL_CON(33), 14, 2, MFLAGS); 193 194static struct rockchip_clk_branch rk3562_clk_uart8_fracmux __initdata = 195 MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, 196 RK3562_PERI_CLKSEL_CON(35), 14, 2, MFLAGS); 197 198static struct rockchip_clk_branch rk3562_clk_uart9_fracmux __initdata = 199 MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, 200 RK3562_PERI_CLKSEL_CON(37), 14, 2, MFLAGS); 201 202static struct rockchip_clk_branch rk3562_rtc32k_pmu_fracmux __initdata = 203 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 204 RK3562_PMU0_CLKSEL_CON(1), 0, 2, MFLAGS); 205 206static struct rockchip_clk_branch rk3562_clk_pmu1_uart0_fracmux __initdata = 207 MUX(CLK_PMU1_UART0, "clk_pmu1_uart0", clk_pmu1_uart0_p, CLK_SET_RATE_PARENT, 208 RK3562_PMU1_CLKSEL_CON(2), 6, 2, MFLAGS); 209 210static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = { 211 /* 212 * CRU Clock-Architecture 213 */ 214 /* PD_TOP */ 215 COMPOSITE(CLK_MATRIX_50M_SRC, "clk_matrix_50m_src", gpll_cpll_p, 0, 216 RK3562_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS, 217 RK3562_CLKGATE_CON(0), 0, GFLAGS), 218 COMPOSITE(CLK_MATRIX_100M_SRC, "clk_matrix_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, 219 RK3562_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 4, DFLAGS, 220 RK3562_CLKGATE_CON(0), 1, GFLAGS), 221 COMPOSITE(CLK_MATRIX_125M_SRC, "clk_matrix_125m_src", gpll_cpll_p, 0, 222 RK3562_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 4, DFLAGS, 223 RK3562_CLKGATE_CON(0), 2, GFLAGS), 224 COMPOSITE(CLK_MATRIX_200M_SRC, "clk_matrix_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, 225 RK3562_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 4, DFLAGS, 226 RK3562_CLKGATE_CON(0), 4, GFLAGS), 227 COMPOSITE(CLK_MATRIX_300M_SRC, "clk_matrix_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, 228 RK3562_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 4, DFLAGS, 229 RK3562_CLKGATE_CON(0), 6, GFLAGS), 230 COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_p, CLK_IS_CRITICAL, 231 RK3562_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 4, DFLAGS, 232 RK3562_CLKGATE_CON(1), 0, GFLAGS), 233 COMPOSITE(ACLK_TOP_VIO, "aclk_top_vio", gpll_cpll_p, 0, 234 RK3562_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 4, DFLAGS, 235 RK3562_CLKGATE_CON(1), 1, GFLAGS), 236 COMPOSITE(CLK_24M_SSCSRC, "clk_24m_sscsrc", vpll_dmyhpll_gpll_cpll_p, 0, 237 RK3562_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, 238 RK3562_CLKGATE_CON(1), 9, GFLAGS), 239 COMPOSITE(CLK_CAM0_OUT2IO, "clk_cam0_out2io", gpll_cpll_xin24m_dmyapll_p, 0, 240 RK3562_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 6, DFLAGS, 241 RK3562_CLKGATE_CON(1), 12, GFLAGS), 242 COMPOSITE(CLK_CAM1_OUT2IO, "clk_cam1_out2io", gpll_cpll_xin24m_dmyapll_p, 0, 243 RK3562_CLKSEL_CON(8), 14, 2, MFLAGS, 8, 6, DFLAGS, 244 RK3562_CLKGATE_CON(1), 13, GFLAGS), 245 COMPOSITE(CLK_CAM2_OUT2IO, "clk_cam2_out2io", gpll_cpll_xin24m_dmyapll_p, 0, 246 RK3562_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 6, DFLAGS, 247 RK3562_CLKGATE_CON(1), 14, GFLAGS), 248 COMPOSITE(CLK_CAM3_OUT2IO, "clk_cam3_out2io", gpll_cpll_xin24m_dmyapll_p, 0, 249 RK3562_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 6, DFLAGS, 250 RK3562_CLKGATE_CON(1), 15, GFLAGS), 251 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), 252 253 /* PD_BUS */ 254 COMPOSITE(ACLK_BUS, "aclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, 255 RK3562_CLKSEL_CON(40), 7, 1, MFLAGS, 0, 5, DFLAGS, 256 RK3562_CLKGATE_CON(18), 0, GFLAGS), 257 COMPOSITE(HCLK_BUS, "hclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, 258 RK3562_CLKSEL_CON(40), 15, 1, MFLAGS, 8, 6, DFLAGS, 259 RK3562_CLKGATE_CON(18), 1, GFLAGS), 260 COMPOSITE(PCLK_BUS, "pclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, 261 RK3562_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS, 262 RK3562_CLKGATE_CON(18), 2, GFLAGS), 263 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, 264 RK3562_CLKGATE_CON(19), 0, GFLAGS), 265 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, 266 RK3562_CLKGATE_CON(19), 1, GFLAGS), 267 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, 268 RK3562_CLKGATE_CON(19), 2, GFLAGS), 269 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, 270 RK3562_CLKGATE_CON(19), 3, GFLAGS), 271 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, 272 RK3562_CLKGATE_CON(19), 4, GFLAGS), 273 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", mux_200m_100m_50m_xin24m_p, 0, 274 RK3562_CLKSEL_CON(41), 8, 2, MFLAGS, 275 RK3562_CLKGATE_CON(19), 5, GFLAGS), 276 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, 277 RK3562_CLKGATE_CON(19), 6, GFLAGS), 278 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, 279 RK3562_CLKGATE_CON(19), 7, GFLAGS), 280 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, 281 RK3562_CLKGATE_CON(19), 8, GFLAGS), 282 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, 283 RK3562_CLKGATE_CON(19), 9, GFLAGS), 284 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, 285 RK3562_CLKGATE_CON(19), 10, GFLAGS), 286 COMPOSITE_NODIV(DCLK_BUS_GPIO, "dclk_bus_gpio", mux_xin24m_32k_p, 0, 287 RK3562_CLKSEL_CON(41), 15, 1, MFLAGS, 288 RK3562_CLKGATE_CON(20), 4, GFLAGS), 289 GATE(DCLK_BUS_GPIO3, "dclk_bus_gpio3", "dclk_bus_gpio", 0, 290 RK3562_CLKGATE_CON(20), 5, GFLAGS), 291 GATE(DCLK_BUS_GPIO4, "dclk_bus_gpio4", "dclk_bus_gpio", 0, 292 RK3562_CLKGATE_CON(20), 6, GFLAGS), 293 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, 294 RK3562_CLKGATE_CON(21), 0, GFLAGS), 295 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, 296 RK3562_CLKGATE_CON(21), 1, GFLAGS), 297 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, 298 RK3562_CLKGATE_CON(21), 2, GFLAGS), 299 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, 300 RK3562_CLKGATE_CON(21), 3, GFLAGS), 301 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, 302 RK3562_CLKGATE_CON(21), 4, GFLAGS), 303 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, 304 RK3562_CLKGATE_CON(21), 5, GFLAGS), 305 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, 306 RK3562_CLKGATE_CON(21), 6, GFLAGS), 307 GATE(PCLK_STIMER, "pclk_stimer", "pclk_bus", CLK_IGNORE_UNUSED, 308 RK3562_CLKGATE_CON(21), 7, GFLAGS), 309 GATE(CLK_STIMER0, "clk_stimer0", "xin24m", CLK_IGNORE_UNUSED, 310 RK3562_CLKGATE_CON(21), 8, GFLAGS), 311 GATE(CLK_STIMER1, "clk_stimer1", "xin24m", CLK_IGNORE_UNUSED, 312 RK3562_CLKGATE_CON(21), 9, GFLAGS), 313 GATE(PCLK_WDTNS, "pclk_wdtns", "pclk_bus", 0, 314 RK3562_CLKGATE_CON(22), 0, GFLAGS), 315 GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0, 316 RK3562_CLKGATE_CON(22), 1, GFLAGS), 317 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, 318 RK3562_CLKGATE_CON(22), 2, GFLAGS), 319 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, 320 RK3562_CLKGATE_CON(22), 3, GFLAGS), 321 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, 322 RK3562_CLKGATE_CON(22), 4, GFLAGS), 323 GATE(PCLK_INTC, "pclk_intc", "pclk_bus", 0, 324 RK3562_CLKGATE_CON(22), 5, GFLAGS), 325 GATE(ACLK_BUS_GIC400, "aclk_bus_gic400", "aclk_bus", CLK_IGNORE_UNUSED, 326 RK3562_CLKGATE_CON(22), 6, GFLAGS), 327 GATE(ACLK_BUS_SPINLOCK, "aclk_bus_spinlock", "aclk_bus", 0, 328 RK3562_CLKGATE_CON(23), 0, GFLAGS), 329 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus", CLK_IGNORE_UNUSED, 330 RK3562_CLKGATE_CON(23), 1, GFLAGS), 331 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", CLK_IGNORE_UNUSED, 332 RK3562_CLKGATE_CON(23), 2, GFLAGS), 333 GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus", 0, 334 RK3562_CLKGATE_CON(23), 3, GFLAGS), 335 GATE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", "clk_rtc_32k", 0, 336 RK3562_CLKGATE_CON(23), 4, GFLAGS), 337 GATE(HCLK_ICACHE, "hclk_icache", "hclk_bus", CLK_IGNORE_UNUSED, 338 RK3562_CLKGATE_CON(23), 8, GFLAGS), 339 GATE(HCLK_DCACHE, "hclk_dcache", "hclk_bus", CLK_IGNORE_UNUSED, 340 RK3562_CLKGATE_CON(23), 9, GFLAGS), 341 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, 342 RK3562_CLKGATE_CON(24), 0, GFLAGS), 343 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, 344 RK3562_CLKSEL_CON(43), 0, 11, DFLAGS, 345 RK3562_CLKGATE_CON(24), 1, GFLAGS), 346 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, 347 RK3562_CLKSEL_CON(43), 11, 5, DFLAGS, 348 RK3562_CLKGATE_CON(24), 3, GFLAGS), 349 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus", CLK_IGNORE_UNUSED, 350 RK3562_CLKGATE_CON(24), 4, GFLAGS), 351 COMPOSITE_NOMUX(CLK_SARADC_VCCIO156, "clk_saradc_vccio156", "xin24m", 0, 352 RK3562_CLKSEL_CON(44), 0, 12, DFLAGS, 353 RK3562_CLKGATE_CON(24), 9, GFLAGS), 354 GATE(PCLK_GMAC, "pclk_gmac", "pclk_bus", 0, 355 RK3562_CLKGATE_CON(25), 0, GFLAGS), 356 GATE(ACLK_GMAC, "aclk_gmac", "aclk_bus", 0, 357 RK3562_CLKGATE_CON(25), 1, GFLAGS), 358 COMPOSITE_NODIV(CLK_GMAC_125M_CRU_I, "clk_gmac_125m_cru_i", mux_125m_xin24m_p, 0, 359 RK3562_CLKSEL_CON(45), 8, 1, MFLAGS, 360 RK3562_CLKGATE_CON(25), 2, GFLAGS), 361 COMPOSITE_NODIV(CLK_GMAC_50M_CRU_I, "clk_gmac_50m_cru_i", mux_50m_xin24m_p, 0, 362 RK3562_CLKSEL_CON(45), 7, 1, MFLAGS, 363 RK3562_CLKGATE_CON(25), 3, GFLAGS), 364 COMPOSITE(CLK_GMAC_ETH_OUT2IO, "clk_gmac_eth_out2io", gpll_cpll_p, 0, 365 RK3562_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 7, DFLAGS, 366 RK3562_CLKGATE_CON(25), 4, GFLAGS), 367 GATE(PCLK_APB2ASB_VCCIO156, "pclk_apb2asb_vccio156", "pclk_bus", CLK_IS_CRITICAL, 368 RK3562_CLKGATE_CON(25), 5, GFLAGS), 369 GATE(PCLK_TO_VCCIO156, "pclk_to_vccio156", "pclk_bus", CLK_IS_CRITICAL, 370 RK3562_CLKGATE_CON(25), 6, GFLAGS), 371 GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_bus", 0, 372 RK3562_CLKGATE_CON(25), 8, GFLAGS), 373 GATE(PCLK_DSITX, "pclk_dsitx", "pclk_bus", 0, 374 RK3562_CLKGATE_CON(25), 9, GFLAGS), 375 GATE(PCLK_CPU_EMA_DET, "pclk_cpu_ema_det", "pclk_bus", CLK_IGNORE_UNUSED, 376 RK3562_CLKGATE_CON(25), 10, GFLAGS), 377 GATE(PCLK_HASH, "pclk_hash", "pclk_bus", 0, 378 RK3562_CLKGATE_CON(25), 11, GFLAGS), 379 GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_bus", CLK_IGNORE_UNUSED, 380 RK3562_CLKGATE_CON(25), 15, GFLAGS), 381 GATE(PCLK_ASB2APB_VCCIO156, "pclk_asb2apb_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL, 382 RK3562_CLKGATE_CON(26), 0, GFLAGS), 383 GATE(PCLK_IOC_VCCIO156, "pclk_ioc_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL, 384 RK3562_CLKGATE_CON(26), 1, GFLAGS), 385 GATE(PCLK_GPIO3_VCCIO156, "pclk_gpio3_vccio156", "pclk_to_vccio156", 0, 386 RK3562_CLKGATE_CON(26), 2, GFLAGS), 387 GATE(PCLK_GPIO4_VCCIO156, "pclk_gpio4_vccio156", "pclk_to_vccio156", 0, 388 RK3562_CLKGATE_CON(26), 3, GFLAGS), 389 GATE(PCLK_SARADC_VCCIO156, "pclk_saradc_vccio156", "pclk_to_vccio156", 0, 390 RK3562_CLKGATE_CON(26), 4, GFLAGS), 391 GATE(PCLK_MAC100, "pclk_mac100", "pclk_bus", 0, 392 RK3562_CLKGATE_CON(27), 0, GFLAGS), 393 GATE(ACLK_MAC100, "aclk_mac100", "aclk_bus", 0, 394 RK3562_CLKGATE_CON(27), 1, GFLAGS), 395 COMPOSITE_NODIV(CLK_MAC100_50M_MATRIX, "clk_mac100_50m_matrix", mux_50m_xin24m_p, 0, 396 RK3562_CLKSEL_CON(47), 7, 1, MFLAGS, 397 RK3562_CLKGATE_CON(27), 2, GFLAGS), 398 399 /* PD_CORE */ 400 COMPOSITE_NOMUX(0, "aclk_core_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED, 401 RK3562_CLKSEL_CON(11), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 402 RK3562_CLKGATE_CON(4), 3, GFLAGS), 403 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED, 404 RK3562_CLKSEL_CON(12), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 405 RK3562_CLKGATE_CON(4), 5, GFLAGS), 406 COMPOSITE_NOMUX(HCLK_CORE, "hclk_core", "gpll", CLK_IS_CRITICAL, 407 RK3562_CLKSEL_CON(13), 0, 6, DFLAGS, 408 RK3562_CLKGATE_CON(5), 2, GFLAGS), 409 GATE(0, "pclk_dbg_daplite", "pclk_dbg_pre", CLK_IGNORE_UNUSED, 410 RK3562_CLKGATE_CON(4), 10, GFLAGS), 411 412 /* PD_DDR */ 413 FACTOR_GATE(0, "clk_gpll_mux_to_ddr", "gpll", 0, 1, 4, 414 RK3328_CLKGATE_CON(1), 6, GFLAGS), 415 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL, 416 RK3562_DDR_CLKSEL_CON(1), 8, 5, DFLAGS, 417 RK3562_DDR_CLKGATE_CON(0), 3, GFLAGS), 418 COMPOSITE_NOMUX(CLK_MSCH_BRG_BIU, "clk_msch_brg_biu", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL, 419 RK3562_DDR_CLKSEL_CON(1), 0, 4, DFLAGS, 420 RK3562_DDR_CLKGATE_CON(0), 4, GFLAGS), 421 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr", CLK_IGNORE_UNUSED, 422 RK3562_DDR_CLKGATE_CON(0), 6, GFLAGS), 423 GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_ddr", CLK_IGNORE_UNUSED, 424 RK3562_DDR_CLKGATE_CON(0), 7, GFLAGS), 425 GATE(PCLK_DDR_PHY, "pclk_ddr_phy", "pclk_ddr", CLK_IGNORE_UNUSED, 426 RK3562_DDR_CLKGATE_CON(0), 8, GFLAGS), 427 GATE(PCLK_DDR_DFICTL, "pclk_ddr_dfictl", "pclk_ddr", CLK_IGNORE_UNUSED, 428 RK3562_DDR_CLKGATE_CON(0), 9, GFLAGS), 429 GATE(PCLK_DDR_DMA2DDR, "pclk_ddr_dma2ddr", "pclk_ddr", CLK_IGNORE_UNUSED, 430 RK3562_DDR_CLKGATE_CON(0), 10, GFLAGS), 431 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, 432 RK3562_DDR_CLKGATE_CON(1), 0, GFLAGS), 433 GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED, 434 RK3562_DDR_CLKGATE_CON(1), 1, GFLAGS), 435 GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, 436 RK3562_DDR_CLKGATE_CON(1), 2, GFLAGS), 437 GATE(PCLK_DDR_CRU, "pclk_ddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED, 438 RK3562_DDR_CLKGATE_CON(1), 3, GFLAGS), 439 GATE(PCLK_SUBDDR_CRU, "pclk_subddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED, 440 RK3562_DDR_CLKGATE_CON(1), 4, GFLAGS), 441 442 /* PD_GPU */ 443 COMPOSITE(CLK_GPU_PRE, "clk_gpu_pre", gpll_cpll_p, 0, 444 RK3562_CLKSEL_CON(18), 7, 1, MFLAGS, 0, 4, DFLAGS, 445 RK3562_CLKGATE_CON(8), 0, GFLAGS), 446 COMPOSITE_NOMUX(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre", 0, 447 RK3562_CLKSEL_CON(19), 0, 4, DFLAGS, 448 RK3562_CLKGATE_CON(8), 2, GFLAGS), 449 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre", 0, 450 RK3562_CLKGATE_CON(8), 4, GFLAGS), 451 COMPOSITE_NODIV(CLK_GPU_BRG, "clk_gpu_brg", mux_200m_100m_p, 0, 452 RK3562_CLKSEL_CON(19), 15, 1, MFLAGS, 453 RK3562_CLKGATE_CON(8), 8, GFLAGS), 454 455 /* PD_NPU */ 456 COMPOSITE(CLK_NPU_PRE, "clk_npu_pre", gpll_cpll_p, 0, 457 RK3562_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 4, DFLAGS, 458 RK3562_CLKGATE_CON(6), 0, GFLAGS), 459 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu_pre", 0, 460 RK3562_CLKSEL_CON(16), 0, 4, DFLAGS, 461 RK3562_CLKGATE_CON(6), 1, GFLAGS), 462 GATE(ACLK_RKNN, "aclk_rknn", "clk_npu_pre", 0, 463 RK3562_CLKGATE_CON(6), 4, GFLAGS), 464 GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_pre", 0, 465 RK3562_CLKGATE_CON(6), 5, GFLAGS), 466 467 /* PD_PERI */ 468 COMPOSITE(ACLK_PERI, "aclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, 469 RK3562_PERI_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS, 470 RK3562_PERI_CLKGATE_CON(1), 0, GFLAGS), 471 COMPOSITE(HCLK_PERI, "hclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, 472 RK3562_PERI_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 6, DFLAGS, 473 RK3562_PERI_CLKGATE_CON(1), 1, GFLAGS), 474 COMPOSITE(PCLK_PERI, "pclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, 475 RK3562_PERI_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 5, DFLAGS, 476 RK3562_PERI_CLKGATE_CON(1), 2, GFLAGS), 477 GATE(PCLK_PERICRU, "pclk_pericru", "pclk_peri", CLK_IGNORE_UNUSED, 478 RK3562_PERI_CLKGATE_CON(1), 6, GFLAGS), 479 GATE(HCLK_SAI0, "hclk_sai0", "hclk_peri", 0, 480 RK3562_PERI_CLKGATE_CON(2), 0, GFLAGS), 481 COMPOSITE(CLK_SAI0_SRC, "clk_sai0_src", gpll_cpll_hpll_p, 0, 482 RK3562_PERI_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS, 483 RK3562_PERI_CLKGATE_CON(2), 1, GFLAGS), 484 COMPOSITE_FRACMUX(CLK_SAI0_FRAC, "clk_sai0_frac", "clk_sai0_src", CLK_SET_RATE_PARENT, 485 RK3562_PERI_CLKSEL_CON(2), 0, 486 RK3562_PERI_CLKGATE_CON(2), 2, GFLAGS, 487 &rk3562_clk_sai0_fracmux), 488 GATE(MCLK_SAI0, "mclk_sai0", "clk_sai0", 0, 489 RK3562_PERI_CLKGATE_CON(2), 3, GFLAGS), 490 COMPOSITE_NODIV(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", mclk_sai0_out2io_p, CLK_SET_RATE_PARENT, 491 RK3562_PERI_CLKSEL_CON(3), 5, 1, MFLAGS, 492 RK3562_PERI_CLKGATE_CON(2), 4, GFLAGS), 493 GATE(HCLK_SAI1, "hclk_sai1", "hclk_peri", 0, 494 RK3562_PERI_CLKGATE_CON(2), 5, GFLAGS), 495 COMPOSITE(CLK_SAI1_SRC, "clk_sai1_src", gpll_cpll_hpll_p, 0, 496 RK3562_PERI_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 6, DFLAGS, 497 RK3562_PERI_CLKGATE_CON(2), 6, GFLAGS), 498 COMPOSITE_FRACMUX(CLK_SAI1_FRAC, "clk_sai1_frac", "clk_sai1_src", CLK_SET_RATE_PARENT, 499 RK3562_PERI_CLKSEL_CON(4), 0, 500 RK3562_PERI_CLKGATE_CON(2), 7, GFLAGS, 501 &rk3562_clk_sai1_fracmux), 502 GATE(MCLK_SAI1, "mclk_sai1", "clk_sai1", 0, 503 RK3562_PERI_CLKGATE_CON(2), 8, GFLAGS), 504 COMPOSITE_NODIV(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", mclk_sai1_out2io_p, CLK_SET_RATE_PARENT, 505 RK3562_PERI_CLKSEL_CON(5), 5, 1, MFLAGS, 506 RK3562_PERI_CLKGATE_CON(2), 9, GFLAGS), 507 GATE(HCLK_SAI2, "hclk_sai2", "hclk_peri", 0, 508 RK3562_PERI_CLKGATE_CON(2), 10, GFLAGS), 509 COMPOSITE(CLK_SAI2_SRC, "clk_sai2_src", gpll_cpll_hpll_p, 0, 510 RK3562_PERI_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, 511 RK3562_PERI_CLKGATE_CON(2), 11, GFLAGS), 512 COMPOSITE_FRACMUX(CLK_SAI2_FRAC, "clk_sai2_frac", "clk_sai2_src", CLK_SET_RATE_PARENT, 513 RK3562_PERI_CLKSEL_CON(7), 0, 514 RK3562_PERI_CLKGATE_CON(2), 12, GFLAGS, 515 &rk3562_clk_sai2_fracmux), 516 GATE(MCLK_SAI2, "mclk_sai2", "clk_sai2", 0, 517 RK3562_PERI_CLKGATE_CON(2), 13, GFLAGS), 518 COMPOSITE_NODIV(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", mclk_sai2_out2io_p, CLK_SET_RATE_PARENT, 519 RK3562_PERI_CLKSEL_CON(8), 5, 1, MFLAGS, 520 RK3562_PERI_CLKGATE_CON(2), 14, GFLAGS), 521 GATE(HCLK_DSM, "hclk_dsm", "hclk_peri", 0, 522 RK3562_PERI_CLKGATE_CON(3), 1, GFLAGS), 523 GATE(CLK_DSM, "clk_dsm", "mclk_sai1", 0, 524 RK3562_PERI_CLKGATE_CON(3), 2, GFLAGS), 525 GATE(HCLK_PDM, "hclk_pdm", "hclk_peri", 0, 526 RK3562_PERI_CLKGATE_CON(3), 4, GFLAGS), 527 COMPOSITE(MCLK_PDM, "mclk_pdm", gpll_cpll_hpll_xin24m_p, 0, 528 RK3562_PERI_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, 529 RK3562_PERI_CLKGATE_CON(3), 5, GFLAGS), 530 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, 531 RK3562_PERI_CLKGATE_CON(3), 8, GFLAGS), 532 COMPOSITE(CLK_SPDIF_SRC, "clk_spdif_src", gpll_cpll_hpll_p, 0, 533 RK3562_PERI_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 6, DFLAGS, 534 RK3562_PERI_CLKGATE_CON(3), 9, GFLAGS), 535 COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT, 536 RK3562_PERI_CLKSEL_CON(14), 0, 537 RK3562_PERI_CLKGATE_CON(3), 10, GFLAGS, 538 &rk3562_clk_spdif_fracmux), 539 GATE(MCLK_SPDIF, "mclk_spdif", "clk_spdif", 0, 540 RK3562_PERI_CLKGATE_CON(3), 11, GFLAGS), 541 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_peri", 0, 542 RK3562_PERI_CLKGATE_CON(4), 0, GFLAGS), 543 COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", gpll_cpll_xin24m_dmyhpll_p, 0, 544 RK3562_PERI_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS, 545 RK3562_PERI_CLKGATE_CON(4), 1, GFLAGS), 546 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "cclk_sdmmc0", RK3562_SDMMC0_CON0, 1), 547 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "cclk_sdmmc0", RK3562_SDMMC0_CON1, 1), 548 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_peri", 0, 549 RK3562_PERI_CLKGATE_CON(4), 2, GFLAGS), 550 COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", gpll_cpll_xin24m_dmyhpll_p, 0, 551 RK3562_PERI_CLKSEL_CON(17), 14, 2, MFLAGS, 0, 8, DFLAGS, 552 RK3562_PERI_CLKGATE_CON(4), 3, GFLAGS), 553 MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "cclk_sdmmc1", RK3562_SDMMC1_CON0, 1), 554 MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "cclk_sdmmc1", RK3562_SDMMC1_CON1, 1), 555 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, 556 RK3562_PERI_CLKGATE_CON(4), 8, GFLAGS), 557 GATE(ACLK_EMMC, "aclk_emmc", "aclk_peri", 0, 558 RK3562_PERI_CLKGATE_CON(4), 9, GFLAGS), 559 COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_xin24m_dmyhpll_p, 0, 560 RK3562_PERI_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS, 561 RK3562_PERI_CLKGATE_CON(4), 10, GFLAGS), 562 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, 563 RK3562_PERI_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS, 564 RK3562_PERI_CLKGATE_CON(4), 11, GFLAGS), 565 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, 566 RK3562_PERI_CLKGATE_CON(4), 12, GFLAGS), 567 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_xin24m_p, 0, 568 RK3562_PERI_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, 569 RK3562_PERI_CLKGATE_CON(4), 13, GFLAGS), 570 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, 571 RK3562_PERI_CLKGATE_CON(4), 14, GFLAGS), 572 GATE(HCLK_USB2HOST, "hclk_usb2host", "hclk_peri", 0, 573 RK3562_PERI_CLKGATE_CON(5), 0, GFLAGS), 574 GATE(HCLK_USB2HOST_ARB, "hclk_usb2host_arb", "hclk_peri", 0, 575 RK3562_PERI_CLKGATE_CON(5), 1, GFLAGS), 576 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, 577 RK3562_PERI_CLKGATE_CON(6), 0, GFLAGS), 578 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_xin24m_p, 0, 579 RK3562_PERI_CLKSEL_CON(20), 12, 2, MFLAGS, 580 RK3562_PERI_CLKGATE_CON(6), 1, GFLAGS), 581 GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0, 582 RK3562_PERI_CLKGATE_CON(6), 2, GFLAGS), 583 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, 584 RK3562_PERI_CLKGATE_CON(6), 3, GFLAGS), 585 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_xin24m_p, 0, 586 RK3562_PERI_CLKSEL_CON(20), 14, 2, MFLAGS, 587 RK3562_PERI_CLKGATE_CON(6), 4, GFLAGS), 588 GATE(SCLK_IN_SPI2, "sclk_in_spi2", "sclk_in_spi2_io", 0, 589 RK3562_PERI_CLKGATE_CON(6), 5, GFLAGS), 590 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, 591 RK3562_PERI_CLKGATE_CON(7), 0, GFLAGS), 592 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, 593 RK3562_PERI_CLKGATE_CON(7), 1, GFLAGS), 594 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, 595 RK3562_PERI_CLKGATE_CON(7), 2, GFLAGS), 596 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, 597 RK3562_PERI_CLKGATE_CON(7), 3, GFLAGS), 598 GATE(PCLK_UART5, "pclk_uart5", "pclk_peri", 0, 599 RK3562_PERI_CLKGATE_CON(7), 4, GFLAGS), 600 GATE(PCLK_UART6, "pclk_uart6", "pclk_peri", 0, 601 RK3562_PERI_CLKGATE_CON(7), 5, GFLAGS), 602 GATE(PCLK_UART7, "pclk_uart7", "pclk_peri", 0, 603 RK3562_PERI_CLKGATE_CON(7), 6, GFLAGS), 604 GATE(PCLK_UART8, "pclk_uart8", "pclk_peri", 0, 605 RK3562_PERI_CLKGATE_CON(7), 7, GFLAGS), 606 GATE(PCLK_UART9, "pclk_uart9", "pclk_peri", 0, 607 RK3562_PERI_CLKGATE_CON(7), 8, GFLAGS), 608 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, 609 RK3562_PERI_CLKSEL_CON(21), 8, 1, MFLAGS, 0, 7, DFLAGS, 610 RK3562_PERI_CLKGATE_CON(7), 9, GFLAGS), 611 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 612 RK3562_PERI_CLKSEL_CON(22), 0, 613 RK3562_PERI_CLKGATE_CON(7), 10, GFLAGS, 614 &rk3562_clk_uart1_fracmux), 615 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, 616 RK3562_PERI_CLKGATE_CON(7), 11, GFLAGS), 617 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, 618 RK3562_PERI_CLKSEL_CON(23), 8, 1, MFLAGS, 0, 7, DFLAGS, 619 RK3562_PERI_CLKGATE_CON(7), 12, GFLAGS), 620 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 621 RK3562_PERI_CLKSEL_CON(24), 0, 622 RK3562_PERI_CLKGATE_CON(7), 13, GFLAGS, 623 &rk3562_clk_uart2_fracmux), 624 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, 625 RK3562_PERI_CLKGATE_CON(7), 14, GFLAGS), 626 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, 627 RK3562_PERI_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS, 628 RK3562_PERI_CLKGATE_CON(7), 15, GFLAGS), 629 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 630 RK3562_PERI_CLKSEL_CON(26), 0, 631 RK3562_PERI_CLKGATE_CON(8), 0, GFLAGS, 632 &rk3562_clk_uart3_fracmux), 633 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, 634 RK3562_PERI_CLKGATE_CON(8), 1, GFLAGS), 635 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, 636 RK3562_PERI_CLKSEL_CON(27), 8, 1, MFLAGS, 0, 7, DFLAGS, 637 RK3562_PERI_CLKGATE_CON(8), 2, GFLAGS), 638 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 639 RK3562_PERI_CLKSEL_CON(28), 0, 640 RK3562_PERI_CLKGATE_CON(8), 3, GFLAGS, 641 &rk3562_clk_uart4_fracmux), 642 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, 643 RK3562_PERI_CLKGATE_CON(8), 4, GFLAGS), 644 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, 645 RK3562_PERI_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 7, DFLAGS, 646 RK3562_PERI_CLKGATE_CON(8), 5, GFLAGS), 647 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 648 RK3562_PERI_CLKSEL_CON(30), 0, 649 RK3562_PERI_CLKGATE_CON(8), 6, GFLAGS, 650 &rk3562_clk_uart5_fracmux), 651 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, 652 RK3562_PERI_CLKGATE_CON(8), 7, GFLAGS), 653 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, 654 RK3562_PERI_CLKSEL_CON(31), 8, 1, MFLAGS, 0, 7, DFLAGS, 655 RK3562_PERI_CLKGATE_CON(8), 8, GFLAGS), 656 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, 657 RK3562_PERI_CLKSEL_CON(32), 0, 658 RK3562_PERI_CLKGATE_CON(8), 9, GFLAGS, 659 &rk3562_clk_uart6_fracmux), 660 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, 661 RK3562_PERI_CLKGATE_CON(8), 10, GFLAGS), 662 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, 663 RK3562_PERI_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 7, DFLAGS, 664 RK3562_PERI_CLKGATE_CON(8), 11, GFLAGS), 665 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, 666 RK3562_PERI_CLKSEL_CON(34), 0, 667 RK3562_PERI_CLKGATE_CON(8), 12, GFLAGS, 668 &rk3562_clk_uart7_fracmux), 669 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, 670 RK3562_PERI_CLKGATE_CON(8), 13, GFLAGS), 671 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, 672 RK3562_PERI_CLKSEL_CON(35), 8, 1, MFLAGS, 0, 7, DFLAGS, 673 RK3562_PERI_CLKGATE_CON(8), 14, GFLAGS), 674 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, 675 RK3562_PERI_CLKSEL_CON(36), 0, 676 RK3562_PERI_CLKGATE_CON(8), 15, GFLAGS, 677 &rk3562_clk_uart8_fracmux), 678 GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, 679 RK3562_PERI_CLKGATE_CON(9), 0, GFLAGS), 680 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, 681 RK3562_PERI_CLKSEL_CON(37), 8, 1, MFLAGS, 0, 7, DFLAGS, 682 RK3562_PERI_CLKGATE_CON(9), 1, GFLAGS), 683 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, 684 RK3562_PERI_CLKSEL_CON(38), 0, 685 RK3562_PERI_CLKGATE_CON(9), 2, GFLAGS, 686 &rk3562_clk_uart9_fracmux), 687 GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, 688 RK3562_PERI_CLKGATE_CON(9), 3, GFLAGS), 689 GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri", 0, 690 RK3562_PERI_CLKGATE_CON(10), 0, GFLAGS), 691 COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_xin24m_p, 0, 692 RK3562_PERI_CLKSEL_CON(40), 0, 2, MFLAGS, 693 RK3562_PERI_CLKGATE_CON(10), 1, GFLAGS), 694 GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0, 695 RK3562_PERI_CLKGATE_CON(10), 2, GFLAGS), 696 GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri", 0, 697 RK3562_PERI_CLKGATE_CON(10), 3, GFLAGS), 698 COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_xin24m_p, 0, 699 RK3562_PERI_CLKSEL_CON(40), 6, 2, MFLAGS, 700 RK3562_PERI_CLKGATE_CON(10), 4, GFLAGS), 701 GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0, 702 RK3562_PERI_CLKGATE_CON(10), 5, GFLAGS), 703 GATE(PCLK_PWM3_PERI, "pclk_pwm3_peri", "pclk_peri", 0, 704 RK3562_PERI_CLKGATE_CON(10), 6, GFLAGS), 705 COMPOSITE_NODIV(CLK_PWM3_PERI, "clk_pwm3_peri", mux_100m_50m_xin24m_p, 0, 706 RK3562_PERI_CLKSEL_CON(40), 8, 2, MFLAGS, 707 RK3562_PERI_CLKGATE_CON(10), 7, GFLAGS), 708 GATE(CLK_CAPTURE_PWM3_PERI, "clk_capture_pwm3_peri", "xin24m", 0, 709 RK3562_PERI_CLKGATE_CON(10), 8, GFLAGS), 710 GATE(PCLK_CAN0, "pclk_can0", "pclk_peri", 0, 711 RK3562_PERI_CLKGATE_CON(11), 0, GFLAGS), 712 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, 713 RK3562_PERI_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS, 714 RK3562_PERI_CLKGATE_CON(11), 1, GFLAGS), 715 GATE(PCLK_CAN1, "pclk_can1", "pclk_peri", 0, 716 RK3562_PERI_CLKGATE_CON(11), 2, GFLAGS), 717 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, 718 RK3562_PERI_CLKSEL_CON(41), 15, 1, MFLAGS, 8, 5, DFLAGS, 719 RK3562_PERI_CLKGATE_CON(11), 3, GFLAGS), 720 GATE(PCLK_PERI_WDT, "pclk_peri_wdt", "pclk_peri", 0, 721 RK3562_PERI_CLKGATE_CON(13), 0, GFLAGS), 722 COMPOSITE_NODIV(TCLK_PERI_WDT, "tclk_peri_wdt", mux_xin24m_32k_p, 0, 723 RK3562_PERI_CLKSEL_CON(43), 15, 1, MFLAGS, 724 RK3562_PERI_CLKGATE_CON(13), 1, GFLAGS), 725 GATE(ACLK_SYSMEM, "aclk_sysmem", "aclk_peri", CLK_IGNORE_UNUSED, 726 RK3562_PERI_CLKGATE_CON(13), 2, GFLAGS), 727 GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri", CLK_IGNORE_UNUSED, 728 RK3562_PERI_CLKGATE_CON(13), 3, GFLAGS), 729 GATE(PCLK_PERI_GRF, "pclk_peri_grf", "pclk_peri", CLK_IGNORE_UNUSED, 730 RK3562_PERI_CLKGATE_CON(13), 4, GFLAGS), 731 GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, 732 RK3562_PERI_CLKGATE_CON(13), 5, GFLAGS), 733 GATE(ACLK_RKDMAC, "aclk_rkdmac", "aclk_peri", 0, 734 RK3562_PERI_CLKGATE_CON(13), 6, GFLAGS), 735 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri", 0, 736 RK3562_PERI_CLKGATE_CON(14), 0, GFLAGS), 737 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, 738 RK3562_PERI_CLKGATE_CON(14), 1, GFLAGS), 739 COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0, 740 RK3562_PERI_CLKSEL_CON(44), 0, 8, DFLAGS, 741 RK3562_PERI_CLKGATE_CON(14), 2, GFLAGS), 742 GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri", CLK_IGNORE_UNUSED, 743 RK3562_PERI_CLKGATE_CON(14), 3, GFLAGS), 744 GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", CLK_IGNORE_UNUSED, 745 RK3562_PERI_CLKGATE_CON(14), 4, GFLAGS), 746 COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", CLK_IGNORE_UNUSED, 747 RK3562_PERI_CLKSEL_CON(44), 8, 8, DFLAGS, 748 RK3562_PERI_CLKGATE_CON(14), 5, GFLAGS), 749 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, 750 RK3562_PERI_CLKGATE_CON(14), 6, GFLAGS), 751 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_peri", 0, 752 RK3562_PERI_CLKGATE_CON(14), 7, GFLAGS), 753 GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri", 0, 754 RK3562_PERI_CLKGATE_CON(15), 0, GFLAGS), 755 GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri", 0, 756 RK3562_PERI_CLKGATE_CON(15), 7, GFLAGS), 757 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, 758 RK3562_PERI_CLKGATE_CON(16), 4, GFLAGS), 759 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, 760 RK3562_PERI_CLKSEL_CON(46), 0, 12, DFLAGS, 761 RK3562_PERI_CLKGATE_CON(16), 5, GFLAGS), 762 GATE(PCLK_IOC_VCCIO234, "pclk_ioc_vccio234", "pclk_peri", CLK_IS_CRITICAL, 763 RK3562_PERI_CLKGATE_CON(16), 12, GFLAGS), 764 GATE(PCLK_PERI_GPIO1, "pclk_peri_gpio1", "pclk_peri", 0, 765 RK3562_PERI_CLKGATE_CON(17), 0, GFLAGS), 766 GATE(PCLK_PERI_GPIO2, "pclk_peri_gpio2", "pclk_peri", 0, 767 RK3562_PERI_CLKGATE_CON(17), 1, GFLAGS), 768 COMPOSITE_NODIV(DCLK_PERI_GPIO, "dclk_peri_gpio", mux_xin24m_32k_p, 0, 769 RK3562_PERI_CLKSEL_CON(47), 8, 1, MFLAGS, 770 RK3562_PERI_CLKGATE_CON(17), 4, GFLAGS), 771 GATE(DCLK_PERI_GPIO1, "dclk_peri_gpio1", "dclk_peri_gpio", 0, 772 RK3562_PERI_CLKGATE_CON(17), 2, GFLAGS), 773 GATE(DCLK_PERI_GPIO2, "dclk_peri_gpio2", "dclk_peri_gpio", 0, 774 RK3562_PERI_CLKGATE_CON(17), 3, GFLAGS), 775 776 /* PD_PHP */ 777 COMPOSITE(ACLK_PHP, "aclk_php", gpll_cpll_p, 0, 778 RK3562_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 4, DFLAGS, 779 RK3562_CLKGATE_CON(16), 0, GFLAGS), 780 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, 781 RK3562_CLKSEL_CON(36), 8, 4, DFLAGS, 782 RK3562_CLKGATE_CON(16), 1, GFLAGS), 783 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_php", 0, 784 RK3562_CLKGATE_CON(16), 4, GFLAGS), 785 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_php", 0, 786 RK3562_CLKGATE_CON(16), 5, GFLAGS), 787 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_php", 0, 788 RK3562_CLKGATE_CON(16), 6, GFLAGS), 789 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_php", 0, 790 RK3562_CLKGATE_CON(16), 7, GFLAGS), 791 GATE(CLK_PCIE20_AUX, "clk_pcie20_aux", "xin24m", 0, 792 RK3562_CLKGATE_CON(16), 8, GFLAGS), 793 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_php", 0, 794 RK3562_CLKGATE_CON(16), 10, GFLAGS), 795 COMPOSITE_NODIV(CLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0, 796 RK3562_CLKSEL_CON(36), 15, 1, MFLAGS, 797 RK3562_CLKGATE_CON(16), 11, GFLAGS), 798 GATE(CLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0, 799 RK3562_CLKGATE_CON(16), 12, GFLAGS), 800 GATE(CLK_PIPEPHY_REF_FUNC, "clk_pipephy_ref_func", "pclk_pcie20", 0, 801 RK3562_CLKGATE_CON(17), 3, GFLAGS), 802 803 /* PD_PMU1 */ 804 COMPOSITE_NOMUX(CLK_200M_PMU, "clk_200m_pmu", "cpll", CLK_IS_CRITICAL, 805 RK3562_PMU1_CLKSEL_CON(0), 0, 5, DFLAGS, 806 RK3562_PMU1_CLKGATE_CON(0), 1, GFLAGS), 807 /* PD_PMU0 */ 808 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IS_CRITICAL, 809 RK3562_PMU0_CLKSEL_CON(0), 0, 810 RK3562_PMU0_CLKGATE_CON(0), 15, GFLAGS, 811 &rk3562_rtc32k_pmu_fracmux), 812 COMPOSITE_NOMUX(BUSCLK_PDPMU0, "busclk_pdpmu0", "clk_200m_pmu", CLK_IS_CRITICAL, 813 RK3562_PMU0_CLKSEL_CON(1), 3, 2, DFLAGS, 814 RK3562_PMU0_CLKGATE_CON(0), 14, GFLAGS), 815 GATE(PCLK_PMU0_CRU, "pclk_pmu0_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED, 816 RK3562_PMU0_CLKGATE_CON(0), 0, GFLAGS), 817 GATE(PCLK_PMU0_PMU, "pclk_pmu0_pmu", "busclk_pdpmu0", CLK_IGNORE_UNUSED, 818 RK3562_PMU0_CLKGATE_CON(0), 1, GFLAGS), 819 GATE(CLK_PMU0_PMU, "clk_pmu0_pmu", "xin24m", CLK_IGNORE_UNUSED, 820 RK3562_PMU0_CLKGATE_CON(0), 2, GFLAGS), 821 GATE(PCLK_PMU0_HP_TIMER, "pclk_pmu0_hp_timer", "busclk_pdpmu0", CLK_IGNORE_UNUSED, 822 RK3562_PMU0_CLKGATE_CON(0), 3, GFLAGS), 823 GATE(CLK_PMU0_HP_TIMER, "clk_pmu0_hp_timer", "xin24m", CLK_IGNORE_UNUSED, 824 RK3562_PMU0_CLKGATE_CON(0), 4, GFLAGS), 825 GATE(CLK_PMU0_32K_HP_TIMER, "clk_pmu0_32k_hp_timer", "clk_rtc_32k", CLK_IGNORE_UNUSED, 826 RK3562_PMU0_CLKGATE_CON(0), 5, GFLAGS), 827 GATE(PCLK_PMU0_PVTM, "pclk_pmu0_pvtm", "busclk_pdpmu0", 0, 828 RK3562_PMU0_CLKGATE_CON(0), 6, GFLAGS), 829 GATE(CLK_PMU0_PVTM, "clk_pmu0_pvtm", "xin24m", 0, 830 RK3562_PMU0_CLKGATE_CON(0), 7, GFLAGS), 831 GATE(PCLK_IOC_PMUIO, "pclk_ioc_pmuio", "busclk_pdpmu0", CLK_IS_CRITICAL, 832 RK3562_PMU0_CLKGATE_CON(0), 8, GFLAGS), 833 GATE(PCLK_PMU0_GPIO0, "pclk_pmu0_gpio0", "busclk_pdpmu0", 0, 834 RK3562_PMU0_CLKGATE_CON(0), 9, GFLAGS), 835 GATE(DBCLK_PMU0_GPIO0, "dbclk_pmu0_gpio0", "xin24m", 0, 836 RK3562_PMU0_CLKGATE_CON(0), 10, GFLAGS), 837 GATE(PCLK_PMU0_GRF, "pclk_pmu0_grf", "busclk_pdpmu0", CLK_IGNORE_UNUSED, 838 RK3562_PMU0_CLKGATE_CON(0), 11, GFLAGS), 839 GATE(PCLK_PMU0_SGRF, "pclk_pmu0_sgrf", "busclk_pdpmu0", CLK_IGNORE_UNUSED, 840 RK3562_PMU0_CLKGATE_CON(0), 12, GFLAGS), 841 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED, 842 RK3562_PMU0_CLKGATE_CON(1), 0, GFLAGS), 843 GATE(PCLK_PMU0_SCRKEYGEN, "pclk_pmu0_scrkeygen", "busclk_pdpmu0", CLK_IGNORE_UNUSED, 844 RK3562_PMU0_CLKGATE_CON(1), 1, GFLAGS), 845 COMPOSITE_NOMUX(CLK_PIPEPHY_DIV, "clk_pipephy_div", "cpll", 0, 846 RK3562_PMU0_CLKSEL_CON(2), 0, 6, DFLAGS, 847 RK3562_PMU0_CLKGATE_CON(2), 0, GFLAGS), 848 GATE(CLK_PIPEPHY_XIN24M, "clk_pipephy_xin24m", "xin24m", 0, 849 RK3562_PMU0_CLKGATE_CON(2), 1, GFLAGS), 850 COMPOSITE_NODIV(CLK_PIPEPHY_REF, "clk_pipephy_ref", clk_pipephy_ref_p, 0, 851 RK3562_PMU0_CLKSEL_CON(2), 7, 1, MFLAGS, 852 RK3562_PMU0_CLKGATE_CON(2), 2, GFLAGS), 853 GATE(CLK_USB2PHY_XIN24M, "clk_usb2phy_xin24m", "xin24m", 0, 854 RK3562_PMU0_CLKGATE_CON(2), 4, GFLAGS), 855 COMPOSITE_NODIV(CLK_USB2PHY_REF, "clk_usb2phy_ref", clk_usbphy_ref_p, 0, 856 RK3562_PMU0_CLKSEL_CON(2), 8, 1, MFLAGS, 857 RK3562_PMU0_CLKGATE_CON(2), 5, GFLAGS), 858 GATE(CLK_MIPIDSIPHY_XIN24M, "clk_mipidsiphy_xin24m", "xin24m", 0, 859 RK3562_PMU0_CLKGATE_CON(2), 6, GFLAGS), 860 COMPOSITE_NODIV(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", clk_mipidsi_ref_p, 0, 861 RK3562_PMU0_CLKSEL_CON(2), 15, 1, MFLAGS, 862 RK3562_PMU0_CLKGATE_CON(2), 7, GFLAGS), 863 GATE(PCLK_PMU0_I2C0, "pclk_pmu0_i2c0", "busclk_pdpmu0", 0, 864 RK3562_PMU0_CLKGATE_CON(2), 8, GFLAGS), 865 COMPOSITE(CLK_PMU0_I2C0, "clk_pmu0_i2c0", mux_200m_xin24m_32k_p, 0, 866 RK3562_PMU0_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 5, DFLAGS, 867 RK3562_PMU0_CLKGATE_CON(2), 9, GFLAGS), 868 /* PD_PMU1 */ 869 GATE(PCLK_PMU1_CRU, "pclk_pmu1_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED, 870 RK3562_PMU1_CLKGATE_CON(0), 0, GFLAGS), 871 GATE(HCLK_PMU1_MEM, "hclk_pmu1_mem", "busclk_pdpmu0", CLK_IGNORE_UNUSED, 872 RK3562_PMU1_CLKGATE_CON(0), 2, GFLAGS), 873 GATE(PCLK_PMU1_UART0, "pclk_pmu1_uart0", "busclk_pdpmu0", 0, 874 RK3562_PMU1_CLKGATE_CON(0), 7, GFLAGS), 875 COMPOSITE_NOMUX(CLK_PMU1_UART0_SRC, "clk_pmu1_uart0_src", "cpll", 0, 876 RK3562_PMU1_CLKSEL_CON(2), 0, 4, DFLAGS, 877 RK3562_PMU1_CLKGATE_CON(0), 8, GFLAGS), 878 COMPOSITE_FRACMUX(CLK_PMU1_UART0_FRAC, "clk_pmu1_uart0_frac", "clk_pmu1_uart0_src", CLK_SET_RATE_PARENT, 879 RK3562_PMU1_CLKSEL_CON(3), 0, 880 RK3562_PMU1_CLKGATE_CON(0), 9, GFLAGS, 881 &rk3562_clk_pmu1_uart0_fracmux), 882 GATE(SCLK_PMU1_UART0, "sclk_pmu1_uart0", "clk_pmu1_uart0", 0, 883 RK3562_PMU1_CLKGATE_CON(0), 10, GFLAGS), 884 GATE(PCLK_PMU1_SPI0, "pclk_pmu1_spi0", "busclk_pdpmu0", 0, 885 RK3562_PMU1_CLKGATE_CON(1), 0, GFLAGS), 886 COMPOSITE(CLK_PMU1_SPI0, "clk_pmu1_spi0", mux_200m_xin24m_32k_p, 0, 887 RK3562_PMU1_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 2, DFLAGS, 888 RK3562_PMU1_CLKGATE_CON(1), 1, GFLAGS), 889 GATE(SCLK_IN_PMU1_SPI0, "sclk_in_pmu1_spi0", "sclk_in_pmu1_spi0_io", 0, 890 RK3562_PMU1_CLKGATE_CON(1), 2, GFLAGS), 891 GATE(PCLK_PMU1_PWM0, "pclk_pmu1_pwm0", "busclk_pdpmu0", 0, 892 RK3562_PMU1_CLKGATE_CON(1), 3, GFLAGS), 893 COMPOSITE(CLK_PMU1_PWM0, "clk_pmu1_pwm0", mux_200m_xin24m_32k_p, 0, 894 RK3562_PMU1_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 2, DFLAGS, 895 RK3562_PMU1_CLKGATE_CON(1), 4, GFLAGS), 896 GATE(CLK_CAPTURE_PMU1_PWM0, "clk_capture_pmu1_pwm0", "xin24m", 0, 897 RK3562_PMU1_CLKGATE_CON(1), 5, GFLAGS), 898 GATE(CLK_PMU1_WIFI, "clk_pmu1_wifi", "xin24m", 0, 899 RK3562_PMU1_CLKGATE_CON(1), 6, GFLAGS), 900 GATE(FCLK_PMU1_CM0_CORE, "fclk_pmu1_cm0_core", "busclk_pdpmu0", 0, 901 RK3562_PMU1_CLKGATE_CON(2), 0, GFLAGS), 902 GATE(CLK_PMU1_CM0_RTC, "clk_pmu1_cm0_rtc", "clk_rtc_32k", 0, 903 RK3562_PMU1_CLKGATE_CON(2), 1, GFLAGS), 904 GATE(PCLK_PMU1_WDTNS, "pclk_pmu1_wdtns", "busclk_pdpmu0", 0, 905 RK3562_PMU1_CLKGATE_CON(2), 3, GFLAGS), 906 GATE(CLK_PMU1_WDTNS, "clk_pmu1_wdtns", "xin24m", 0, 907 RK3562_PMU1_CLKGATE_CON(2), 4, GFLAGS), 908 GATE(PCLK_PMU1_MAILBOX, "pclk_pmu1_mailbox", "busclk_pdpmu0", 0, 909 RK3562_PMU1_CLKGATE_CON(3), 8, GFLAGS), 910 911 /* PD_RGA */ 912 COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", gpll_cpll_pvtpll_dmyapll_p, 0, 913 RK3562_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 4, DFLAGS, 914 RK3562_CLKGATE_CON(14), 0, GFLAGS), 915 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_jdec", 0, 916 RK3562_CLKSEL_CON(32), 8, 3, DFLAGS, 917 RK3562_CLKGATE_CON(14), 1, GFLAGS), 918 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_jdec", 0, 919 RK3562_CLKGATE_CON(14), 6, GFLAGS), 920 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, 921 RK3562_CLKGATE_CON(14), 7, GFLAGS), 922 COMPOSITE(CLK_RGA_CORE, "clk_rga_core", gpll_cpll_pvtpll_dmyapll_p, 0, 923 RK3562_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 4, DFLAGS, 924 RK3562_CLKGATE_CON(14), 8, GFLAGS), 925 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_jdec", 0, 926 RK3562_CLKGATE_CON(14), 9, GFLAGS), 927 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, 928 RK3562_CLKGATE_CON(14), 10, GFLAGS), 929 930 /* PD_VDPU */ 931 COMPOSITE(ACLK_VDPU_PRE, "aclk_vdpu_pre", gpll_cpll_pvtpll_dmyapll_p, 0, 932 RK3562_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 5, DFLAGS, 933 RK3562_CLKGATE_CON(10), 0, GFLAGS), 934 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_pvtpll_dmyapll_p, 0, 935 RK3562_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 5, DFLAGS, 936 RK3562_CLKGATE_CON(10), 3, GFLAGS), 937 COMPOSITE_NOMUX(HCLK_VDPU_PRE, "hclk_vdpu_pre", "aclk_vdpu", 0, 938 RK3562_CLKSEL_CON(24), 0, 4, DFLAGS, 939 RK3562_CLKGATE_CON(10), 4, GFLAGS), 940 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_vdpu", 0, 941 RK3562_CLKGATE_CON(10), 7, GFLAGS), 942 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdpu_pre", 0, 943 RK3562_CLKGATE_CON(10), 8, GFLAGS), 944 945 /* PD_VEPU */ 946 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_pvtpll_dmyapll_p, 0, 947 RK3562_CLKSEL_CON(20), 6, 2, MFLAGS, 0, 5, DFLAGS, 948 RK3562_CLKGATE_CON(9), 0, GFLAGS), 949 COMPOSITE(ACLK_VEPU_PRE, "aclk_vepu_pre", gpll_cpll_pvtpll_dmyapll_p, 0, 950 RK3562_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, 951 RK3562_CLKGATE_CON(9), 1, GFLAGS), 952 COMPOSITE_NOMUX(HCLK_VEPU_PRE, "hclk_vepu_pre", "aclk_vepu", 0, 953 RK3562_CLKSEL_CON(21), 0, 4, DFLAGS, 954 RK3562_CLKGATE_CON(9), 2, GFLAGS), 955 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_vepu", 0, 956 RK3562_CLKGATE_CON(9), 5, GFLAGS), 957 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_vepu", 0, 958 RK3562_CLKGATE_CON(9), 6, GFLAGS), 959 960 /* PD_VI */ 961 COMPOSITE(ACLK_VI, "aclk_vi", gpll_cpll_pvtpll_dmyapll_p, 0, 962 RK3562_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 4, DFLAGS, 963 RK3562_CLKGATE_CON(11), 0, GFLAGS), 964 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi_isp", 0, 965 RK3562_CLKSEL_CON(26), 0, 4, DFLAGS, 966 RK3562_CLKGATE_CON(11), 1, GFLAGS), 967 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi_isp", 0, 968 RK3562_CLKSEL_CON(26), 8, 4, DFLAGS, 969 RK3562_CLKGATE_CON(11), 2, GFLAGS), 970 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_isp", 0, 971 RK3562_CLKGATE_CON(11), 6, GFLAGS), 972 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, 973 RK3562_CLKGATE_CON(11), 7, GFLAGS), 974 COMPOSITE(CLK_ISP, "clk_isp", gpll_cpll_pvtpll_dmyapll_p, 0, 975 RK3562_CLKSEL_CON(27), 6, 2, MFLAGS, 0, 4, DFLAGS, 976 RK3562_CLKGATE_CON(11), 8, GFLAGS), 977 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_isp", 0, 978 RK3562_CLKGATE_CON(11), 9, GFLAGS), 979 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, 980 RK3562_CLKGATE_CON(11), 10, GFLAGS), 981 COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_pvtpll_dmyapll_p, 0, 982 RK3562_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 4, DFLAGS, 983 RK3562_CLKGATE_CON(11), 11, GFLAGS), 984 GATE(CSIRX0_CLK_DATA, "csirx0_clk_data", "csirx0_clk_data_io", 0, 985 RK3562_CLKGATE_CON(11), 12, GFLAGS), 986 GATE(CSIRX1_CLK_DATA, "csirx1_clk_data", "csirx1_clk_data_io", 0, 987 RK3562_CLKGATE_CON(11), 13, GFLAGS), 988 GATE(CSIRX2_CLK_DATA, "csirx2_clk_data", "csirx2_clk_data_io", 0, 989 RK3562_CLKGATE_CON(11), 14, GFLAGS), 990 GATE(CSIRX3_CLK_DATA, "csirx3_clk_data", "csirx3_clk_data_io", 0, 991 RK3562_CLKGATE_CON(11), 15, GFLAGS), 992 GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi", 0, 993 RK3562_CLKGATE_CON(12), 0, GFLAGS), 994 GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi", 0, 995 RK3562_CLKGATE_CON(12), 1, GFLAGS), 996 GATE(PCLK_CSIHOST2, "pclk_csihost2", "pclk_vi", 0, 997 RK3562_CLKGATE_CON(12), 2, GFLAGS), 998 GATE(PCLK_CSIHOST3, "pclk_csihost3", "pclk_vi", 0, 999 RK3562_CLKGATE_CON(12), 3, GFLAGS), 1000 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi", 0, 1001 RK3562_CLKGATE_CON(12), 4, GFLAGS), 1002 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi", 0, 1003 RK3562_CLKGATE_CON(12), 5, GFLAGS), 1004 1005 /* PD_VO */ 1006 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", gpll_cpll_vpll_dmyhpll_p, 0, 1007 RK3562_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 1008 RK3562_CLKGATE_CON(13), 0, GFLAGS), 1009 COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo", 0, 1010 RK3562_CLKSEL_CON(29), 0, 5, DFLAGS, 1011 RK3562_CLKGATE_CON(13), 1, GFLAGS), 1012 GATE(ACLK_VOP, "aclk_vop", "aclk_vo", 0, 1013 RK3562_CLKGATE_CON(13), 6, GFLAGS), 1014 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_pre", 0, 1015 RK3562_CLKGATE_CON(13), 7, GFLAGS), 1016 COMPOSITE(DCLK_VOP, "dclk_vop", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT, 1017 RK3562_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 8, DFLAGS, 1018 RK3562_CLKGATE_CON(13), 8, GFLAGS), 1019 COMPOSITE(DCLK_VOP1, "dclk_vop1", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT, 1020 RK3562_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 8, DFLAGS, 1021 RK3562_CLKGATE_CON(13), 9, GFLAGS), 1022}; 1023 1024static void __init rk3562_clk_init(struct device_node *np) 1025{ 1026 struct rockchip_clk_provider *ctx; 1027 unsigned long clk_nr_clks; 1028 void __iomem *reg_base; 1029 1030 clk_nr_clks = rockchip_clk_find_max_clk_id(rk3562_clk_branches, 1031 ARRAY_SIZE(rk3562_clk_branches)) + 1; 1032 1033 reg_base = of_iomap(np, 0); 1034 if (!reg_base) { 1035 pr_err("%s: could not map cru region\n", __func__); 1036 return; 1037 } 1038 1039 ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); 1040 if (IS_ERR(ctx)) { 1041 pr_err("%s: rockchip clk init failed\n", __func__); 1042 iounmap(reg_base); 1043 return; 1044 } 1045 1046 rockchip_clk_register_plls(ctx, rk3562_pll_clks, 1047 ARRAY_SIZE(rk3562_pll_clks), 1048 RK3562_GRF_SOC_STATUS0); 1049 1050 rockchip_clk_register_branches(ctx, rk3562_clk_branches, 1051 ARRAY_SIZE(rk3562_clk_branches)); 1052 1053 rk3562_rst_init(np, reg_base); 1054 1055 rockchip_register_restart_notifier(ctx, RK3562_GLB_SRST_FST, NULL); 1056 1057 rockchip_clk_of_add_provider(np, ctx); 1058} 1059 1060CLK_OF_DECLARE(rk3562_cru, "rockchip,rk3562-cru", rk3562_clk_init); 1061 1062struct clk_rk3562_inits { 1063 void (*inits)(struct device_node *np); 1064}; 1065 1066static const struct clk_rk3562_inits clk_rk3562_cru_init = { 1067 .inits = rk3562_clk_init, 1068}; 1069 1070static const struct of_device_id clk_rk3562_match_table[] = { 1071 { 1072 .compatible = "rockchip,rk3562-cru", 1073 .data = &clk_rk3562_cru_init, 1074 }, 1075 { } 1076}; 1077 1078static int clk_rk3562_probe(struct platform_device *pdev) 1079{ 1080 const struct clk_rk3562_inits *init_data; 1081 struct device *dev = &pdev->dev; 1082 1083 init_data = device_get_match_data(dev); 1084 if (!init_data) 1085 return -EINVAL; 1086 1087 if (init_data->inits) 1088 init_data->inits(dev->of_node); 1089 1090 return 0; 1091} 1092 1093static struct platform_driver clk_rk3562_driver = { 1094 .probe = clk_rk3562_probe, 1095 .driver = { 1096 .name = "clk-rk3562", 1097 .of_match_table = clk_rk3562_match_table, 1098 .suppress_bind_attrs = true, 1099 }, 1100}; 1101builtin_platform_driver_probe(clk_rk3562_driver, clk_rk3562_probe);
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