rzv2h-cpg.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Renesas RZ/V2H(P) Clock Pulse Generator
  4 *
  5 * Copyright (C) 2024 Renesas Electronics Corp.
  6 */
  7
  8#ifndef __RENESAS_RZV2H_CPG_H__
  9#define __RENESAS_RZV2H_CPG_H__
 10
 11#include <linux/bitfield.h>
 12#include <linux/types.h>
 13
 14/**
 15 * struct pll - Structure for PLL configuration
 16 *
 17 * @offset: STBY register offset
 18 * @has_clkn: Flag to indicate if CLK1/2 are accessible or not
 19 * @instance: PLL instance number
 20 */
 21struct pll {
 22	unsigned int offset:9;
 23	unsigned int has_clkn:1;
 24	unsigned int instance:2;
 25	const struct rzv2h_pll_limits *limits;
 26};
 27
 28#define PLL_PACK_LIMITS(_offset, _has_clkn, _instance, _limits) \
 29	((struct pll){ \
 30		.offset = _offset, \
 31		.has_clkn = _has_clkn, \
 32		.instance = _instance, \
 33		.limits = _limits \
 34	})
 35
 36#define PLL_PACK(_offset, _has_clkn, _instance) \
 37	PLL_PACK_LIMITS(_offset, _has_clkn, _instance, NULL)
 38
 39#define PLLCA55		PLL_PACK(0x60, 1, 0)
 40#define PLLGPU		PLL_PACK(0x120, 1, 0)
 41
 42/**
 43 * struct ddiv - Structure for dynamic switching divider
 44 *
 45 * @offset: register offset
 46 * @shift: position of the divider bit
 47 * @width: width of the divider
 48 * @monbit: monitor bit in CPG_CLKSTATUS0 register
 49 * @no_rmw: flag to indicate if the register is read-modify-write
 50 *        (1: no RMW, 0: RMW)
 51 */
 52struct ddiv {
 53	unsigned int offset:11;
 54	unsigned int shift:4;
 55	unsigned int width:4;
 56	unsigned int monbit:5;
 57	unsigned int no_rmw:1;
 58};
 59
 60/*
 61 * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits,
 62 * while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value
 63 * `0x1f` to indicate that monitor bits are not supported for static divider
 64 * clocks.
 65 */
 66#define CSDIV_NO_MON	(0x1f)
 67
 68#define DDIV_PACK(_offset, _shift, _width, _monbit) \
 69	((struct ddiv){ \
 70		.offset = _offset, \
 71		.shift = _shift, \
 72		.width = _width, \
 73		.monbit = _monbit \
 74	})
 75
 76#define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \
 77	((struct ddiv){ \
 78		.offset = (_offset), \
 79		.shift = (_shift), \
 80		.width = (_width), \
 81		.monbit = (_monbit), \
 82		.no_rmw = 1 \
 83	})
 84
 85/**
 86 * struct smuxed - Structure for static muxed clocks
 87 *
 88 * @offset: register offset
 89 * @shift: position of the divider field
 90 * @width: width of the divider field
 91 */
 92struct smuxed {
 93	unsigned int offset:11;
 94	unsigned int shift:4;
 95	unsigned int width:4;
 96};
 97
 98#define SMUX_PACK(_offset, _shift, _width) \
 99	((struct smuxed){ \
100		.offset = (_offset), \
101		.shift = (_shift), \
102		.width = (_width), \
103	})
104
105/**
106 * struct fixed_mod_conf - Structure for fixed module configuration
107 *
108 * @mon_index: monitor index
109 * @mon_bit: monitor bit
110 */
111struct fixed_mod_conf {
112	u8 mon_index;
113	u8 mon_bit;
114};
115
116#define FIXED_MOD_CONF_PACK(_index, _bit) \
117	((struct fixed_mod_conf){ \
118		.mon_index = (_index), \
119		.mon_bit = (_bit), \
120	})
121
122#define CPG_SSEL0		(0x300)
123#define CPG_SSEL1		(0x304)
124#define CPG_CDDIV0		(0x400)
125#define CPG_CDDIV1		(0x404)
126#define CPG_CDDIV2		(0x408)
127#define CPG_CDDIV3		(0x40C)
128#define CPG_CDDIV4		(0x410)
129#define CPG_CSDIV0		(0x500)
130#define CPG_CSDIV1		(0x504)
131
132#define CDDIV0_DIVCTL1	DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
133#define CDDIV0_DIVCTL2	DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
134#define CDDIV1_DIVCTL0	DDIV_PACK(CPG_CDDIV1, 0, 2, 4)
135#define CDDIV1_DIVCTL1	DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
136#define CDDIV1_DIVCTL2	DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
137#define CDDIV1_DIVCTL3	DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
138#define CDDIV2_DIVCTL3	DDIV_PACK(CPG_CDDIV2, 12, 3, 11)
139#define CDDIV3_DIVCTL1	DDIV_PACK(CPG_CDDIV3, 4, 3, 13)
140#define CDDIV3_DIVCTL2	DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
141#define CDDIV3_DIVCTL3	DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
142#define CDDIV4_DIVCTL0	DDIV_PACK(CPG_CDDIV4, 0, 1, 16)
143#define CDDIV4_DIVCTL1	DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
144#define CDDIV4_DIVCTL2	DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
145
146#define CSDIV0_DIVCTL0	DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
147#define CSDIV0_DIVCTL1	DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
148#define CSDIV0_DIVCTL2	DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON)
149#define CSDIV0_DIVCTL3	DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
150#define CSDIV1_DIVCTL2	DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON)
151
152#define SSEL0_SELCTL2	SMUX_PACK(CPG_SSEL0, 8, 1)
153#define SSEL0_SELCTL3	SMUX_PACK(CPG_SSEL0, 12, 1)
154#define SSEL1_SELCTL0	SMUX_PACK(CPG_SSEL1, 0, 1)
155#define SSEL1_SELCTL1	SMUX_PACK(CPG_SSEL1, 4, 1)
156#define SSEL1_SELCTL2	SMUX_PACK(CPG_SSEL1, 8, 1)
157#define SSEL1_SELCTL3	SMUX_PACK(CPG_SSEL1, 12, 1)
158
159#define BUS_MSTOP_IDX_MASK	GENMASK(31, 16)
160#define BUS_MSTOP_BITS_MASK	GENMASK(15, 0)
161#define BUS_MSTOP(idx, mask)	(FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
162				 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
163#define BUS_MSTOP_NONE		GENMASK(31, 0)
164
165#define FIXED_MOD_CONF_XSPI	FIXED_MOD_CONF_PACK(5, 1)
166
167/**
168 * Definitions of CPG Core Clocks
169 *
170 * These include:
171 *   - Clock outputs exported to DT
172 *   - External input clocks
173 *   - Internal CPG clocks
174 */
175struct cpg_core_clk {
176	const char *name;
177	unsigned int id;
178	unsigned int parent;
179	unsigned int div;
180	unsigned int mult;
181	unsigned int type;
182	union {
183		unsigned int conf;
184		struct ddiv ddiv;
185		struct pll pll;
186		struct smuxed smux;
187		struct fixed_mod_conf fixed_mod;
188	} cfg;
189	const struct clk_div_table *dtable;
190	const char * const *parent_names;
191	unsigned int num_parents;
192	u8 mux_flags;
193	u32 flag;
194};
195
196enum clk_types {
197	/* Generic */
198	CLK_TYPE_IN,		/* External Clock Input */
199	CLK_TYPE_FF,		/* Fixed Factor Clock */
200	CLK_TYPE_FF_MOD_STATUS,	/* Fixed Factor Clock which can report the status of module clock */
201	CLK_TYPE_PLL,
202	CLK_TYPE_DDIV,		/* Dynamic Switching Divider */
203	CLK_TYPE_SMUX,		/* Static Mux */
204	CLK_TYPE_PLLDSI,	/* PLLDSI */
205	CLK_TYPE_PLLDSI_DIV,	/* PLLDSI divider */
206};
207
208#define DEF_TYPE(_name, _id, _type...) \
209	{ .name = _name, .id = _id, .type = _type }
210#define DEF_BASE(_name, _id, _type, _parent...) \
211	DEF_TYPE(_name, _id, _type, .parent = _parent)
212#define DEF_PLL(_name, _id, _parent, _pll_packed) \
213	DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed)
214#define DEF_INPUT(_name, _id) \
215	DEF_TYPE(_name, _id, CLK_TYPE_IN)
216#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
217	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
218#define DEF_FIXED_MOD_STATUS(_name, _id, _parent, _mult, _div, _gate) \
219	DEF_BASE(_name, _id, CLK_TYPE_FF_MOD_STATUS, _parent, .div = _div, \
220		 .mult = _mult, .cfg.fixed_mod = _gate)
221#define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
222	DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
223		.cfg.ddiv = _ddiv_packed, \
224		.parent = _parent, \
225		.dtable = _dtable, \
226		.flag = CLK_DIVIDER_HIWORD_MASK)
227#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
228	DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable)
229#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
230	DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
231		 .cfg.smux = _smux_packed, \
232		 .parent_names = _parent_names, \
233		 .num_parents = ARRAY_SIZE(_parent_names), \
234		 .flag = CLK_SET_RATE_PARENT, \
235		 .mux_flags = CLK_MUX_HIWORD_MASK)
236#define DEF_PLLDSI(_name, _id, _parent, _pll_packed) \
237	DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI, .parent = _parent, .cfg.pll = _pll_packed)
238#define DEF_PLLDSI_DIV(_name, _id, _parent, _ddiv_packed, _dtable) \
239	DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_DIV, \
240		 .cfg.ddiv = _ddiv_packed, \
241		 .dtable = _dtable, \
242		 .parent = _parent, \
243		 .flag = CLK_SET_RATE_PARENT)
244
245/**
246 * struct rzv2h_mod_clk - Module Clocks definitions
247 *
248 * @name: handle between common and hardware-specific interfaces
249 * @mstop_data: packed data mstop register offset and mask
250 * @parent: id of parent clock
251 * @critical: flag to indicate the clock is critical
252 * @no_pm: flag to indicate PM is not supported
253 * @on_index: control register index
254 * @on_bit: ON bit
255 * @mon_index: monitor register index
256 * @mon_bit: monitor bit
257 * @ext_clk_mux_index: mux index for external clock source, or -1 if internal
258 */
259struct rzv2h_mod_clk {
260	const char *name;
261	u32 mstop_data;
262	u16 parent;
263	bool critical;
264	bool no_pm;
265	u8 on_index;
266	u8 on_bit;
267	s8 mon_index;
268	u8 mon_bit;
269	s8 ext_clk_mux_index;
270};
271
272#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \
273		     _onbit, _monindex, _monbit, _ext_clk_mux_index) \
274	{ \
275		.name = (_name), \
276		.mstop_data = (_mstop), \
277		.parent = (_parent), \
278		.critical = (_critical), \
279		.no_pm = (_no_pm), \
280		.on_index = (_onindex), \
281		.on_bit = (_onbit), \
282		.mon_index = (_monindex), \
283		.mon_bit = (_monbit), \
284		.ext_clk_mux_index = (_ext_clk_mux_index), \
285	}
286
287#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
288	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1)
289
290#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
291	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1)
292
293#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
294	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1)
295
296#define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
297			     _ext_clk_mux_index) \
298	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
299		     _ext_clk_mux_index)
300
301/**
302 * struct rzv2h_reset - Reset definitions
303 *
304 * @reset_index: reset register index
305 * @reset_bit: reset bit
306 * @mon_index: monitor register index
307 * @mon_bit: monitor bit
308 */
309struct rzv2h_reset {
310	u8 reset_index;
311	u8 reset_bit;
312	u8 mon_index;
313	u8 mon_bit;
314};
315
316#define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)	\
317	{ \
318		.reset_index = (_resindex), \
319		.reset_bit = (_resbit), \
320		.mon_index = (_monindex), \
321		.mon_bit = (_monbit), \
322	}
323
324#define DEF_RST(_resindex, _resbit, _monindex, _monbit)	\
325	DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)
326
327/**
328 * struct rzv2h_cpg_info - SoC-specific CPG Description
329 *
330 * @core_clks: Array of Core Clock definitions
331 * @num_core_clks: Number of entries in core_clks[]
332 * @last_dt_core_clk: ID of the last Core Clock exported to DT
333 * @num_total_core_clks: Total number of Core Clocks (exported + internal)
334 *
335 * @mod_clks: Array of Module Clock definitions
336 * @num_mod_clks: Number of entries in mod_clks[]
337 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
338 *
339 * @resets: Array of Module Reset definitions
340 * @num_resets: Number of entries in resets[]
341 *
342 * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the
343 *		    number of CPG_BUS_m_MSTOP registers multiplied by 16.
344 */
345struct rzv2h_cpg_info {
346	/* Core Clocks */
347	const struct cpg_core_clk *core_clks;
348	unsigned int num_core_clks;
349	unsigned int last_dt_core_clk;
350	unsigned int num_total_core_clks;
351
352	/* Module Clocks */
353	const struct rzv2h_mod_clk *mod_clks;
354	unsigned int num_mod_clks;
355	unsigned int num_hw_mod_clks;
356
357	/* Resets */
358	const struct rzv2h_reset *resets;
359	unsigned int num_resets;
360
361	unsigned int num_mstop_bits;
362};
363
364extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
365extern const struct rzv2h_cpg_info r9a09g056_cpg_info;
366extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
367
368#endif	/* __RENESAS_RZV2H_CPG_H__ */