rzg2l-cpg.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * RZ/G2L Clock Pulse Generator
  4 *
  5 * Copyright (C) 2021 Renesas Electronics Corp.
  6 *
  7 */
  8
  9#ifndef __RENESAS_RZG2L_CPG_H__
 10#define __RENESAS_RZG2L_CPG_H__
 11
 12#include <linux/notifier.h>
 13
 14#define CPG_SIPLL5_STBY		(0x140)
 15#define CPG_SIPLL5_CLK1		(0x144)
 16#define CPG_SIPLL5_CLK3		(0x14C)
 17#define CPG_SIPLL5_CLK4		(0x150)
 18#define CPG_SIPLL5_CLK5		(0x154)
 19#define CPG_SIPLL5_MON		(0x15C)
 20#define CPG_PL1_DDIV		(0x200)
 21#define CPG_PL2_DDIV		(0x204)
 22#define CPG_PL3A_DDIV		(0x208)
 23#define CPG_PL6_DDIV		(0x210)
 24#define CPG_PL3C_SDIV		(0x214)
 25#define CPG_CLKSTATUS		(0x280)
 26#define CPG_PL3_SSEL		(0x408)
 27#define CPG_PL6_SSEL		(0x414)
 28#define CPG_PL6_ETH_SSEL	(0x418)
 29#define CPG_PL5_SDIV		(0x420)
 30#define CPG_RST_MON		(0x680)
 31#define CPG_BUS_ACPU_MSTOP	(0xB60)
 32#define CPG_BUS_MCPU1_MSTOP	(0xB64)
 33#define CPG_BUS_MCPU2_MSTOP	(0xB68)
 34#define CPG_BUS_PERI_COM_MSTOP	(0xB6C)
 35#define CPG_BUS_PERI_CPU_MSTOP	(0xB70)
 36#define CPG_BUS_PERI_DDR_MSTOP	(0xB74)
 37#define CPG_BUS_PERI_VIDEO_MSTOP (0xB78)
 38#define CPG_BUS_REG0_MSTOP	(0xB7C)
 39#define CPG_BUS_REG1_MSTOP	(0xB80)
 40#define CPG_BUS_TZCDDR_MSTOP	(0xB84)
 41#define CPG_MHU_MSTOP		(0xB88)
 42#define CPG_BUS_MCPU3_MSTOP	(0xB90)
 43#define CPG_BUS_PERI_CPU2_MSTOP	(0xB94)
 44#define CPG_OTHERFUNC1_REG	(0xBE8)
 45
 46#define CPG_SIPLL5_STBY_RESETB		BIT(0)
 47#define CPG_SIPLL5_STBY_RESETB_WEN	BIT(16)
 48#define CPG_SIPLL5_STBY_SSCG_EN_WEN	BIT(18)
 49#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN	BIT(20)
 50#define CPG_SIPLL5_CLK4_RESV_LSB	(0xFF)
 51#define CPG_SIPLL5_MON_PLL5_LOCK	BIT(4)
 52
 53#define CPG_OTHERFUNC1_REG_RES0_ON_WEN	BIT(16)
 54
 55#define CPG_PL5_SDIV_DIV_DSI_A_WEN	BIT(16)
 56#define CPG_PL5_SDIV_DIV_DSI_B_WEN	BIT(24)
 57
 58#define CPG_CLKSTATUS_SELSDHI0_STS	BIT(28)
 59#define CPG_CLKSTATUS_SELSDHI1_STS	BIT(29)
 60
 61/* n = 0/1/2 for PLL1/4/6 */
 62#define CPG_SAMPLL_CLK1(n)	(0x04 + (16 * n))
 63#define CPG_SAMPLL_CLK2(n)	(0x08 + (16 * n))
 64
 65#define PLL146_CONF(n)	(CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
 66
 67#define DDIV_PACK(offset, bitpos, size) \
 68		(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
 69#define DIVPL1A		DDIV_PACK(CPG_PL1_DDIV, 0, 2)
 70#define DIVPL2A		DDIV_PACK(CPG_PL2_DDIV, 0, 3)
 71#define DIVDSILPCLK	DDIV_PACK(CPG_PL2_DDIV, 12, 2)
 72#define DIVPL3A		DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
 73#define DIVPL3B		DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
 74#define DIVPL3C		DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
 75#define DIVPL3E		DDIV_PACK(CPG_PL3C_SDIV, 8, 5)
 76#define DIVGPU		DDIV_PACK(CPG_PL6_DDIV, 0, 2)
 77
 78#define SEL_PLL_PACK(offset, bitpos, size) \
 79		(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
 80
 81#define SEL_PLL3_3	SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
 82#define SEL_PLL5_4	SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1)
 83#define SEL_PLL6_2	SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
 84#define SEL_GPU2	SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
 85
 86#define MSTOP(name, bitmask)	((CPG_##name##_MSTOP) << 16 | (bitmask))
 87
 88#define EXTAL_FREQ_IN_MEGA_HZ	(24)
 89
 90/**
 91 * Definitions of CPG Core Clocks
 92 *
 93 * These include:
 94 *   - Clock outputs exported to DT
 95 *   - External input clocks
 96 *   - Internal CPG clocks
 97 */
 98struct cpg_core_clk {
 99	const char *name;
100	unsigned int id;
101	unsigned int parent;
102	unsigned int div;
103	unsigned int mult;
104	unsigned int type;
105	unsigned int conf;
106	unsigned int sconf;
107	const struct clk_div_table *dtable;
108	const u32 *mtable;
109	const unsigned long invalid_rate;
110	union {
111		const unsigned long max_rate;
112		const unsigned long default_rate;
113	};
114	const char * const *parent_names;
115	notifier_fn_t notifier;
116	u32 flag;
117	u32 mux_flags;
118	int num_parents;
119};
120
121enum clk_types {
122	/* Generic */
123	CLK_TYPE_IN,		/* External Clock Input */
124	CLK_TYPE_FF,		/* Fixed Factor Clock */
125	CLK_TYPE_SAM_PLL,
126	CLK_TYPE_G3S_PLL,
127
128	/* Clock with divider */
129	CLK_TYPE_DIV,
130	CLK_TYPE_G3S_DIV,
131
132	/* Clock with clock source selector */
133	CLK_TYPE_MUX,
134
135	/* Clock with SD clock source selector */
136	CLK_TYPE_SD_MUX,
137
138	/* Clock for SIPLL5 */
139	CLK_TYPE_SIPLL5,
140
141	/* Clock for PLL5_4 clock source selector */
142	CLK_TYPE_PLL5_4_MUX,
143
144	/* Clock for DSI divider */
145	CLK_TYPE_DSI_DIV,
146
147};
148
149#define DEF_TYPE(_name, _id, _type...) \
150	{ .name = _name, .id = _id, .type = _type }
151#define DEF_BASE(_name, _id, _type, _parent...) \
152	DEF_TYPE(_name, _id, _type, .parent = _parent)
153#define DEF_SAMPLL(_name, _id, _parent, _conf) \
154	DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
155#define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \
156	DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
157		 .default_rate = _default_rate)
158#define DEF_INPUT(_name, _id) \
159	DEF_TYPE(_name, _id, CLK_TYPE_IN)
160#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
161	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
162#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
163	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
164		 .parent = _parent, .dtable = _dtable, \
165		 .flag = CLK_DIVIDER_HIWORD_MASK)
166#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
167	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
168		 .parent = _parent, .dtable = _dtable, \
169		 .flag = CLK_DIVIDER_READ_ONLY)
170#define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \
171		    _max_rate, _clk_flags, _notif) \
172	DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \
173		 .parent = _parent, .dtable = _dtable, \
174		 .invalid_rate = _invalid_rate, \
175		 .max_rate = _max_rate, .flag = (_clk_flags), \
176		 .notifier = _notif)
177#define DEF_MUX(_name, _id, _conf, _parent_names) \
178	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
179		 .parent_names = _parent_names, \
180		 .num_parents = ARRAY_SIZE(_parent_names), \
181		 .mux_flags = CLK_MUX_HIWORD_MASK)
182#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
183	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
184		 .parent_names = _parent_names, \
185		 .num_parents = ARRAY_SIZE(_parent_names), \
186		 .mux_flags = CLK_MUX_READ_ONLY)
187#define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \
188	DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \
189		 .parent_names = _parent_names, \
190		 .num_parents = ARRAY_SIZE(_parent_names), \
191		 .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier)
192#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
193	DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
194#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \
195	DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
196		 .parent_names = _parent_names, \
197		 .num_parents = ARRAY_SIZE(_parent_names))
198#define DEF_DSI_DIV(_name, _id, _parent, _flag) \
199	DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)
200
201/**
202 * struct rzg2l_mod_clk - Module Clocks definitions
203 *
204 * @name: handle between common and hardware-specific interfaces
205 * @id: clock index in array containing all Core and Module Clocks
206 * @parent: id of parent clock
207 * @mstop_conf: MSTOP configuration
208 * @off: register offset
209 * @bit: ON/MON bit
210 * @is_coupled: flag to indicate coupled clock
211 */
212struct rzg2l_mod_clk {
213	const char *name;
214	unsigned int id;
215	unsigned int parent;
216	u32 mstop_conf;
217	u16 off;
218	u8 bit;
219	bool is_coupled;
220};
221
222#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled)	\
223	{ \
224		.name = _name, \
225		.id = MOD_CLK_BASE + (_id), \
226		.parent = (_parent), \
227		.mstop_conf = (_mstop_conf), \
228		.off = (_off), \
229		.bit = (_bit), \
230		.is_coupled = (_is_coupled), \
231	}
232
233#define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf)	\
234	DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false)
235
236#define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf)	\
237	DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true)
238
239/**
240 * struct rzg2l_reset - Reset definitions
241 *
242 * @off: register offset
243 * @bit: reset bit
244 * @monbit: monitor bit in CPG_RST_MON register, -1 if none
245 */
246struct rzg2l_reset {
247	u16 off;
248	u8 bit;
249	s8 monbit;
250};
251
252#define DEF_RST_MON(_id, _off, _bit, _monbit)	\
253	[_id] = { \
254		.off = (_off), \
255		.bit = (_bit), \
256		.monbit = (_monbit) \
257	}
258#define DEF_RST(_id, _off, _bit)	\
259	DEF_RST_MON(_id, _off, _bit, -1)
260
261/**
262 * struct rzg2l_cpg_info - SoC-specific CPG Description
263 *
264 * @core_clks: Array of Core Clock definitions
265 * @num_core_clks: Number of entries in core_clks[]
266 * @last_dt_core_clk: ID of the last Core Clock exported to DT
267 * @num_total_core_clks: Total number of Core Clocks (exported + internal)
268 *
269 * @mod_clks: Array of Module Clock definitions
270 * @num_mod_clks: Number of entries in mod_clks[]
271 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
272 *
273 * @resets: Array of Module Reset definitions
274 * @num_resets: Number of entries in resets[]
275 *
276 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
277 *                 should not be disabled without a knowledgeable driver
278 * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
279 * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
280 */
281struct rzg2l_cpg_info {
282	/* Core Clocks */
283	const struct cpg_core_clk *core_clks;
284	unsigned int num_core_clks;
285	unsigned int last_dt_core_clk;
286	unsigned int num_total_core_clks;
287
288	/* Module Clocks */
289	const struct rzg2l_mod_clk *mod_clks;
290	unsigned int num_mod_clks;
291	unsigned int num_hw_mod_clks;
292
293	/* No PM Module Clocks */
294	const unsigned int *no_pm_mod_clks;
295	unsigned int num_no_pm_mod_clks;
296
297	/* Resets */
298	const struct rzg2l_reset *resets;
299	unsigned int num_resets;
300
301	/* Critical Module Clocks that should not be disabled */
302	const unsigned int *crit_mod_clks;
303	unsigned int num_crit_mod_clks;
304
305	bool has_clk_mon_regs;
306};
307
308extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
309extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
310extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
311extern const struct rzg2l_cpg_info r9a08g045_cpg_info;
312extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
313
314int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data);
315int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data);
316
317#endif