renesas-cpg-mssr.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
  4 *
  5 * Copyright (C) 2015 Glider bvba
  6 */
  7
  8#ifndef __CLK_RENESAS_CPG_MSSR_H__
  9#define __CLK_RENESAS_CPG_MSSR_H__
 10
 11#include <linux/notifier.h>
 12
 13    /*
 14     * Definitions of CPG Core Clocks
 15     *
 16     * These include:
 17     *   - Clock outputs exported to DT
 18     *   - External input clocks
 19     *   - Internal CPG clocks
 20     */
 21
 22struct cpg_core_clk {
 23	/* Common */
 24	const char *name;
 25	unsigned int id;
 26	unsigned int type;
 27	/* Depending on type */
 28	unsigned int parent;	/* Core Clocks only */
 29	unsigned int div;
 30	unsigned int mult;
 31	unsigned int offset;
 32	union {
 33		const char * const *parent_names;
 34		const struct clk_div_table *dtable;
 35	};
 36	u32 conf;
 37	u16 flag;
 38	u8 mux_flags;
 39	u8 num_parents;
 40};
 41
 42/**
 43 * struct cpg_mssr_pub - data shared with device-specific clk registration code
 44 *
 45 * @base0: CPG/MSSR register block base0 address
 46 * @base1: CPG/MSSR register block base1 address
 47 * @notifiers: Notifier chain to save/restore clock state for system resume
 48 * @rmw_lock: protects RMW register accesses
 49 * @clks: pointer to clocks
 50 */
 51struct cpg_mssr_pub {
 52	void __iomem *base0;
 53	void __iomem *base1;
 54	struct raw_notifier_head notifiers;
 55	spinlock_t rmw_lock;
 56	struct clk **clks;
 57};
 58
 59enum clk_types {
 60	/* Generic */
 61	CLK_TYPE_IN,		/* External Clock Input */
 62	CLK_TYPE_FF,		/* Fixed Factor Clock */
 63	CLK_TYPE_DIV6P1,	/* DIV6 Clock with 1 parent clock */
 64	CLK_TYPE_DIV6_RO,	/* DIV6 Clock read only with extra divisor */
 65	CLK_TYPE_FR,		/* Fixed Rate Clock */
 66
 67	/* Custom definitions start here */
 68	CLK_TYPE_CUSTOM,
 69};
 70
 71#define DEF_TYPE(_name, _id, _type...)	\
 72	{ .name = _name, .id = _id, .type = _type }
 73#define DEF_BASE(_name, _id, _type, _parent...)	\
 74	DEF_TYPE(_name, _id, _type, .parent = _parent)
 75
 76#define DEF_INPUT(_name, _id) \
 77	DEF_TYPE(_name, _id, CLK_TYPE_IN)
 78#define DEF_FIXED(_name, _id, _parent, _div, _mult)	\
 79	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
 80#define DEF_DIV6P1(_name, _id, _parent, _offset)	\
 81	DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
 82#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div)	\
 83	DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
 84#define DEF_RATE(_name, _id, _rate)	\
 85	DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
 86
 87    /*
 88     * Definitions of Module Clocks
 89     */
 90
 91struct mssr_mod_clk {
 92	const char *name;
 93	unsigned int id;
 94	unsigned int parent;	/* Add MOD_CLK_BASE for Module Clocks */
 95};
 96
 97/* Convert from sparse base-100 to packed index space */
 98#define MOD_CLK_PACK(x)	((x) - ((x) / 100) * (100 - 32))
 99
100#define MOD_CLK_ID(x)	(MOD_CLK_BASE + MOD_CLK_PACK(x))
101
102#define DEF_MOD(_name, _mod, _parent...)	\
103	{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
104
105/* Convert from sparse base-10 to packed index space */
106#define MOD_CLK_PACK_10(x)	((x / 10) * 32 + (x % 10))
107
108#define MOD_CLK_ID_10(x)	(MOD_CLK_BASE + MOD_CLK_PACK_10(x))
109
110#define DEF_MOD_STB(_name, _mod, _parent...)	\
111	{ .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
112
113struct device_node;
114
115enum clk_reg_layout {
116	CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
117	CLK_REG_LAYOUT_RZ_A,
118	CLK_REG_LAYOUT_RCAR_GEN4,
119	CLK_REG_LAYOUT_RZ_T2H,
120};
121
122    /**
123     * SoC-specific CPG/MSSR Description
124     *
125     * @early_core_clks: Array of Early Core Clock definitions
126     * @num_early_core_clks: Number of entries in early_core_clks[]
127     * @early_mod_clks: Array of Early Module Clock definitions
128     * @num_early_mod_clks: Number of entries in early_mod_clks[]
129     *
130     * @core_clks: Array of Core Clock definitions
131     * @num_core_clks: Number of entries in core_clks[]
132     * @last_dt_core_clk: ID of the last Core Clock exported to DT
133     * @num_total_core_clks: Total number of Core Clocks (exported + internal)
134     *
135     * @mod_clks: Array of Module Clock definitions
136     * @num_mod_clks: Number of entries in mod_clks[]
137     * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
138     *
139     * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
140     *                 should not be disabled without a knowledgeable driver
141     * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
142     * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
143     *
144     * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
145     *                Management, in addition to Module Clocks
146     * @num_core_pm_clks: Number of entries in core_pm_clks[]
147     *
148     * @init: Optional callback to perform SoC-specific initialization
149     * @cpg_clk_register: Optional callback to handle special Core Clock types
150     */
151
152struct cpg_mssr_info {
153	/* Early Clocks */
154	const struct cpg_core_clk *early_core_clks;
155	unsigned int num_early_core_clks;
156	const struct mssr_mod_clk *early_mod_clks;
157	unsigned int num_early_mod_clks;
158
159	/* Core Clocks */
160	const struct cpg_core_clk *core_clks;
161	unsigned int num_core_clks;
162	unsigned int last_dt_core_clk;
163	unsigned int num_total_core_clks;
164	enum clk_reg_layout reg_layout;
165
166	/* Module Clocks */
167	const struct mssr_mod_clk *mod_clks;
168	unsigned int num_mod_clks;
169	unsigned int num_hw_mod_clks;
170
171	/* Critical Module Clocks that should not be disabled */
172	const unsigned int *crit_mod_clks;
173	unsigned int num_crit_mod_clks;
174
175	/* Core Clocks suitable for PM, in addition to the Module Clocks */
176	const unsigned int *core_pm_clks;
177	unsigned int num_core_pm_clks;
178
179	/* Callbacks */
180	int (*init)(struct device *dev);
181	struct clk *(*cpg_clk_register)(struct device *dev,
182					const struct cpg_core_clk *core,
183					const struct cpg_mssr_info *info,
184					struct cpg_mssr_pub *pub);
185};
186
187extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
188extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
189extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
190extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
191extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
192extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
193extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
194extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
195extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;
196extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
197extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
198extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
199extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
200extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
201extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
202extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
203extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
204extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
205extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
206extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
207extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
208extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
209extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;
210extern const struct cpg_mssr_info r8a779h0_cpg_mssr_info;
211extern const struct cpg_mssr_info r9a09g077_cpg_mssr_info;
212
213void __init cpg_mssr_early_init(struct device_node *np,
214				const struct cpg_mssr_info *info);
215
216    /*
217     * Helpers for fixing up clock tables depending on SoC revision
218     */
219extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
220			     unsigned int num_mod_clks,
221			     const unsigned int *clks, unsigned int n);
222#endif