rcar-gen4-cpg.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * R-Car Gen4 Clock Pulse Generator
  4 *
  5 * Copyright (C) 2021 Renesas Electronics Corp.
  6 *
  7 * Based on rcar-gen3-cpg.c
  8 *
  9 * Copyright (C) 2015-2018 Glider bvba
 10 * Copyright (C) 2019 Renesas Electronics Corp.
 11 */
 12
 13#include <linux/bitfield.h>
 14#include <linux/clk.h>
 15#include <linux/clk-provider.h>
 16#include <linux/device.h>
 17#include <linux/err.h>
 18#include <linux/init.h>
 19#include <linux/io.h>
 20#include <linux/iopoll.h>
 21#include <linux/slab.h>
 22
 23#include "renesas-cpg-mssr.h"
 24#include "rcar-gen4-cpg.h"
 25#include "rcar-cpg-lib.h"
 26
 27static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata;
 28static unsigned int cpg_clk_extalr __initdata;
 29static u32 cpg_mode __initdata;
 30
 31#define CPG_PLLECR		0x0820	/* PLL Enable Control Register */
 32
 33#define CPG_PLLECR_PLLST(n)	BIT(8 + ((n) < 3 ? (n) - 1 : \
 34					 (n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */
 35
 36#define CPG_PLL1CR0		0x830	/* PLLn Control Registers */
 37#define CPG_PLL1CR1		0x8b0
 38#define CPG_PLL2CR0		0x834
 39#define CPG_PLL2CR1		0x8b8
 40#define CPG_PLL3CR0		0x83c
 41#define CPG_PLL3CR1		0x8c0
 42#define CPG_PLL4CR0		0x844
 43#define CPG_PLL4CR1		0x8c8
 44#define CPG_PLL6CR0		0x84c
 45#define CPG_PLL6CR1		0x8d8
 46
 47#define CPG_PLLxCR0_KICK	BIT(31)
 48#define CPG_PLLxCR0_SSMODE	GENMASK(18, 16)	/* PLL mode */
 49#define CPG_PLLxCR0_SSMODE_FM	BIT(18)	/* Fractional Multiplication */
 50#define CPG_PLLxCR0_SSMODE_DITH	BIT(17) /* Frequency Dithering */
 51#define CPG_PLLxCR0_SSMODE_CENT	BIT(16)	/* Center (vs. Down) Spread Dithering */
 52#define CPG_PLLxCR0_SSFREQ	GENMASK(14, 8)	/* SSCG Modulation Frequency */
 53#define CPG_PLLxCR0_SSDEPT	GENMASK(6, 0)	/* SSCG Modulation Depth */
 54
 55/* Fractional 8.25 PLL */
 56#define CPG_PLLxCR0_NI8		GENMASK(27, 20)	/* Integer mult. factor */
 57#define CPG_PLLxCR1_NF25	GENMASK(24, 0)	/* Fractional mult. factor */
 58
 59/* Fractional 9.24 PLL */
 60#define CPG_PLLxCR0_NI9		GENMASK(28, 20)	/* Integer mult. factor */
 61#define CPG_PLLxCR1_NF24	GENMASK(23, 0)	/* Fractional mult. factor */
 62
 63#define CPG_PLLxCR_STC		GENMASK(30, 24)	/* R_Car V3U PLLxCR */
 64
 65#define CPG_RPCCKCR		0x874	/* RPC Clock Freq. Control Register */
 66
 67#define CPG_SD0CKCR1		0x8a4	/* SD-IF0 Clock Freq. Control Reg. 1 */
 68
 69#define CPG_SD0CKCR1_SDSRC_SEL	GENMASK(30, 29)	/* SDSRC clock freq. select */
 70
 71/* PLL Clocks */
 72struct cpg_pll_clk {
 73	struct clk_hw hw;
 74	void __iomem *pllcr0_reg;
 75	void __iomem *pllcr1_reg;
 76	void __iomem *pllecr_reg;
 77	u32 pllecr_pllst_mask;
 78};
 79
 80#define to_pll_clk(_hw)   container_of(_hw, struct cpg_pll_clk, hw)
 81
 82static unsigned long cpg_pll_8_25_clk_recalc_rate(struct clk_hw *hw,
 83						  unsigned long parent_rate)
 84{
 85	struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
 86	u32 cr0 = readl(pll_clk->pllcr0_reg);
 87	unsigned int ni, nf;
 88	unsigned long rate;
 89
 90	ni = (FIELD_GET(CPG_PLLxCR0_NI8, cr0) + 1) * 2;
 91	rate = parent_rate * ni;
 92	if (cr0 & CPG_PLLxCR0_SSMODE_FM) {
 93		nf = FIELD_GET(CPG_PLLxCR1_NF25, readl(pll_clk->pllcr1_reg));
 94		rate += mul_u64_u32_shr(parent_rate, nf, 24);
 95	}
 96
 97	return rate;
 98}
 99
100static int cpg_pll_8_25_clk_determine_rate(struct clk_hw *hw,
101					   struct clk_rate_request *req)
102{
103	struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
104	unsigned int min_mult, max_mult, ni, nf;
105	u32 cr0 = readl(pll_clk->pllcr0_reg);
106	unsigned long prate;
107
108	prate = req->best_parent_rate * 2;
109	min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
110	max_mult = min(div64_ul(req->max_rate, prate), 256ULL);
111	if (max_mult < min_mult)
112		return -EINVAL;
113
114	if (cr0 & CPG_PLLxCR0_SSMODE_FM) {
115		ni = div64_ul(req->rate, prate);
116		if (ni < min_mult) {
117			ni = min_mult;
118			nf = 0;
119		} else {
120			ni = min(ni, max_mult);
121			nf = div64_ul((u64)(req->rate - prate * ni) << 24,
122				      req->best_parent_rate);
123		}
124	} else {
125		ni = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
126		ni = clamp(ni, min_mult, max_mult);
127		nf = 0;
128	}
129	req->rate = prate * ni + mul_u64_u32_shr(req->best_parent_rate, nf, 24);
130
131	return 0;
132}
133
134static int cpg_pll_8_25_clk_set_rate(struct clk_hw *hw, unsigned long rate,
135				     unsigned long parent_rate)
136{
137	struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
138	unsigned long prate = parent_rate * 2;
139	u32 cr0 = readl(pll_clk->pllcr0_reg);
140	unsigned int ni, nf;
141	u32 val;
142
143	if (cr0 & CPG_PLLxCR0_SSMODE_FM) {
144		ni = div64_ul(rate, prate);
145		if (ni < 1) {
146			ni = 1;
147			nf = 0;
148		} else {
149			ni = min(ni, 256U);
150			nf = div64_ul((u64)(rate - prate * ni) << 24,
151				      parent_rate);
152		}
153	} else {
154		ni = DIV_ROUND_CLOSEST_ULL(rate, prate);
155		ni = clamp(ni, 1U, 256U);
156	}
157
158	if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK)
159		return -EBUSY;
160
161	cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI8,
162		       FIELD_PREP(CPG_PLLxCR0_NI8, ni - 1));
163	if (cr0 & CPG_PLLxCR0_SSMODE_FM)
164		cpg_reg_modify(pll_clk->pllcr1_reg, CPG_PLLxCR1_NF25,
165			       FIELD_PREP(CPG_PLLxCR1_NF25, nf));
166
167	/*
168	 * Set KICK bit in PLLxCR0 to update hardware setting and wait for
169	 * clock change completion.
170	 */
171	cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK);
172
173	/*
174	 * Note: There is no HW information about the worst case latency.
175	 *
176	 * Using experimental measurements, it seems that no more than
177	 * ~45 µs are needed, independently of the CPU rate.
178	 * Since this value might be dependent on external xtal rate, pll
179	 * rate or even the other emulation clocks rate, use 1000 as a
180	 * "super" safe value.
181	 */
182	return readl_poll_timeout(pll_clk->pllecr_reg, val,
183				  val & pll_clk->pllecr_pllst_mask, 0, 1000);
184}
185
186static const struct clk_ops cpg_pll_f8_25_clk_ops = {
187	.recalc_rate = cpg_pll_8_25_clk_recalc_rate,
188};
189
190static const struct clk_ops cpg_pll_v8_25_clk_ops = {
191	.recalc_rate = cpg_pll_8_25_clk_recalc_rate,
192	.determine_rate = cpg_pll_8_25_clk_determine_rate,
193	.set_rate = cpg_pll_8_25_clk_set_rate,
194};
195
196static unsigned long cpg_pll_9_24_clk_recalc_rate(struct clk_hw *hw,
197						  unsigned long parent_rate)
198{
199	struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
200	u32 cr0 = readl(pll_clk->pllcr0_reg);
201	unsigned int ni, nf;
202	unsigned long rate;
203
204	ni = FIELD_GET(CPG_PLLxCR0_NI9, cr0) + 1;
205	rate = parent_rate * ni;
206	if (cr0 & CPG_PLLxCR0_SSMODE_FM) {
207		nf = FIELD_GET(CPG_PLLxCR1_NF24, readl(pll_clk->pllcr1_reg));
208		rate += mul_u64_u32_shr(parent_rate, nf, 24);
209	} else {
210		rate *= 2;
211	}
212
213	return rate;
214}
215
216static const struct clk_ops cpg_pll_f9_24_clk_ops = {
217	.recalc_rate = cpg_pll_9_24_clk_recalc_rate,
218};
219
220static struct clk * __init cpg_pll_clk_register(const char *name,
221						const char *parent_name,
222						void __iomem *base,
223						unsigned int index,
224						const struct clk_ops *ops)
225{
226	static const struct { u16 cr0, cr1; } pll_cr_offsets[] __initconst = {
227		[1 - 1] = { CPG_PLL1CR0, CPG_PLL1CR1 },
228		[2 - 1] = { CPG_PLL2CR0, CPG_PLL2CR1 },
229		[3 - 1] = { CPG_PLL3CR0, CPG_PLL3CR1 },
230		[4 - 1] = { CPG_PLL4CR0, CPG_PLL4CR1 },
231		[6 - 1] = { CPG_PLL6CR0, CPG_PLL6CR1 },
232	};
233	struct clk_init_data init = {};
234	struct cpg_pll_clk *pll_clk;
235	struct clk *clk;
236
237	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
238	if (!pll_clk)
239		return ERR_PTR(-ENOMEM);
240
241	init.name = name;
242	init.ops = ops;
243	init.parent_names = &parent_name;
244	init.num_parents = 1;
245
246	pll_clk->hw.init = &init;
247	pll_clk->pllcr0_reg = base + pll_cr_offsets[index - 1].cr0;
248	pll_clk->pllcr1_reg = base + pll_cr_offsets[index - 1].cr1;
249	pll_clk->pllecr_reg = base + CPG_PLLECR;
250	pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
251
252	clk = clk_register(NULL, &pll_clk->hw);
253	if (IS_ERR(clk))
254		kfree(pll_clk);
255
256	return clk;
257}
258
259/*
260 * Z0, Z1 and ZG Clock
261 */
262#define CPG_FRQCRB			0x00000804
263#define CPG_FRQCRB_KICK			BIT(31)
264#define CPG_FRQCRC0			0x00000808
265#define CPG_FRQCRC1			0x000008e0
266
267struct cpg_z_clk {
268	struct clk_hw hw;
269	void __iomem *reg;
270	void __iomem *kick_reg;
271	unsigned long max_rate;		/* Maximum rate for normal mode */
272	unsigned int fixed_div;
273	u32 mask;
274};
275
276#define to_z_clk(_hw)	container_of(_hw, struct cpg_z_clk, hw)
277
278static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
279					   unsigned long parent_rate)
280{
281	struct cpg_z_clk *zclk = to_z_clk(hw);
282	unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));
283
284	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
285				     32 * zclk->fixed_div);
286}
287
288static int cpg_z_clk_determine_rate(struct clk_hw *hw,
289				    struct clk_rate_request *req)
290{
291	struct cpg_z_clk *zclk = to_z_clk(hw);
292	unsigned int min_mult, max_mult, mult;
293	unsigned long rate, prate;
294
295	rate = min(req->rate, req->max_rate);
296	if (rate <= zclk->max_rate) {
297		/* Set parent rate to initial value for normal modes */
298		prate = zclk->max_rate;
299	} else {
300		/* Set increased parent rate for boost modes */
301		prate = rate;
302	}
303	req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
304						  prate * zclk->fixed_div);
305
306	prate = req->best_parent_rate / zclk->fixed_div;
307	min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
308	max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
309	if (max_mult < min_mult)
310		return -EINVAL;
311
312	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
313	mult = clamp(mult, min_mult, max_mult);
314
315	req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
316	return 0;
317}
318
319static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
320			      unsigned long parent_rate)
321{
322	struct cpg_z_clk *zclk = to_z_clk(hw);
323	unsigned int mult;
324	unsigned int i;
325
326	mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
327				       parent_rate);
328	mult = clamp(mult, 1U, 32U);
329
330	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
331		return -EBUSY;
332
333	cpg_reg_modify(zclk->reg, zclk->mask,
334		       field_prep(zclk->mask, 32 - mult));
335
336	/*
337	 * Set KICK bit in FRQCRB to update hardware setting and wait for
338	 * clock change completion.
339	 */
340	cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
341
342	/*
343	 * Note: There is no HW information about the worst case latency.
344	 *
345	 * Using experimental measurements, it seems that no more than
346	 * ~10 iterations are needed, independently of the CPU rate.
347	 * Since this value might be dependent on external xtal rate, pll1
348	 * rate or even the other emulation clocks rate, use 1000 as a
349	 * "super" safe value.
350	 */
351	for (i = 1000; i; i--) {
352		if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
353			return 0;
354
355		cpu_relax();
356	}
357
358	return -ETIMEDOUT;
359}
360
361static const struct clk_ops cpg_z_clk_ops = {
362	.recalc_rate = cpg_z_clk_recalc_rate,
363	.determine_rate = cpg_z_clk_determine_rate,
364	.set_rate = cpg_z_clk_set_rate,
365};
366
367static struct clk * __init cpg_z_clk_register(const char *name,
368					      const char *parent_name,
369					      void __iomem *reg,
370					      unsigned int div,
371					      unsigned int offset)
372{
373	struct clk_init_data init = {};
374	struct cpg_z_clk *zclk;
375	struct clk *clk;
376
377	zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
378	if (!zclk)
379		return ERR_PTR(-ENOMEM);
380
381	init.name = name;
382	init.ops = &cpg_z_clk_ops;
383	init.flags = CLK_SET_RATE_PARENT;
384	init.parent_names = &parent_name;
385	init.num_parents = 1;
386
387	if (offset < 32) {
388		zclk->reg = reg + CPG_FRQCRC0;
389	} else if (offset < 64) {
390		zclk->reg = reg + CPG_FRQCRC1;
391		offset -= 32;
392	} else if (offset < 96) {
393		zclk->reg = reg + CPG_FRQCRB;
394		offset -= 64;
395	} else {
396		return ERR_PTR(-EINVAL);
397	}
398	zclk->kick_reg = reg + CPG_FRQCRB;
399	zclk->hw.init = &init;
400	zclk->mask = GENMASK(offset + 4, offset);
401	zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
402
403	clk = clk_register(NULL, &zclk->hw);
404	if (IS_ERR(clk)) {
405		kfree(zclk);
406		return clk;
407	}
408
409	zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
410			 zclk->fixed_div;
411	return clk;
412}
413
414/*
415 * RPC Clocks
416 */
417static const struct clk_div_table cpg_rpcsrc_div_table[] = {
418	{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
419};
420
421struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
422	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
423	struct cpg_mssr_pub *pub)
424{
425	struct raw_notifier_head *notifiers = &pub->notifiers;
426	void __iomem *base = pub->base0;
427	struct clk **clks = pub->clks;
428	const struct clk *parent;
429	unsigned int mult = 1;
430	unsigned int div = 1;
431	u32 value;
432
433	parent = clks[core->parent & 0xffff];	/* some types use high bits */
434	if (IS_ERR(parent))
435		return ERR_CAST(parent);
436
437	switch (core->type) {
438	case CLK_TYPE_GEN4_MAIN:
439		div = cpg_pll_config->extal_div;
440		break;
441
442	case CLK_TYPE_GEN4_PLL1:
443		mult = cpg_pll_config->pll1_mult;
444		div = cpg_pll_config->pll1_div;
445		break;
446
447	case CLK_TYPE_GEN4_PLL5:
448		mult = cpg_pll_config->pll5_mult;
449		div = cpg_pll_config->pll5_div;
450		break;
451
452	case CLK_TYPE_GEN4_PLL2X_3X:
453		value = readl(base + core->offset);
454		mult = (FIELD_GET(CPG_PLLxCR_STC, value) + 1) * 2;
455		break;
456
457	case CLK_TYPE_GEN4_PLL_F8_25:
458		return cpg_pll_clk_register(core->name, __clk_get_name(parent),
459					    base, core->offset,
460					    &cpg_pll_f8_25_clk_ops);
461
462	case CLK_TYPE_GEN4_PLL_V8_25:
463		return cpg_pll_clk_register(core->name, __clk_get_name(parent),
464					    base, core->offset,
465					    &cpg_pll_v8_25_clk_ops);
466
467	case CLK_TYPE_GEN4_PLL_V9_24:
468		/* Variable fractional 9.24 is not yet supported, using fixed */
469		fallthrough;
470	case CLK_TYPE_GEN4_PLL_F9_24:
471		return cpg_pll_clk_register(core->name, __clk_get_name(parent),
472					    base, core->offset,
473					    &cpg_pll_f9_24_clk_ops);
474
475	case CLK_TYPE_GEN4_Z:
476		return cpg_z_clk_register(core->name, __clk_get_name(parent),
477					  base, core->div, core->offset);
478
479	case CLK_TYPE_GEN4_SDSRC:
480		value = readl(base + CPG_SD0CKCR1);
481		div = FIELD_GET(CPG_SD0CKCR1_SDSRC_SEL, value) + 4;
482		break;
483
484	case CLK_TYPE_GEN4_SDH:
485		return cpg_sdh_clk_register(core->name, base + core->offset,
486					   __clk_get_name(parent), notifiers);
487
488	case CLK_TYPE_GEN4_SD:
489		return cpg_sd_clk_register(core->name, base + core->offset,
490					   __clk_get_name(parent));
491
492	case CLK_TYPE_GEN4_MDSEL:
493		/*
494		 * Clock selectable between two parents and two fixed dividers
495		 * using a mode pin
496		 */
497		if (cpg_mode & BIT(core->offset)) {
498			div = core->div & 0xffff;
499		} else {
500			parent = clks[core->parent >> 16];
501			if (IS_ERR(parent))
502				return ERR_CAST(parent);
503			div = core->div >> 16;
504		}
505		mult = 1;
506		break;
507
508	case CLK_TYPE_GEN4_OSC:
509		/*
510		 * Clock combining OSC EXTAL predivider and a fixed divider
511		 */
512		div = cpg_pll_config->osc_prediv * core->div;
513		break;
514
515	case CLK_TYPE_GEN4_RPCSRC:
516		return clk_register_divider_table(NULL, core->name,
517						  __clk_get_name(parent), 0,
518						  base + CPG_RPCCKCR, 3, 2, 0,
519						  cpg_rpcsrc_div_table,
520						  &cpg_lock);
521
522	case CLK_TYPE_GEN4_RPC:
523		return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
524					    __clk_get_name(parent), notifiers);
525
526	case CLK_TYPE_GEN4_RPCD2:
527		return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
528					      __clk_get_name(parent));
529
530	default:
531		return ERR_PTR(-EINVAL);
532	}
533
534	return clk_register_fixed_factor(NULL, core->name,
535					 __clk_get_name(parent), 0, mult, div);
536}
537
538int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
539			      unsigned int clk_extalr, u32 mode)
540{
541	cpg_pll_config = config;
542	cpg_clk_extalr = clk_extalr;
543	cpg_mode = mode;
544
545	return 0;
546}