r9a09g057-cpg.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Renesas RZ/V2H(P) CPG driver
  4 *
  5 * Copyright (C) 2024 Renesas Electronics Corp.
  6 */
  7
  8#include <linux/clk-provider.h>
  9#include <linux/clk/renesas.h>
 10#include <linux/device.h>
 11#include <linux/init.h>
 12#include <linux/kernel.h>
 13
 14#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
 15
 16#include "rzv2h-cpg.h"
 17
 18enum clk_ids {
 19	/* Core Clock Outputs exported to DT */
 20	LAST_DT_CORE_CLK = R9A09G057_USB3_1_CLKCORE,
 21
 22	/* External Input Clocks */
 23	CLK_AUDIO_EXTAL,
 24	CLK_RTXIN,
 25	CLK_QEXTAL,
 26
 27	/* PLL Clocks */
 28	CLK_PLLCM33,
 29	CLK_PLLCLN,
 30	CLK_PLLDTY,
 31	CLK_PLLCA55,
 32	CLK_PLLVDO,
 33	CLK_PLLETH,
 34	CLK_PLLDSI,
 35	CLK_PLLGPU,
 36
 37	/* Internal Core Clocks */
 38	CLK_PLLCM33_DIV3,
 39	CLK_PLLCM33_DIV4,
 40	CLK_PLLCM33_DIV5,
 41	CLK_PLLCM33_DIV16,
 42	CLK_PLLCM33_GEAR,
 43	CLK_SMUX2_XSPI_CLK0,
 44	CLK_SMUX2_XSPI_CLK1,
 45	CLK_PLLCM33_XSPI,
 46	CLK_PLLCLN_DIV2,
 47	CLK_PLLCLN_DIV8,
 48	CLK_PLLCLN_DIV16,
 49	CLK_PLLDTY_ACPU,
 50	CLK_PLLDTY_ACPU_DIV2,
 51	CLK_PLLDTY_ACPU_DIV4,
 52	CLK_PLLDTY_DIV8,
 53	CLK_PLLDTY_DIV16,
 54	CLK_PLLDTY_RCPU,
 55	CLK_PLLDTY_RCPU_DIV4,
 56	CLK_PLLVDO_CRU0,
 57	CLK_PLLVDO_CRU1,
 58	CLK_PLLVDO_CRU2,
 59	CLK_PLLVDO_CRU3,
 60	CLK_PLLVDO_ISP,
 61	CLK_PLLETH_DIV_250_FIX,
 62	CLK_PLLETH_DIV_125_FIX,
 63	CLK_CSDIV_PLLETH_GBE0,
 64	CLK_CSDIV_PLLETH_GBE1,
 65	CLK_SMUX2_GBE0_TXCLK,
 66	CLK_SMUX2_GBE0_RXCLK,
 67	CLK_SMUX2_GBE1_TXCLK,
 68	CLK_SMUX2_GBE1_RXCLK,
 69	CLK_CDIV4_PLLETH_LPCLK,
 70	CLK_PLLETH_LPCLK_GEAR,
 71	CLK_PLLDSI_GEAR,
 72	CLK_PLLGPU_GEAR,
 73
 74	/* Module Clocks */
 75	MOD_CLK_BASE,
 76};
 77
 78static const struct clk_div_table dtable_1_8[] = {
 79	{0, 1},
 80	{1, 2},
 81	{2, 4},
 82	{3, 8},
 83	{0, 0},
 84};
 85
 86static const struct clk_div_table dtable_2_4[] = {
 87	{0, 2},
 88	{1, 4},
 89	{0, 0},
 90};
 91
 92static const struct clk_div_table dtable_2_16[] = {
 93	{0, 2},
 94	{1, 4},
 95	{2, 8},
 96	{3, 16},
 97	{0, 0},
 98};
 99
100static const struct clk_div_table dtable_2_32[] = {
101	{0, 2},
102	{1, 4},
103	{2, 6},
104	{3, 8},
105	{4, 10},
106	{5, 12},
107	{6, 14},
108	{7, 16},
109	{8, 18},
110	{9, 20},
111	{10, 22},
112	{11, 24},
113	{12, 26},
114	{13, 28},
115	{14, 30},
116	{15, 32},
117	{0, 0},
118};
119
120static const struct clk_div_table dtable_2_64[] = {
121	{0, 2},
122	{1, 4},
123	{2, 8},
124	{3, 16},
125	{4, 64},
126	{0, 0},
127};
128
129static const struct clk_div_table dtable_2_100[] = {
130	{0, 2},
131	{1, 10},
132	{2, 100},
133	{0, 0},
134};
135
136static const struct clk_div_table dtable_16_128[] = {
137	{0, 16},
138	{1, 32},
139	{2, 64},
140	{3, 128},
141	{0, 0},
142};
143
144RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits);
145#define PLLDSI		PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2h_cpg_pll_dsi_limits)
146
147/* Mux clock tables */
148static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
149static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
150static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
151static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
152static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
153static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
154
155static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
156	/* External Clock Inputs */
157	DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
158	DEF_INPUT("rtxin", CLK_RTXIN),
159	DEF_INPUT("qextal", CLK_QEXTAL),
160
161	/* PLL Clocks */
162	DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
163	DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
164	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
165	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
166	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
167	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
168	DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
169	DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
170
171	/* Internal Core Clocks */
172	DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
173	DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
174	DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
175	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
176	DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
177	DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
178	DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
179	DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
180		  dtable_2_16),
181
182	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
183	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
184	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
185
186	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
187	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
188	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
189	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
190	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
191	DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
192	DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
193
194	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
195	DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
196	DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
197	DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
198	DEF_DDIV(".pllvdo_isp",  CLK_PLLVDO_ISP,  CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
199
200	DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
201	DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
202	DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
203		  CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
204	DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
205		  CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
206	DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
207	DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
208	DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
209	DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
210	DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),
211	DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,
212		  CSDIV0_DIVCTL2, dtable_16_128),
213
214	DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,
215		       CSDIV1_DIVCTL2, dtable_2_32),
216
217	DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
218
219	/* Core Clocks */
220	DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
221	DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55,
222		 CDDIV1_DIVCTL0, dtable_1_8),
223	DEF_DDIV("ca55_0_coreclk1", R9A09G057_CA55_0_CORE_CLK1, CLK_PLLCA55,
224		 CDDIV1_DIVCTL1, dtable_1_8),
225	DEF_DDIV("ca55_0_coreclk2", R9A09G057_CA55_0_CORE_CLK2, CLK_PLLCA55,
226		 CDDIV1_DIVCTL2, dtable_1_8),
227	DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55,
228		 CDDIV1_DIVCTL3, dtable_1_8),
229	DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
230	DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
231	DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
232	DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I,
233		  CLK_PLLETH_DIV_125_FIX, 1, 1),
234	DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I,
235		  CLK_PLLETH_DIV_125_FIX, 1, 1),
236	DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
237			     FIXED_MOD_CONF_XSPI),
238	DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G057_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
239	DEF_FIXED("usb3_0_core_clk", R9A09G057_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
240	DEF_FIXED("usb3_1_ref_alt_clk_p", R9A09G057_USB3_1_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
241	DEF_FIXED("usb3_1_core_clk", R9A09G057_USB3_1_CLKCORE, CLK_QEXTAL, 1, 1),
242};
243
244static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
245	DEF_MOD("dmac_0_aclk",			CLK_PLLCM33_GEAR, 0, 0, 0, 0,
246						BUS_MSTOP(5, BIT(9))),
247	DEF_MOD("dmac_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
248						BUS_MSTOP(3, BIT(2))),
249	DEF_MOD("dmac_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
250						BUS_MSTOP(3, BIT(3))),
251	DEF_MOD("dmac_3_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
252						BUS_MSTOP(10, BIT(11))),
253	DEF_MOD("dmac_4_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
254						BUS_MSTOP(10, BIT(12))),
255	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,
256						BUS_MSTOP_NONE),
257	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
258						BUS_MSTOP(3, BIT(5))),
259	DEF_MOD("gtm_0_pclk",			CLK_PLLCM33_DIV16, 4, 3, 2, 3,
260						BUS_MSTOP(5, BIT(10))),
261	DEF_MOD("gtm_1_pclk",			CLK_PLLCM33_DIV16, 4, 4, 2, 4,
262						BUS_MSTOP(5, BIT(11))),
263	DEF_MOD("gtm_2_pclk",			CLK_PLLCLN_DIV16, 4, 5, 2, 5,
264						BUS_MSTOP(2, BIT(13))),
265	DEF_MOD("gtm_3_pclk",			CLK_PLLCLN_DIV16, 4, 6, 2, 6,
266						BUS_MSTOP(2, BIT(14))),
267	DEF_MOD("gtm_4_pclk",			CLK_PLLCLN_DIV16, 4, 7, 2, 7,
268						BUS_MSTOP(11, BIT(13))),
269	DEF_MOD("gtm_5_pclk",			CLK_PLLCLN_DIV16, 4, 8, 2, 8,
270						BUS_MSTOP(11, BIT(14))),
271	DEF_MOD("gtm_6_pclk",			CLK_PLLCLN_DIV16, 4, 9, 2, 9,
272						BUS_MSTOP(11, BIT(15))),
273	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10,
274						BUS_MSTOP(12, BIT(0))),
275	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11,
276						BUS_MSTOP(3, BIT(10))),
277	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12,
278						BUS_MSTOP(3, BIT(10))),
279	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
280						BUS_MSTOP(1, BIT(0))),
281	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,
282						BUS_MSTOP(1, BIT(0))),
283	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15,
284						BUS_MSTOP(5, BIT(12))),
285	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16,
286						BUS_MSTOP(5, BIT(12))),
287	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,
288						BUS_MSTOP(5, BIT(13))),
289	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,
290						BUS_MSTOP(5, BIT(13))),
291	DEF_MOD("rtc_0_clk_rtc",		CLK_PLLCM33_DIV16, 5, 3, 2, 19,
292						BUS_MSTOP(3, BIT(11) | BIT(12))),
293	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,
294						BUS_MSTOP(11, BIT(0))),
295	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,
296						BUS_MSTOP(11, BIT(0))),
297	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,
298						BUS_MSTOP(11, BIT(0))),
299	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,
300						BUS_MSTOP(11, BIT(1))),
301	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,
302						BUS_MSTOP(11, BIT(1))),
303	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,
304						BUS_MSTOP(11, BIT(1))),
305	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,
306						BUS_MSTOP(11, BIT(2))),
307	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,
308						BUS_MSTOP(11, BIT(2))),
309	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,
310						BUS_MSTOP(11, BIT(2))),
311	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,
312						BUS_MSTOP(3, BIT(14))),
313	DEF_MOD("i3c_0_pclkrw",			CLK_PLLCLN_DIV16, 9, 0, 4, 16,
314						BUS_MSTOP(10, BIT(15))),
315	DEF_MOD("i3c_0_pclk",			CLK_PLLCLN_DIV16, 9, 1, 4, 17,
316						BUS_MSTOP(10, BIT(15))),
317	DEF_MOD("i3c_0_tclk",			CLK_PLLCLN_DIV8, 9, 2, 4, 18,
318						BUS_MSTOP(10, BIT(15))),
319	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19,
320						BUS_MSTOP(3, BIT(13))),
321	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20,
322						BUS_MSTOP(1, BIT(1))),
323	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21,
324						BUS_MSTOP(1, BIT(2))),
325	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22,
326						BUS_MSTOP(1, BIT(3))),
327	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23,
328						BUS_MSTOP(1, BIT(4))),
329	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24,
330						BUS_MSTOP(1, BIT(5))),
331	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25,
332						BUS_MSTOP(1, BIT(6))),
333	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26,
334						BUS_MSTOP(1, BIT(7))),
335	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27,
336						BUS_MSTOP(1, BIT(8))),
337	DEF_MOD("spi_hclk",			CLK_PLLCM33_GEAR, 9, 15, 4, 31,
338						BUS_MSTOP(4, BIT(5))),
339	DEF_MOD("spi_aclk",			CLK_PLLCM33_GEAR, 10, 0, 5, 0,
340						BUS_MSTOP(4, BIT(5))),
341	DEF_MOD("spi_clk_spix2",		CLK_PLLCM33_XSPI, 10, 1, 5, 2,
342						BUS_MSTOP(4, BIT(5))),
343	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3,
344						BUS_MSTOP(8, BIT(2))),
345	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4,
346						BUS_MSTOP(8, BIT(2))),
347	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5,
348						BUS_MSTOP(8, BIT(2))),
349	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
350						BUS_MSTOP(8, BIT(2))),
351	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7,
352						BUS_MSTOP(8, BIT(3))),
353	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8,
354						BUS_MSTOP(8, BIT(3))),
355	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,
356						BUS_MSTOP(8, BIT(3))),
357	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
358						BUS_MSTOP(8, BIT(3))),
359	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11,
360						BUS_MSTOP(8, BIT(4))),
361	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12,
362						BUS_MSTOP(8, BIT(4))),
363	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13,
364						BUS_MSTOP(8, BIT(4))),
365	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
366						BUS_MSTOP(8, BIT(4))),
367	DEF_MOD("usb3_0_aclk",			CLK_PLLDTY_DIV8, 10, 15, 5, 15,
368						BUS_MSTOP(7, BIT(12))),
369	DEF_MOD("usb3_0_pclk_usbtst",		CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
370						BUS_MSTOP(7, BIT(14))),
371	DEF_MOD("usb3_1_aclk",			CLK_PLLDTY_DIV8, 11, 1, 5, 17,
372						BUS_MSTOP(7, BIT(13))),
373	DEF_MOD("usb3_1_pclk_usbtst",		CLK_PLLDTY_ACPU_DIV4, 11, 2, 5, 18,
374						BUS_MSTOP(7, BIT(15))),
375	DEF_MOD("usb2_0_u2h0_hclk",		CLK_PLLDTY_DIV8, 11, 3, 5, 19,
376						BUS_MSTOP(7, BIT(7))),
377	DEF_MOD("usb2_0_u2h1_hclk",		CLK_PLLDTY_DIV8, 11, 4, 5, 20,
378						BUS_MSTOP(7, BIT(8))),
379	DEF_MOD("usb2_0_u2p_exr_cpuclk",	CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
380						BUS_MSTOP(7, BIT(9))),
381	DEF_MOD("usb2_0_pclk_usbtst0",		CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
382						BUS_MSTOP(7, BIT(10))),
383	DEF_MOD("usb2_0_pclk_usbtst1",		CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
384						BUS_MSTOP(7, BIT(11))),
385	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
386						BUS_MSTOP(8, BIT(5)), 1),
387	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
388						BUS_MSTOP(8, BIT(5)), 1),
389	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
390						BUS_MSTOP(8, BIT(5)), 1),
391	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
392						BUS_MSTOP(8, BIT(5)), 1),
393	DEF_MOD("gbeth_0_aclk_csr_i",		CLK_PLLDTY_DIV8, 11, 12, 5, 28,
394						BUS_MSTOP(8, BIT(5))),
395	DEF_MOD("gbeth_0_aclk_i",		CLK_PLLDTY_DIV8, 11, 13, 5, 29,
396						BUS_MSTOP(8, BIT(5))),
397	DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
398						BUS_MSTOP(8, BIT(6)), 1),
399	DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
400						BUS_MSTOP(8, BIT(6)), 1),
401	DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
402						BUS_MSTOP(8, BIT(6)), 1),
403	DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
404						BUS_MSTOP(8, BIT(6)), 1),
405	DEF_MOD("gbeth_1_aclk_csr_i",		CLK_PLLDTY_DIV8, 12, 2, 6, 2,
406						BUS_MSTOP(8, BIT(6))),
407	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,
408						BUS_MSTOP(8, BIT(6))),
409	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
410						BUS_MSTOP(9, BIT(4))),
411	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,
412						BUS_MSTOP(9, BIT(4))),
413	DEF_MOD("cru_0_pclk",			CLK_PLLDTY_DIV16, 13, 4, 6, 20,
414						BUS_MSTOP(9, BIT(4))),
415	DEF_MOD("cru_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
416						BUS_MSTOP(9, BIT(5))),
417	DEF_MOD_NO_PM("cru_1_vclk",		CLK_PLLVDO_CRU1, 13, 6, 6, 22,
418						BUS_MSTOP(9, BIT(5))),
419	DEF_MOD("cru_1_pclk",			CLK_PLLDTY_DIV16, 13, 7, 6, 23,
420						BUS_MSTOP(9, BIT(5))),
421	DEF_MOD("cru_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
422						BUS_MSTOP(9, BIT(6))),
423	DEF_MOD_NO_PM("cru_2_vclk",		CLK_PLLVDO_CRU2, 13, 9, 6, 25,
424						BUS_MSTOP(9, BIT(6))),
425	DEF_MOD("cru_2_pclk",			CLK_PLLDTY_DIV16, 13, 10, 6, 26,
426						BUS_MSTOP(9, BIT(6))),
427	DEF_MOD("cru_3_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
428						BUS_MSTOP(9, BIT(7))),
429	DEF_MOD_NO_PM("cru_3_vclk",		CLK_PLLVDO_CRU3, 13, 12, 6, 28,
430						BUS_MSTOP(9, BIT(7))),
431	DEF_MOD("cru_3_pclk",			CLK_PLLDTY_DIV16, 13, 13, 6, 29,
432						BUS_MSTOP(9, BIT(7))),
433	DEF_MOD("isp_0_reg_aclk",		CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
434						BUS_MSTOP(9, BIT(8))),
435	DEF_MOD("isp_0_pclk",			CLK_PLLDTY_DIV16, 14, 3, 7, 3,
436						BUS_MSTOP(9, BIT(8))),
437	DEF_MOD("isp_0_vin_aclk",		CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
438						BUS_MSTOP(9, BIT(9))),
439	DEF_MOD("isp_0_isp_sclk",		CLK_PLLVDO_ISP, 14, 5, 7, 5,
440						BUS_MSTOP(9, BIT(9))),
441	DEF_MOD("dsi_0_pclk",			CLK_PLLDTY_DIV16, 14, 8, 7, 8,
442						BUS_MSTOP(9, BIT(14) | BIT(15))),
443	DEF_MOD("dsi_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
444						BUS_MSTOP(9, BIT(14) | BIT(15))),
445	DEF_MOD("dsi_0_vclk1",			CLK_PLLDSI_GEAR, 14, 10, 7, 10,
446						BUS_MSTOP(9, BIT(14) | BIT(15))),
447	DEF_MOD("dsi_0_lpclk",			CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,
448						BUS_MSTOP(9, BIT(14) | BIT(15))),
449	DEF_MOD("dsi_0_pllref_clk",		CLK_QEXTAL, 14, 12, 7, 12,
450						BUS_MSTOP(9, BIT(14) | BIT(15))),
451	DEF_MOD("lcdc_0_clk_a",			CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
452						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
453	DEF_MOD("lcdc_0_clk_p",			CLK_PLLDTY_DIV16, 14, 14, 7, 14,
454						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
455	DEF_MOD("lcdc_0_clk_d",			CLK_PLLDSI_GEAR, 14, 15, 7, 15,
456						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
457	DEF_MOD("gpu_0_clk",			CLK_PLLGPU_GEAR, 15, 0, 7, 16,
458						BUS_MSTOP(3, BIT(4))),
459	DEF_MOD("gpu_0_axi_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
460						BUS_MSTOP(3, BIT(4))),
461	DEF_MOD("gpu_0_ace_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
462						BUS_MSTOP(3, BIT(4))),
463	DEF_MOD("tsu_0_pclk",			CLK_QEXTAL, 16, 9, 8, 9,
464						BUS_MSTOP(5, BIT(2))),
465	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
466						BUS_MSTOP(2, BIT(15))),
467};
468
469static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
470	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
471	DEF_RST(3, 1, 1, 2),		/* DMAC_0_ARESETN */
472	DEF_RST(3, 2, 1, 3),		/* DMAC_1_ARESETN */
473	DEF_RST(3, 3, 1, 4),		/* DMAC_2_ARESETN */
474	DEF_RST(3, 4, 1, 5),		/* DMAC_3_ARESETN */
475	DEF_RST(3, 5, 1, 6),		/* DMAC_4_ARESETN */
476	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */
477	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
478	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
479	DEF_RST(6, 13, 2, 30),		/* GTM_0_PRESETZ */
480	DEF_RST(6, 14, 2, 31),		/* GTM_1_PRESETZ */
481	DEF_RST(6, 15, 3, 0),		/* GTM_2_PRESETZ */
482	DEF_RST(7, 0, 3, 1),		/* GTM_3_PRESETZ */
483	DEF_RST(7, 1, 3, 2),		/* GTM_4_PRESETZ */
484	DEF_RST(7, 2, 3, 3),		/* GTM_5_PRESETZ */
485	DEF_RST(7, 3, 3, 4),		/* GTM_6_PRESETZ */
486	DEF_RST(7, 4, 3, 5),		/* GTM_7_PRESETZ */
487	DEF_RST(7, 5, 3, 6),		/* WDT_0_RESET */
488	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
489	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
490	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
491	DEF_RST(7, 9, 3, 10),		/* RTC_0_RST_RTC */
492	DEF_RST(7, 10, 3, 11),		/* RTC_0_RST_RTC_V */
493	DEF_RST(7, 11, 3, 12),		/* RSPI_0_PRESETN */
494	DEF_RST(7, 12, 3, 13),		/* RSPI_0_TRESETN */
495	DEF_RST(7, 13, 3, 14),		/* RSPI_1_PRESETN */
496	DEF_RST(7, 14, 3, 15),		/* RSPI_1_TRESETN */
497	DEF_RST(7, 15, 3, 16),		/* RSPI_2_PRESETN */
498	DEF_RST(8, 0, 3, 17),		/* RSPI_2_TRESETN */
499	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
500	DEF_RST(9, 6, 4, 7),		/* I3C_0_PRESETN */
501	DEF_RST(9, 7, 4, 8),		/* I3C_0_TRESETN */
502	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
503	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
504	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
505	DEF_RST(9, 11, 4, 12),		/* RIIC_3_MRST */
506	DEF_RST(9, 12, 4, 13),		/* RIIC_4_MRST */
507	DEF_RST(9, 13, 4, 14),		/* RIIC_5_MRST */
508	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */
509	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */
510	DEF_RST(10, 0, 4, 17),		/* RIIC_8_MRST */
511	DEF_RST(10, 3, 4, 20),		/* SPI_HRESETN */
512	DEF_RST(10, 4, 4, 21),		/* SPI_ARESETN */
513	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
514	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
515	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
516	DEF_RST(10, 10, 4, 27),		/* USB3_0_ARESETN */
517	DEF_RST(10, 11, 4, 28),		/* USB3_1_ARESETN */
518	DEF_RST(10, 12, 4, 29),		/* USB2_0_U2H0_HRESETN */
519	DEF_RST(10, 13, 4, 30),		/* USB2_0_U2H1_HRESETN */
520	DEF_RST(10, 14, 4, 31),		/* USB2_0_U2P_EXL_SYSRST */
521	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */
522	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */
523	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */
524	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */
525	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */
526	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */
527	DEF_RST(12, 8, 5, 25),		/* CRU_1_PRESETN */
528	DEF_RST(12, 9, 5, 26),		/* CRU_1_ARESETN */
529	DEF_RST(12, 10, 5, 27),		/* CRU_1_S_RESETN */
530	DEF_RST(12, 11, 5, 28),		/* CRU_2_PRESETN */
531	DEF_RST(12, 12, 5, 29),		/* CRU_2_ARESETN */
532	DEF_RST(12, 13, 5, 30),		/* CRU_2_S_RESETN */
533	DEF_RST(12, 14, 5, 31),		/* CRU_3_PRESETN */
534	DEF_RST(12, 15, 6, 0),		/* CRU_3_ARESETN */
535	DEF_RST(13, 0, 6, 1),		/* CRU_3_S_RESETN */
536	DEF_RST(13, 1, 6, 2),		/* ISP_0_VIN_ARESETN */
537	DEF_RST(13, 2, 6, 3),		/* ISP_0_REG_ARESETN */
538	DEF_RST(13, 3, 6, 4),		/* ISP_0_ISP_SRESETN */
539	DEF_RST(13, 4, 6, 5),		/* ISP_0_PRESETN */
540	DEF_RST(13, 7, 6, 8),		/* DSI_0_PRESETN */
541	DEF_RST(13, 8, 6, 9),		/* DSI_0_ARESETN */
542	DEF_RST(13, 12, 6, 13),		/* LCDC_0_RESET_N */
543	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */
544	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */
545	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */
546	DEF_RST(15, 7, 7, 8),		/* TSU_0_PRESETN */
547	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */
548};
549
550const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
551	/* Core Clocks */
552	.core_clks = r9a09g057_core_clks,
553	.num_core_clks = ARRAY_SIZE(r9a09g057_core_clks),
554	.last_dt_core_clk = LAST_DT_CORE_CLK,
555	.num_total_core_clks = MOD_CLK_BASE,
556
557	/* Module Clocks */
558	.mod_clks = r9a09g057_mod_clks,
559	.num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks),
560	.num_hw_mod_clks = 25 * 16,
561
562	/* Resets */
563	.resets = r9a09g057_resets,
564	.num_resets = ARRAY_SIZE(r9a09g057_resets),
565
566	.num_mstop_bits = 192,
567};