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r9a09g047-cpg.c
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linux-6.19.14/drivers/clk/renesas/r9a09g047-cpg.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Renesas RZ/G3E CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/device.h> 10#include <linux/init.h> 11#include <linux/kernel.h> 12 13#include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 14 15#include "rzv2h-cpg.h" 16 17enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G047_USB2_0_CLK_CORE1, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLVDO, 32 CLK_PLLETH, 33 34 /* Internal Core Clocks */ 35 CLK_PLLCM33_DIV3, 36 CLK_PLLCM33_DIV4, 37 CLK_PLLCM33_DIV5, 38 CLK_PLLCM33_DIV16, 39 CLK_PLLCM33_GEAR, 40 CLK_SMUX2_XSPI_CLK0, 41 CLK_SMUX2_XSPI_CLK1, 42 CLK_PLLCM33_XSPI, 43 CLK_PLLCLN_DIV2, 44 CLK_PLLCLN_DIV8, 45 CLK_PLLCLN_DIV16, 46 CLK_PLLCLN_DIV20, 47 CLK_PLLCLN_DIV64, 48 CLK_PLLCLN_DIV256, 49 CLK_PLLCLN_DIV1024, 50 CLK_PLLDTY_ACPU, 51 CLK_PLLDTY_ACPU_DIV2, 52 CLK_PLLDTY_ACPU_DIV4, 53 CLK_PLLDTY_DIV8, 54 CLK_PLLDTY_RCPU, 55 CLK_PLLDTY_RCPU_DIV4, 56 CLK_PLLETH_DIV_250_FIX, 57 CLK_PLLETH_DIV_125_FIX, 58 CLK_CSDIV_PLLETH_GBE0, 59 CLK_CSDIV_PLLETH_GBE1, 60 CLK_SMUX2_GBE0_TXCLK, 61 CLK_SMUX2_GBE0_RXCLK, 62 CLK_SMUX2_GBE1_TXCLK, 63 CLK_SMUX2_GBE1_RXCLK, 64 CLK_PLLDTY_DIV16, 65 CLK_PLLVDO_CRU0, 66 CLK_PLLVDO_GPU, 67 68 /* Module Clocks */ 69 MOD_CLK_BASE, 70}; 71 72static const struct clk_div_table dtable_1_8[] = { 73 {0, 1}, 74 {1, 2}, 75 {2, 4}, 76 {3, 8}, 77 {0, 0}, 78}; 79 80static const struct clk_div_table dtable_2_4[] = { 81 {0, 2}, 82 {1, 4}, 83 {0, 0}, 84}; 85 86static const struct clk_div_table dtable_2_16[] = { 87 {0, 2}, 88 {1, 4}, 89 {2, 8}, 90 {3, 16}, 91 {0, 0}, 92}; 93 94static const struct clk_div_table dtable_2_64[] = { 95 {0, 2}, 96 {1, 4}, 97 {2, 8}, 98 {3, 16}, 99 {4, 64}, 100 {0, 0}, 101}; 102 103static const struct clk_div_table dtable_2_100[] = { 104 {0, 2}, 105 {1, 10}, 106 {2, 100}, 107 {0, 0}, 108}; 109 110/* Mux clock tables */ 111static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" }; 112static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" }; 113static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" }; 114static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" }; 115static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" }; 116static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" }; 117 118static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 119 /* External Clock Inputs */ 120 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 121 DEF_INPUT("rtxin", CLK_RTXIN), 122 DEF_INPUT("qextal", CLK_QEXTAL), 123 124 /* PLL Clocks */ 125 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 126 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 127 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 128 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 129 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), 130 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 131 132 /* Internal Core Clocks */ 133 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3), 134 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), 135 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), 136 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 137 138 DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), 139 140 DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0), 141 DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1), 142 DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3, 143 dtable_2_16), 144 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 145 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 146 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 147 DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20), 148 DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64), 149 DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256), 150 DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024), 151 152 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 153 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 154 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 155 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), 156 157 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), 158 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2), 159 DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX, 160 CSDIV0_DIVCTL0, dtable_2_100), 161 DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX, 162 CSDIV0_DIVCTL1, dtable_2_100), 163 DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk), 164 DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), 165 DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), 166 DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), 167 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 168 DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64), 169 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4), 170 171 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 172 DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64), 173 174 /* Core Clocks */ 175 DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 176 DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55, 177 CDDIV1_DIVCTL0, dtable_1_8), 178 DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55, 179 CDDIV1_DIVCTL1, dtable_1_8), 180 DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55, 181 CDDIV1_DIVCTL2, dtable_1_8), 182 DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55, 183 CDDIV1_DIVCTL3, dtable_1_8), 184 DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 185 DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2), 186 DEF_FIXED("usb2_0_clk_core0", R9A09G047_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1), 187 DEF_FIXED("usb2_0_clk_core1", R9A09G047_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1), 188 DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I, 189 CLK_PLLETH_DIV_125_FIX, 1, 1), 190 DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I, 191 CLK_PLLETH_DIV_125_FIX, 1, 1), 192 DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1), 193 DEF_FIXED("usb3_0_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1), 194}; 195 196static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 197 DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0, 198 BUS_MSTOP(5, BIT(9))), 199 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1, 200 BUS_MSTOP(3, BIT(2))), 201 DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2, 202 BUS_MSTOP(3, BIT(3))), 203 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3, 204 BUS_MSTOP(10, BIT(11))), 205 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4, 206 BUS_MSTOP(10, BIT(12))), 207 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 208 BUS_MSTOP_NONE), 209 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 210 BUS_MSTOP(3, BIT(5))), 211 DEF_MOD("gpt_0_pclk_sfr", CLK_PLLCLN_DIV8, 3, 1, 1, 17, 212 BUS_MSTOP(6, BIT(11))), 213 DEF_MOD("gpt_1_pclk_sfr", CLK_PLLCLN_DIV8, 3, 2, 1, 18, 214 BUS_MSTOP(6, BIT(12))), 215 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 216 BUS_MSTOP(1, BIT(0))), 217 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 218 BUS_MSTOP(1, BIT(0))), 219 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 220 BUS_MSTOP(5, BIT(12))), 221 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 222 BUS_MSTOP(5, BIT(12))), 223 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 224 BUS_MSTOP(5, BIT(13))), 225 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 226 BUS_MSTOP(5, BIT(13))), 227 DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29, 228 BUS_MSTOP(11, BIT(3))), 229 DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30, 230 BUS_MSTOP(11, BIT(3))), 231 DEF_MOD("rsci0_ps_ps3_n", CLK_PLLCLN_DIV1024, 5, 15, 2, 31, 232 BUS_MSTOP(11, BIT(3))), 233 DEF_MOD("rsci0_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 0, 3, 0, 234 BUS_MSTOP(11, BIT(3))), 235 DEF_MOD("rsci0_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 1, 3, 1, 236 BUS_MSTOP(11, BIT(3))), 237 DEF_MOD("rsci1_pclk", CLK_PLLCLN_DIV16, 6, 2, 3, 2, 238 BUS_MSTOP(11, BIT(4))), 239 DEF_MOD("rsci1_tclk", CLK_PLLCLN_DIV16, 6, 3, 3, 3, 240 BUS_MSTOP(11, BIT(4))), 241 DEF_MOD("rsci1_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 4, 3, 4, 242 BUS_MSTOP(11, BIT(4))), 243 DEF_MOD("rsci1_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 5, 3, 5, 244 BUS_MSTOP(11, BIT(4))), 245 DEF_MOD("rsci1_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 6, 3, 6, 246 BUS_MSTOP(11, BIT(4))), 247 DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7, 248 BUS_MSTOP(11, BIT(5))), 249 DEF_MOD("rsci2_tclk", CLK_PLLCLN_DIV16, 6, 8, 3, 8, 250 BUS_MSTOP(11, BIT(5))), 251 DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9, 252 BUS_MSTOP(11, BIT(5))), 253 DEF_MOD("rsci2_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 10, 3, 10, 254 BUS_MSTOP(11, BIT(5))), 255 DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11, 256 BUS_MSTOP(11, BIT(5))), 257 DEF_MOD("rsci3_pclk", CLK_PLLCLN_DIV16, 6, 12, 3, 12, 258 BUS_MSTOP(11, BIT(6))), 259 DEF_MOD("rsci3_tclk", CLK_PLLCLN_DIV16, 6, 13, 3, 13, 260 BUS_MSTOP(11, BIT(6))), 261 DEF_MOD("rsci3_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 14, 3, 14, 262 BUS_MSTOP(11, BIT(6))), 263 DEF_MOD("rsci3_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 15, 3, 15, 264 BUS_MSTOP(11, BIT(6))), 265 DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16, 266 BUS_MSTOP(11, BIT(6))), 267 DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17, 268 BUS_MSTOP(11, BIT(7))), 269 DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18, 270 BUS_MSTOP(11, BIT(7))), 271 DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19, 272 BUS_MSTOP(11, BIT(7))), 273 DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20, 274 BUS_MSTOP(11, BIT(7))), 275 DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21, 276 BUS_MSTOP(11, BIT(7))), 277 DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22, 278 BUS_MSTOP(11, BIT(8))), 279 DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23, 280 BUS_MSTOP(11, BIT(8))), 281 DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24, 282 BUS_MSTOP(11, BIT(8))), 283 DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25, 284 BUS_MSTOP(11, BIT(8))), 285 DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26, 286 BUS_MSTOP(11, BIT(8))), 287 DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27, 288 BUS_MSTOP(11, BIT(9))), 289 DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28, 290 BUS_MSTOP(11, BIT(9))), 291 DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29, 292 BUS_MSTOP(11, BIT(9))), 293 DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30, 294 BUS_MSTOP(11, BIT(9))), 295 DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31, 296 BUS_MSTOP(11, BIT(9))), 297 DEF_MOD("rsci7_pclk", CLK_PLLCLN_DIV16, 8, 0, 4, 0, 298 BUS_MSTOP(11, BIT(10))), 299 DEF_MOD("rsci7_tclk", CLK_PLLCLN_DIV16, 8, 1, 4, 1, 300 BUS_MSTOP(11, BIT(10))), 301 DEF_MOD("rsci7_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 2, 4, 2, 302 BUS_MSTOP(11, BIT(10))), 303 DEF_MOD("rsci7_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 3, 4, 3, 304 BUS_MSTOP(11, BIT(10))), 305 DEF_MOD("rsci7_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 4, 4, 4, 306 BUS_MSTOP(11, BIT(10))), 307 DEF_MOD("rsci8_pclk", CLK_PLLCLN_DIV16, 8, 5, 4, 5, 308 BUS_MSTOP(11, BIT(11))), 309 DEF_MOD("rsci8_tclk", CLK_PLLCLN_DIV16, 8, 6, 4, 6, 310 BUS_MSTOP(11, BIT(11))), 311 DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7, 312 BUS_MSTOP(11, BIT(11))), 313 DEF_MOD("rsci8_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 8, 4, 8, 314 BUS_MSTOP(11, BIT(11))), 315 DEF_MOD("rsci8_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 9, 4, 9, 316 BUS_MSTOP(11, BIT(11))), 317 DEF_MOD("rsci9_pclk", CLK_PLLCLN_DIV16, 8, 10, 4, 10, 318 BUS_MSTOP(11, BIT(12))), 319 DEF_MOD("rsci9_tclk", CLK_PLLCLN_DIV16, 8, 11, 4, 11, 320 BUS_MSTOP(11, BIT(12))), 321 DEF_MOD("rsci9_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 12, 4, 12, 322 BUS_MSTOP(11, BIT(12))), 323 DEF_MOD("rsci9_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 13, 4, 13, 324 BUS_MSTOP(11, BIT(12))), 325 DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14, 326 BUS_MSTOP(11, BIT(12))), 327 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 328 BUS_MSTOP(3, BIT(14))), 329 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16, 330 BUS_MSTOP(10, BIT(15))), 331 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17, 332 BUS_MSTOP(10, BIT(15))), 333 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18, 334 BUS_MSTOP(10, BIT(15))), 335 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 336 BUS_MSTOP(3, BIT(13))), 337 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 338 BUS_MSTOP(1, BIT(1))), 339 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 340 BUS_MSTOP(1, BIT(2))), 341 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 342 BUS_MSTOP(1, BIT(3))), 343 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 344 BUS_MSTOP(1, BIT(4))), 345 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 346 BUS_MSTOP(1, BIT(5))), 347 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 348 BUS_MSTOP(1, BIT(6))), 349 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 350 BUS_MSTOP(1, BIT(7))), 351 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 352 BUS_MSTOP(1, BIT(8))), 353 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28, 354 BUS_MSTOP(10, BIT(14))), 355 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29, 356 BUS_MSTOP(10, BIT(14))), 357 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30, 358 BUS_MSTOP(10, BIT(14))), 359 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31, 360 BUS_MSTOP(4, BIT(5))), 361 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0, 362 BUS_MSTOP(4, BIT(5))), 363 DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2, 364 BUS_MSTOP(4, BIT(5))), 365 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 366 BUS_MSTOP(8, BIT(2))), 367 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 368 BUS_MSTOP(8, BIT(2))), 369 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 370 BUS_MSTOP(8, BIT(2))), 371 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 372 BUS_MSTOP(8, BIT(2))), 373 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 374 BUS_MSTOP(8, BIT(3))), 375 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 376 BUS_MSTOP(8, BIT(3))), 377 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 378 BUS_MSTOP(8, BIT(3))), 379 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 380 BUS_MSTOP(8, BIT(3))), 381 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 382 BUS_MSTOP(8, BIT(4))), 383 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 384 BUS_MSTOP(8, BIT(4))), 385 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 386 BUS_MSTOP(8, BIT(4))), 387 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 388 BUS_MSTOP(8, BIT(4))), 389 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15, 390 BUS_MSTOP(7, BIT(12))), 391 DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16, 392 BUS_MSTOP(7, BIT(14))), 393 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19, 394 BUS_MSTOP(7, BIT(7))), 395 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20, 396 BUS_MSTOP(7, BIT(8))), 397 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21, 398 BUS_MSTOP(7, BIT(9))), 399 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22, 400 BUS_MSTOP(7, BIT(10))), 401 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23, 402 BUS_MSTOP(7, BIT(11))), 403 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24, 404 BUS_MSTOP(8, BIT(5)), 1), 405 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25, 406 BUS_MSTOP(8, BIT(5)), 1), 407 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26, 408 BUS_MSTOP(8, BIT(5)), 1), 409 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27, 410 BUS_MSTOP(8, BIT(5)), 1), 411 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, 412 BUS_MSTOP(8, BIT(5))), 413 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, 414 BUS_MSTOP(8, BIT(5))), 415 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30, 416 BUS_MSTOP(8, BIT(6)), 1), 417 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31, 418 BUS_MSTOP(8, BIT(6)), 1), 419 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0, 420 BUS_MSTOP(8, BIT(6)), 1), 421 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1, 422 BUS_MSTOP(8, BIT(6)), 1), 423 DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, 424 BUS_MSTOP(8, BIT(6))), 425 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, 426 BUS_MSTOP(8, BIT(6))), 427 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 428 BUS_MSTOP(9, BIT(4))), 429 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 430 BUS_MSTOP(9, BIT(4))), 431 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 432 BUS_MSTOP(9, BIT(4))), 433 DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16, 434 BUS_MSTOP(3, BIT(4))), 435 DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, 436 BUS_MSTOP(3, BIT(4))), 437 DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, 438 BUS_MSTOP(3, BIT(4))), 439 DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, 440 BUS_MSTOP(2, BIT(15))), 441}; 442 443static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 444 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 445 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */ 446 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */ 447 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */ 448 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */ 449 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */ 450 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 451 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 452 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 453 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */ 454 DEF_RST(5, 10, 2, 11), /* GPT_0_RST_S_REG */ 455 DEF_RST(5, 11, 2, 12), /* GPT_1_RST_P_REG */ 456 DEF_RST(5, 12, 2, 13), /* GPT_1_RST_S_REG */ 457 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 458 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 459 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 460 DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */ 461 DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */ 462 DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */ 463 DEF_RST(8, 4, 3, 21), /* RSCI1_TRESETN */ 464 DEF_RST(8, 5, 3, 22), /* RSCI2_PRESETN */ 465 DEF_RST(8, 6, 3, 23), /* RSCI2_TRESETN */ 466 DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */ 467 DEF_RST(8, 8, 3, 25), /* RSCI3_TRESETN */ 468 DEF_RST(8, 9, 3, 26), /* RSCI4_PRESETN */ 469 DEF_RST(8, 10, 3, 27), /* RSCI4_TRESETN */ 470 DEF_RST(8, 11, 3, 28), /* RSCI5_PRESETN */ 471 DEF_RST(8, 12, 3, 29), /* RSCI5_TRESETN */ 472 DEF_RST(8, 13, 3, 30), /* RSCI6_PRESETN */ 473 DEF_RST(8, 14, 3, 31), /* RSCI6_TRESETN */ 474 DEF_RST(8, 15, 4, 0), /* RSCI7_PRESETN */ 475 DEF_RST(9, 0, 4, 1), /* RSCI7_TRESETN */ 476 DEF_RST(9, 1, 4, 2), /* RSCI8_PRESETN */ 477 DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */ 478 DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */ 479 DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */ 480 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 481 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */ 482 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */ 483 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 484 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 485 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 486 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 487 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 488 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 489 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 490 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 491 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 492 DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */ 493 DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */ 494 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */ 495 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */ 496 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 497 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 498 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 499 DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */ 500 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */ 501 DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */ 502 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ 503 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ 504 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ 505 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ 506 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 507 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 508 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 509 DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */ 510 DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */ 511 DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */ 512 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ 513}; 514 515const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { 516 /* Core Clocks */ 517 .core_clks = r9a09g047_core_clks, 518 .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks), 519 .last_dt_core_clk = LAST_DT_CORE_CLK, 520 .num_total_core_clks = MOD_CLK_BASE, 521 522 /* Module Clocks */ 523 .mod_clks = r9a09g047_mod_clks, 524 .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks), 525 .num_hw_mod_clks = 28 * 16, 526 527 /* Resets */ 528 .resets = r9a09g047_resets, 529 .num_resets = ARRAY_SIZE(r9a09g047_resets), 530 531 .num_mstop_bits = 208, 532};
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