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r9a07g044-cpg.c
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linux-6.19.14/drivers/clk/renesas/r9a07g044-cpg.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * RZ/G2L CPG driver 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/device.h> 10#include <linux/init.h> 11#include <linux/kernel.h> 12 13#include <dt-bindings/clock/r9a07g044-cpg.h> 14#include <dt-bindings/clock/r9a07g054-cpg.h> 15 16#include "rzg2l-cpg.h" 17 18/* Specific registers. */ 19#define CPG_PL2SDHI_DSEL (0x218) 20 21/* Clock select configuration. */ 22#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) 23#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) 24 25/* Clock status configuration. */ 26#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1) 27#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1) 28 29enum clk_ids { 30 /* Core Clock Outputs exported to DT */ 31 LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, 32 33 /* External Input Clocks */ 34 CLK_EXTAL, 35 36 /* Internal Core Clocks */ 37 CLK_OSC_DIV1000, 38 CLK_PLL1, 39 CLK_PLL2, 40 CLK_PLL2_DIV2, 41 CLK_PLL2_DIV2_8, 42 CLK_PLL2_DIV2_10, 43 CLK_PLL3, 44 CLK_PLL3_400, 45 CLK_PLL3_533, 46 CLK_M2_DIV2, 47 CLK_PLL3_DIV2, 48 CLK_PLL3_DIV2_2, 49 CLK_PLL3_DIV2_4, 50 CLK_PLL3_DIV2_4_2, 51 CLK_SEL_PLL3_3, 52 CLK_DIV_PLL3_C, 53 CLK_PLL4, 54 CLK_PLL5, 55 CLK_PLL5_FOUTPOSTDIV, 56 CLK_PLL5_FOUT1PH0, 57 CLK_PLL5_FOUT3, 58 CLK_PLL5_250, 59 CLK_PLL6, 60 CLK_PLL6_250, 61 CLK_P1_DIV2, 62 CLK_PLL2_800, 63 CLK_PLL2_SDHI_533, 64 CLK_PLL2_SDHI_400, 65 CLK_PLL2_SDHI_266, 66 CLK_SD0_DIV4, 67 CLK_SD1_DIV4, 68 CLK_SEL_GPU2, 69 CLK_SEL_PLL5_4, 70 CLK_DSI_DIV, 71 CLK_PLL2_533, 72 CLK_PLL2_533_DIV2, 73 CLK_DIV_DSI_LPCLK, 74 75 /* Module Clocks */ 76 MOD_CLK_BASE, 77}; 78 79/* Divider tables */ 80static const struct clk_div_table dtable_1_8[] = { 81 {0, 1}, 82 {1, 2}, 83 {2, 4}, 84 {3, 8}, 85 {0, 0}, 86}; 87 88static const struct clk_div_table dtable_1_32[] = { 89 {0, 1}, 90 {1, 2}, 91 {2, 4}, 92 {3, 8}, 93 {4, 32}, 94 {0, 0}, 95}; 96 97#ifdef CONFIG_CLK_R9A07G054 98static const struct clk_div_table dtable_4_32[] = { 99 {3, 4}, 100 {4, 5}, 101 {5, 6}, 102 {6, 7}, 103 {7, 8}, 104 {8, 9}, 105 {9, 10}, 106 {10, 11}, 107 {11, 12}, 108 {12, 13}, 109 {13, 14}, 110 {14, 15}, 111 {15, 16}, 112 {16, 17}, 113 {17, 18}, 114 {18, 19}, 115 {19, 20}, 116 {20, 21}, 117 {21, 22}, 118 {22, 23}, 119 {23, 24}, 120 {24, 25}, 121 {25, 26}, 122 {26, 27}, 123 {27, 28}, 124 {28, 29}, 125 {29, 30}, 126 {30, 31}, 127 {31, 32}, 128 {0, 0}, 129}; 130#endif 131 132static const struct clk_div_table dtable_16_128[] = { 133 {0, 16}, 134 {1, 32}, 135 {2, 64}, 136 {3, 128}, 137 {0, 0}, 138}; 139 140/* Mux clock tables */ 141static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 142static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; 143static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 144static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" }; 145static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; 146 147static const u32 mtable_sdhi[] = { 1, 2, 3 }; 148 149static const struct { 150 struct cpg_core_clk common[56]; 151#ifdef CONFIG_CLK_R9A07G054 152 struct cpg_core_clk drp[3]; 153#endif 154} core_clks __initconst = { 155 .common = { 156 /* External Clock Inputs */ 157 DEF_INPUT("extal", CLK_EXTAL), 158 159 /* Internal Core Clocks */ 160 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), 161 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 162 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 163 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), 164 DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3), 165 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), 166 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), 167 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), 168 169 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 170 DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), 171 172 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 173 174 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 175 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), 176 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), 177 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), 178 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), 179 180 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), 181 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), 182 183 DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2), 184 185 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 186 DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), 187 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 188 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 189 DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), 190 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), 191 192 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), 193 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), 194 DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2), 195 DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), 196 DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), 197 DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4), 198 DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2, 199 DIVDSILPCLK, dtable_16_128), 200 201 /* Core output clk */ 202 DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), 203 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), 204 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), 205 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), 206 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), 207 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), 208 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), 209 DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 210 DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), 211 DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2), 212 DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), 213 DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), 214 DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi, 215 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 216 DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi, 217 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 218 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), 219 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), 220 DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8), 221 DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), 222 DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2), 223 DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2), 224 DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT), 225 DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1), 226 DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1), 227 }, 228#ifdef CONFIG_CLK_R9A07G054 229 .drp = { 230 DEF_FIXED("DRP_M", R9A07G054_CLK_DRP_M, CLK_PLL3, 1, 5), 231 DEF_FIXED("DRP_D", R9A07G054_CLK_DRP_D, CLK_PLL3, 1, 2), 232 DEF_DIV("DRP_A", R9A07G054_CLK_DRP_A, CLK_PLL3, DIVPL3E, dtable_4_32), 233 }, 234#endif 235}; 236 237static const struct { 238 struct rzg2l_mod_clk common[79]; 239#ifdef CONFIG_CLK_R9A07G054 240 struct rzg2l_mod_clk drp[5]; 241#endif 242} mod_clks = { 243 .common = { 244 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, 245 0x514, 0, MSTOP(BUS_REG1, BIT(7))), 246 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, 247 0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))), 248 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 249 0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))), 250 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, 251 0x52c, 0, MSTOP(BUS_REG1, BIT(2))), 252 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, 253 0x52c, 1, MSTOP(BUS_REG1, BIT(3))), 254 DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, 255 0x534, 0, MSTOP(BUS_REG0, BIT(4))), 256 DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, 257 0x534, 1, MSTOP(BUS_REG0, BIT(5))), 258 DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 259 0x534, 2, MSTOP(BUS_REG0, BIT(6))), 260 DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0, 261 0x538, 0, MSTOP(BUS_MCPU1, BIT(2))), 262 DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, 263 0x540, 0, MSTOP(BUS_MCPU1, BIT(4))), 264 DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, 265 0x544, 0, MSTOP(BUS_MCPU1, BIT(5))), 266 DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0, 267 0x544, 1, MSTOP(BUS_MCPU1, BIT(6))), 268 DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0, 269 0x544, 2, MSTOP(BUS_MCPU1, BIT(7))), 270 DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0, 271 0x544, 3, MSTOP(BUS_MCPU1, BIT(8))), 272 DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, 273 0x548, 0, MSTOP(BUS_REG0, BIT(2))), 274 DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, 275 0x548, 1, MSTOP(BUS_REG0, BIT(2))), 276 DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, 277 0x548, 2, MSTOP(BUS_REG0, BIT(3))), 278 DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, 279 0x548, 3, MSTOP(BUS_REG0, BIT(3))), 280 DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, 281 0x550, 0, MSTOP(BUS_MCPU1, BIT(1))), 282 DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, 283 0x550, 1, MSTOP(BUS_MCPU1, BIT(1))), 284 DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, 285 0x554, 0, MSTOP(BUS_PERI_COM, BIT(0))), 286 DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, 287 0x554, 1, MSTOP(BUS_PERI_COM, BIT(0))), 288 DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, 289 0x554, 2, MSTOP(BUS_PERI_COM, BIT(0))), 290 DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, 291 0x554, 3, MSTOP(BUS_PERI_COM, BIT(0))), 292 DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, 293 0x554, 4, MSTOP(BUS_PERI_COM, BIT(1))), 294 DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, 295 0x554, 5, MSTOP(BUS_PERI_COM, BIT(1))), 296 DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, 297 0x554, 6, MSTOP(BUS_PERI_COM, BIT(1))), 298 DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, 299 0x554, 7, MSTOP(BUS_PERI_COM, BIT(1))), 300 DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, 301 0x558, 0, MSTOP(BUS_REG1, BIT(4))), 302 DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, 303 0x558, 1, 0), 304 DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 305 0x558, 2, 0), 306 DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2, 307 0x564, 0, MSTOP(BUS_PERI_VIDEO, BIT(3))), 308 DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2, 309 0x564, 1, MSTOP(BUS_PERI_VIDEO, BIT(3))), 310 DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT, 311 0x564, 2, MSTOP(BUS_PERI_VIDEO, BIT(3))), 312 DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0, 313 0x564, 3, MSTOP(BUS_PERI_VIDEO, BIT(3))), 314 DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1, 315 0x568, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))), 316 DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2, 317 0x568, 1, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))), 318 DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1, 319 0x568, 2, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))), 320 DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2, 321 0x568, 3, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))), 322 DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3, 323 0x568, 4, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))), 324 DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4, 325 0x568, 5, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))), 326 DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0, 327 0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))), 328 DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT, 329 0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))), 330 DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3, 331 0x56c, 1, MSTOP(BUS_PERI_VIDEO, BIT(9))), 332 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 333 0x570, 0, MSTOP(BUS_MCPU1, BIT(10))), 334 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, 335 0x570, 1, MSTOP(BUS_MCPU1, BIT(10))), 336 DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, 337 0x570, 2, MSTOP(BUS_MCPU1, BIT(11))), 338 DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, 339 0x570, 3, MSTOP(BUS_MCPU1, BIT(11))), 340 DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, 341 0x570, 4, MSTOP(BUS_MCPU1, BIT(12))), 342 DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, 343 0x570, 5, MSTOP(BUS_MCPU1, BIT(12))), 344 DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, 345 0x570, 6, MSTOP(BUS_MCPU1, BIT(13))), 346 DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, 347 0x570, 7, MSTOP(BUS_MCPU1, BIT(13))), 348 DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, 349 0x578, 0, MSTOP(BUS_PERI_COM, BIT(5))), 350 DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, 351 0x578, 1, MSTOP(BUS_PERI_COM, BIT(7))), 352 DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, 353 0x578, 2, MSTOP(BUS_PERI_COM, BIT(6))), 354 DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, 355 0x578, 3, MSTOP(BUS_PERI_COM, BIT(4))), 356 DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, 357 0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))), 358 DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, 359 0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))), 360 DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, 361 0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))), 362 DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, 363 0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))), 364 DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, 365 0x580, 0, MSTOP(BUS_MCPU2, BIT(10))), 366 DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, 367 0x580, 1, MSTOP(BUS_MCPU2, BIT(11))), 368 DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, 369 0x580, 2, MSTOP(BUS_MCPU2, BIT(12))), 370 DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, 371 0x580, 3, MSTOP(BUS_MCPU2, BIT(13))), 372 DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, 373 0x584, 0, MSTOP(BUS_MCPU2, BIT(1))), 374 DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, 375 0x584, 1, MSTOP(BUS_MCPU2, BIT(2))), 376 DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, 377 0x584, 2, MSTOP(BUS_MCPU2, BIT(3))), 378 DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, 379 0x584, 3, MSTOP(BUS_MCPU2, BIT(4))), 380 DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, 381 0x584, 4, MSTOP(BUS_MCPU2, BIT(5))), 382 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, 383 0x588, 0, MSTOP(BUS_MCPU2, BIT(7))), 384 DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, 385 0x588, 1, MSTOP(BUS_MCPU2, BIT(8))), 386 DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, 387 0x590, 0, MSTOP(BUS_MCPU1, BIT(14))), 388 DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, 389 0x590, 1, MSTOP(BUS_MCPU1, BIT(15))), 390 DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, 391 0x590, 2, MSTOP(BUS_MCPU2, BIT(0))), 392 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, 393 0x594, 0, MSTOP(BUS_MCPU2, BIT(9))), 394 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, 395 0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))), 396 DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, 397 0x5a8, 0, MSTOP(BUS_MCPU2, BIT(14))), 398 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, 399 0x5a8, 1, MSTOP(BUS_MCPU2, BIT(14))), 400 DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, 401 0x5ac, 0, MSTOP(BUS_MCPU2, BIT(15))), 402 }, 403#ifdef CONFIG_CLK_R9A07G054 404 .drp = { 405 DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK, 406 0x5e8, 0, 0), 407 DEF_MOD("stpai_aclk", R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1, 408 0x5e8, 1, 0), 409 DEF_MOD("stpai_mclk", R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M, 410 0x5e8, 2, 0), 411 DEF_MOD("stpai_dclkin", R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D, 412 0x5e8, 3, 0), 413 DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A, 414 0x5e8, 4, 0), 415 }, 416#endif 417}; 418 419static const struct rzg2l_reset r9a07g044_resets[] = { 420 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), 421 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), 422 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), 423 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0), 424 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1), 425 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), 426 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), 427 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), 428 DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0), 429 DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), 430 DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0), 431 DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1), 432 DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2), 433 DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3), 434 DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), 435 DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), 436 DEF_RST(R9A07G044_SPI_RST, 0x850, 0), 437 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), 438 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1), 439 DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), 440 DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), 441 DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), 442 DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0), 443 DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1), 444 DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2), 445 DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0), 446 DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1), 447 DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2), 448 DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0), 449 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), 450 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), 451 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2), 452 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3), 453 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0), 454 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1), 455 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2), 456 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3), 457 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0), 458 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1), 459 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0), 460 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1), 461 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2), 462 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3), 463 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0), 464 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1), 465 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2), 466 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3), 467 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4), 468 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0), 469 DEF_RST(R9A07G044_SCI1_RST, 0x888, 1), 470 DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0), 471 DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1), 472 DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2), 473 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0), 474 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1), 475 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0), 476 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1), 477 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2), 478 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0), 479 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1), 480 DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0), 481#ifdef CONFIG_CLK_R9A07G054 482 DEF_RST(R9A07G054_STPAI_ARESETN, 0x8e8, 0), 483#endif 484}; 485 486static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 487 MOD_CLK_BASE + R9A07G044_GIC600_GICCLK, 488 MOD_CLK_BASE + R9A07G044_IA55_CLK, 489 MOD_CLK_BASE + R9A07G044_DMAC_ACLK, 490}; 491 492static const unsigned int r9a07g044_no_pm_mod_clks[] = { 493 MOD_CLK_BASE + R9A07G044_CRU_SYSCLK, 494 MOD_CLK_BASE + R9A07G044_CRU_VCLK, 495}; 496 497#ifdef CONFIG_CLK_R9A07G044 498const struct rzg2l_cpg_info r9a07g044_cpg_info = { 499 /* Core Clocks */ 500 .core_clks = core_clks.common, 501 .num_core_clks = ARRAY_SIZE(core_clks.common), 502 .last_dt_core_clk = LAST_DT_CORE_CLK, 503 .num_total_core_clks = MOD_CLK_BASE, 504 505 /* Critical Module Clocks */ 506 .crit_mod_clks = r9a07g044_crit_mod_clks, 507 .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), 508 509 /* Module Clocks */ 510 .mod_clks = mod_clks.common, 511 .num_mod_clks = ARRAY_SIZE(mod_clks.common), 512 .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, 513 514 /* No PM Module Clocks */ 515 .no_pm_mod_clks = r9a07g044_no_pm_mod_clks, 516 .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks), 517 518 /* Resets */ 519 .resets = r9a07g044_resets, 520 .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ 521 522 .has_clk_mon_regs = true, 523}; 524#endif 525 526#ifdef CONFIG_CLK_R9A07G054 527const struct rzg2l_cpg_info r9a07g054_cpg_info = { 528 /* Core Clocks */ 529 .core_clks = core_clks.common, 530 .num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp), 531 .last_dt_core_clk = LAST_DT_CORE_CLK, 532 .num_total_core_clks = MOD_CLK_BASE, 533 534 /* Critical Module Clocks */ 535 .crit_mod_clks = r9a07g044_crit_mod_clks, 536 .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), 537 538 /* Module Clocks */ 539 .mod_clks = mod_clks.common, 540 .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp), 541 .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1, 542 543 /* No PM Module Clocks */ 544 .no_pm_mod_clks = r9a07g044_no_pm_mod_clks, 545 .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks), 546 547 /* Resets */ 548 .resets = r9a07g044_resets, 549 .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ 550 551 .has_clk_mon_regs = true, 552}; 553#endif
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