r9a07g043-cpg.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * RZ/G2UL CPG driver
  4 *
  5 * Copyright (C) 2022 Renesas Electronics Corp.
  6 */
  7
  8#include <linux/clk-provider.h>
  9#include <linux/device.h>
 10#include <linux/init.h>
 11#include <linux/kernel.h>
 12
 13#include <dt-bindings/clock/r9a07g043-cpg.h>
 14
 15#include "rzg2l-cpg.h"
 16
 17/* Specific registers. */
 18#define CPG_PL2SDHI_DSEL	(0x218)
 19
 20/* Clock select configuration. */
 21#define SEL_SDHI0		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
 22#define SEL_SDHI1		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)
 23
 24/* Clock status configuration. */
 25#define SEL_SDHI0_STS		SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)
 26#define SEL_SDHI1_STS		SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)
 27
 28enum clk_ids {
 29	/* Core Clock Outputs exported to DT */
 30	LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,
 31
 32	/* External Input Clocks */
 33	CLK_EXTAL,
 34
 35	/* Internal Core Clocks */
 36	CLK_OSC_DIV1000,
 37	CLK_PLL1,
 38	CLK_PLL2,
 39	CLK_PLL2_DIV2,
 40	CLK_PLL2_DIV2_8,
 41	CLK_PLL2_DIV2_10,
 42	CLK_PLL3,
 43	CLK_PLL3_400,
 44	CLK_PLL3_533,
 45	CLK_PLL3_DIV2,
 46	CLK_PLL3_DIV2_4,
 47	CLK_PLL3_DIV2_4_2,
 48	CLK_SEL_PLL3_3,
 49	CLK_DIV_PLL3_C,
 50#ifdef CONFIG_ARM64
 51	CLK_M2_DIV2,
 52	CLK_PLL5,
 53	CLK_PLL5_500,
 54	CLK_PLL5_250,
 55	CLK_PLL5_FOUTPOSTDIV,
 56	CLK_DSI_DIV,
 57#endif
 58	CLK_PLL6,
 59	CLK_PLL6_250,
 60	CLK_P1_DIV2,
 61	CLK_PLL2_800,
 62	CLK_PLL2_SDHI_533,
 63	CLK_PLL2_SDHI_400,
 64	CLK_PLL2_SDHI_266,
 65	CLK_SD0_DIV4,
 66	CLK_SD1_DIV4,
 67
 68	/* Module Clocks */
 69	MOD_CLK_BASE,
 70};
 71
 72/* Divider tables */
 73static const struct clk_div_table dtable_1_8[] = {
 74	{0, 1},
 75	{1, 2},
 76	{2, 4},
 77	{3, 8},
 78	{0, 0},
 79};
 80
 81static const struct clk_div_table dtable_1_32[] = {
 82	{0, 1},
 83	{1, 2},
 84	{2, 4},
 85	{3, 8},
 86	{4, 32},
 87	{0, 0},
 88};
 89
 90/* Mux clock tables */
 91static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
 92#ifdef CONFIG_ARM64
 93static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };
 94#endif
 95static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
 96
 97static const u32 mtable_sdhi[] = { 1, 2, 3 };
 98
 99static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
100	/* External Clock Inputs */
101	DEF_INPUT("extal", CLK_EXTAL),
102
103	/* Internal Core Clocks */
104	DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
105	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
106	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
107	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
108	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
109	DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
110	DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
111	DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
112	DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
113	DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
114	DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
115	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
116	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
117	DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
118	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
119	DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
120	DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
121	DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
122	DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
123#ifdef CONFIG_ARM64
124	DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
125	DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
126	DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
127	DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),
128#endif
129	DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
130	DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
131
132	/* Core output clk */
133	DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
134	DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
135	DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
136	DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
137	DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
138	DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
139	DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
140	DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
141	DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
142#ifdef CONFIG_ARM64
143	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
144#endif
145#ifdef CONFIG_RISCV
146	DEF_FIXED("HP", R9A07G043_CLK_HP, CLK_PLL6_250, 1, 1),
147#endif
148	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
149	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
150	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
151		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
152	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,
153		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
154	DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
155	DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
156#ifdef CONFIG_ARM64
157	DEF_FIXED("M2", R9A07G043_CLK_M2, CLK_PLL3_533, 1, 2),
158	DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G043_CLK_M2, 1, 2),
159	DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_PLL5_FOUTPOSTDIV, CLK_SET_RATE_PARENT),
160	DEF_FIXED("M3", R9A07G043_CLK_M3, CLK_DSI_DIV, 1, 1),
161#endif
162};
163
164static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
165#ifdef CONFIG_ARM64
166	DEF_MOD("gic",		R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
167				0x514, 0, MSTOP(BUS_REG1, BIT(7))),
168	DEF_MOD("ia55_pclk",	R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
169				0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))),
170	DEF_MOD("ia55_clk",	R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
171				0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))),
172#endif
173#ifdef CONFIG_RISCV
174	DEF_MOD("iax45_pclk",	R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
175				0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))),
176	DEF_MOD("iax45_clk",	R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
177				0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))),
178#endif
179	DEF_MOD("dmac_aclk",	R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
180				0x52c, 0, MSTOP(BUS_REG1, BIT(2))),
181	DEF_MOD("dmac_pclk",	R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
182				0x52c, 1, MSTOP(BUS_REG1, BIT(3))),
183	DEF_MOD("ostm0_pclk",	R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
184				0x534, 0, MSTOP(BUS_REG0, BIT(4))),
185	DEF_MOD("ostm1_pclk",	R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
186				0x534, 1, MSTOP(BUS_REG0, BIT(5))),
187	DEF_MOD("ostm2_pclk",	R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
188				0x534, 2, MSTOP(BUS_REG0, BIT(6))),
189	DEF_MOD("mtu_x_mck",	R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0,
190				0x538, 0, MSTOP(BUS_MCPU1, BIT(2))),
191	DEF_MOD("wdt0_pclk",	R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
192				0x548, 0, MSTOP(BUS_REG0, BIT(2))),
193	DEF_MOD("wdt0_clk",	R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
194				0x548, 1, MSTOP(BUS_REG0, BIT(2))),
195	DEF_MOD("spi_clk2",	R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
196				0x550, 0, MSTOP(BUS_MCPU1, BIT(1))),
197	DEF_MOD("spi_clk",	R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
198				0x550, 1, MSTOP(BUS_MCPU1, BIT(1))),
199	DEF_MOD("sdhi0_imclk",	R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
200				0x554, 0, MSTOP(BUS_PERI_COM, BIT(0))),
201	DEF_MOD("sdhi0_imclk2",	R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
202				0x554, 1, MSTOP(BUS_PERI_COM, BIT(0))),
203	DEF_MOD("sdhi0_clk_hs",	R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0,
204				0x554, 2, MSTOP(BUS_PERI_COM, BIT(0))),
205	DEF_MOD("sdhi0_aclk",	R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1,
206				0x554, 3, MSTOP(BUS_PERI_COM, BIT(0))),
207	DEF_MOD("sdhi1_imclk",	R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4,
208				0x554, 4, MSTOP(BUS_PERI_COM, BIT(1))),
209	DEF_MOD("sdhi1_imclk2",	R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4,
210				0x554, 5, MSTOP(BUS_PERI_COM, BIT(1))),
211	DEF_MOD("sdhi1_clk_hs",	R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1,
212				0x554, 6, MSTOP(BUS_PERI_COM, BIT(1))),
213	DEF_MOD("sdhi1_aclk",	R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
214				0x554, 7, MSTOP(BUS_PERI_COM, BIT(1))),
215#ifdef CONFIG_ARM64
216	DEF_MOD("cru_sysclk",	R9A07G043_CRU_SYSCLK, CLK_M2_DIV2,
217				0x564, 0, MSTOP(BUS_PERI_VIDEO, BIT(3))),
218	DEF_MOD("cru_vclk",	R9A07G043_CRU_VCLK, R9A07G043_CLK_M2,
219				0x564, 1, MSTOP(BUS_PERI_VIDEO, BIT(3))),
220	DEF_MOD("cru_pclk",	R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT,
221				0x564, 2, MSTOP(BUS_PERI_VIDEO, BIT(3))),
222	DEF_MOD("cru_aclk",	R9A07G043_CRU_ACLK, R9A07G043_CLK_M0,
223				0x564, 3, MSTOP(BUS_PERI_VIDEO, BIT(3))),
224	DEF_COUPLED("lcdc_clk_a", R9A07G043_LCDC_CLK_A, R9A07G043_CLK_M0,
225				0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
226	DEF_COUPLED("lcdc_clk_p", R9A07G043_LCDC_CLK_P, R9A07G043_CLK_ZT,
227				0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
228	DEF_MOD("lcdc_clk_d",	R9A07G043_LCDC_CLK_D, R9A07G043_CLK_M3,
229				0x56c, 1, MSTOP(BUS_PERI_VIDEO, BIT(9))),
230#endif
231	DEF_MOD("ssi0_pclk",	R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,
232				0x570, 0, MSTOP(BUS_MCPU1, BIT(10))),
233	DEF_MOD("ssi0_sfr",	R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,
234				0x570, 1, MSTOP(BUS_MCPU1, BIT(10))),
235	DEF_MOD("ssi1_pclk",	R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,
236				0x570, 2, MSTOP(BUS_MCPU1, BIT(11))),
237	DEF_MOD("ssi1_sfr",	R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,
238				0x570, 3, MSTOP(BUS_MCPU1, BIT(11))),
239	DEF_MOD("ssi2_pclk",	R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,
240				0x570, 4, MSTOP(BUS_MCPU1, BIT(12))),
241	DEF_MOD("ssi2_sfr",	R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,
242				0x570, 5, MSTOP(BUS_MCPU1, BIT(12))),
243	DEF_MOD("ssi3_pclk",	R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,
244				0x570, 6, MSTOP(BUS_MCPU1, BIT(13))),
245	DEF_MOD("ssi3_sfr",	R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
246				0x570, 7, MSTOP(BUS_MCPU1, BIT(13))),
247	DEF_MOD("usb0_host",	R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
248				0x578, 0, MSTOP(BUS_PERI_COM, BIT(5))),
249	DEF_MOD("usb1_host",	R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
250				0x578, 1, MSTOP(BUS_PERI_COM, BIT(7))),
251	DEF_MOD("usb0_func",	R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
252				0x578, 2, MSTOP(BUS_PERI_COM, BIT(6))),
253	DEF_MOD("usb_pclk",	R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
254				0x578, 3, MSTOP(BUS_PERI_COM, BIT(4))),
255	DEF_COUPLED("eth0_axi",	R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
256				0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
257	DEF_COUPLED("eth0_chi",	R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
258				0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
259	DEF_COUPLED("eth1_axi",	R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
260				0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
261	DEF_COUPLED("eth1_chi",	R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
262				0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
263	DEF_MOD("i2c0",		R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0,
264				0x580, 0, MSTOP(BUS_MCPU2, BIT(10))),
265	DEF_MOD("i2c1",		R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0,
266				0x580, 1, MSTOP(BUS_MCPU2, BIT(11))),
267	DEF_MOD("i2c2",		R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0,
268				0x580, 2, MSTOP(BUS_MCPU2, BIT(12))),
269	DEF_MOD("i2c3",		R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0,
270				0x580, 3, MSTOP(BUS_MCPU2, BIT(13))),
271	DEF_MOD("scif0",	R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
272				0x584, 0, MSTOP(BUS_MCPU2, BIT(1))),
273	DEF_MOD("scif1",	R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
274				0x584, 1, MSTOP(BUS_MCPU2, BIT(2))),
275	DEF_MOD("scif2",	R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
276				0x584, 2, MSTOP(BUS_MCPU2, BIT(3))),
277	DEF_MOD("scif3",	R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
278				0x584, 3, MSTOP(BUS_MCPU2, BIT(4))),
279	DEF_MOD("scif4",	R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
280				0x584, 4, MSTOP(BUS_MCPU2, BIT(5))),
281	DEF_MOD("sci0",		R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
282				0x588, 0, MSTOP(BUS_MCPU2, BIT(7))),
283	DEF_MOD("sci1",		R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
284				0x588, 1, MSTOP(BUS_MCPU2, BIT(8))),
285	DEF_MOD("rspi0",	R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0,
286				0x590, 0, MSTOP(BUS_MCPU1, BIT(14))),
287	DEF_MOD("rspi1",	R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0,
288				0x590, 1, MSTOP(BUS_MCPU1, BIT(15))),
289	DEF_MOD("rspi2",	R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0,
290				0x590, 2, MSTOP(BUS_MCPU2, BIT(0))),
291	DEF_MOD("canfd",	R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
292				0x594, 0, MSTOP(BUS_MCPU2, BIT(9))),
293	DEF_MOD("gpio",		R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
294				0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))),
295	DEF_MOD("adc_adclk",	R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,
296				0x5a8, 0, MSTOP(BUS_MCPU2, BIT(14))),
297	DEF_MOD("adc_pclk",	R9A07G043_ADC_PCLK, R9A07G043_CLK_P0,
298				0x5a8, 1, MSTOP(BUS_MCPU2, BIT(14))),
299	DEF_MOD("tsu_pclk",	R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
300				0x5ac, 0, MSTOP(BUS_MCPU2, BIT(15))),
301#ifdef CONFIG_RISCV
302	DEF_MOD("nceplic_aclk",	R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
303				0x608, 0, MSTOP(BUS_REG1, BIT(7))),
304#endif
305};
306
307static const struct rzg2l_reset r9a07g043_resets[] = {
308#ifdef CONFIG_ARM64
309	DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
310	DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
311	DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
312#endif
313#ifdef CONFIG_RISCV
314	DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
315#endif
316	DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
317	DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
318	DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
319	DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
320	DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
321	DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
322	DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
323	DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
324	DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
325	DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
326#ifdef CONFIG_ARM64
327	DEF_RST(R9A07G043_CRU_CMN_RSTB, 0x864, 0),
328	DEF_RST(R9A07G043_CRU_PRESETN, 0x864, 1),
329	DEF_RST(R9A07G043_CRU_ARESETN, 0x864, 2),
330	DEF_RST(R9A07G043_LCDC_RESET_N, 0x86c, 0),
331#endif
332	DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
333	DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
334	DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
335	DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
336	DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
337	DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
338	DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
339	DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
340	DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
341	DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
342	DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
343	DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),
344	DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),
345	DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),
346	DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
347	DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
348	DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
349	DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
350	DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
351	DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
352	DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
353	DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),
354	DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),
355	DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),
356	DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
357	DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
358	DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
359	DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
360	DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
361	DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
362	DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
363	DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
364#ifdef CONFIG_RISCV
365	DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),
366#endif
367
368};
369
370static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
371#ifdef CONFIG_ARM64
372	MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
373	MOD_CLK_BASE + R9A07G043_IA55_CLK,
374#endif
375#ifdef CONFIG_RISCV
376	MOD_CLK_BASE + R9A07G043_IAX45_CLK,
377	MOD_CLK_BASE + R9A07G043_NCEPLIC_ACLK,
378#endif
379	MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
380};
381
382#ifdef CONFIG_ARM64
383static const unsigned int r9a07g043_no_pm_mod_clks[] = {
384	MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
385	MOD_CLK_BASE + R9A07G043_CRU_VCLK,
386};
387#endif
388
389const struct rzg2l_cpg_info r9a07g043_cpg_info = {
390	/* Core Clocks */
391	.core_clks = r9a07g043_core_clks,
392	.num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
393	.last_dt_core_clk = LAST_DT_CORE_CLK,
394	.num_total_core_clks = MOD_CLK_BASE,
395
396	/* Critical Module Clocks */
397	.crit_mod_clks = r9a07g043_crit_mod_clks,
398	.num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
399
400	/* Module Clocks */
401	.mod_clks = r9a07g043_mod_clks,
402	.num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
403#ifdef CONFIG_ARM64
404	.num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,
405
406	/* No PM Module Clocks */
407	.no_pm_mod_clks = r9a07g043_no_pm_mod_clks,
408	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g043_no_pm_mod_clks),
409#endif
410#ifdef CONFIG_RISCV
411	.num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1,
412#endif
413
414	/* Resets */
415	.resets = r9a07g043_resets,
416#ifdef CONFIG_ARM64
417	.num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */
418#endif
419#ifdef CONFIG_RISCV
420	.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
421#endif
422
423	.has_clk_mon_regs = true,
424};