r8a779a0-cpg-mssr.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
  4 *
  5 * Copyright (C) 2020 Renesas Electronics Corp.
  6 *
  7 * Based on r8a7795-cpg-mssr.c
  8 *
  9 * Copyright (C) 2015 Glider bvba
 10 * Copyright (C) 2015 Renesas Electronics Corp.
 11 */
 12
 13#include <linux/bitfield.h>
 14#include <linux/clk.h>
 15#include <linux/clk-provider.h>
 16#include <linux/device.h>
 17#include <linux/err.h>
 18#include <linux/init.h>
 19#include <linux/kernel.h>
 20#include <linux/soc/renesas/rcar-rst.h>
 21
 22#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
 23
 24#include "renesas-cpg-mssr.h"
 25#include "rcar-gen4-cpg.h"
 26
 27enum clk_ids {
 28	/* Core Clock Outputs exported to DT */
 29	LAST_DT_CORE_CLK = R8A779A0_CLK_ZG,
 30
 31	/* External Input Clocks */
 32	CLK_EXTAL,
 33	CLK_EXTALR,
 34
 35	/* Internal Core Clocks */
 36	CLK_MAIN,
 37	CLK_PLL1,
 38	CLK_PLL20,
 39	CLK_PLL21,
 40	CLK_PLL30,
 41	CLK_PLL31,
 42	CLK_PLL4,
 43	CLK_PLL5,
 44	CLK_PLL1_DIV2,
 45	CLK_PLL20_DIV2,
 46	CLK_PLL21_DIV2,
 47	CLK_PLL30_DIV2,
 48	CLK_PLL31_DIV2,
 49	CLK_PLL5_DIV2,
 50	CLK_PLL5_DIV4,
 51	CLK_S1,
 52	CLK_S3,
 53	CLK_SDSRC,
 54	CLK_RPCSRC,
 55	CLK_OCO,
 56
 57	/* Module Clocks */
 58	MOD_CLK_BASE
 59};
 60
 61#define DEF_PLL(_name, _id, _offset)	\
 62	DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
 63		 .offset = _offset)
 64
 65#define CPG_PLL20CR	0x0834	/* PLL20 Control Register */
 66#define CPG_PLL21CR	0x0838	/* PLL21 Control Register */
 67#define CPG_PLL30CR	0x083c	/* PLL30 Control Register */
 68#define CPG_PLL31CR	0x0840	/* PLL31 Control Register */
 69#define CPG_PLL4CR	0x0844	/* PLL4 Control Register */
 70
 71static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 72	/* External Clock Inputs */
 73	DEF_INPUT("extal",  CLK_EXTAL),
 74	DEF_INPUT("extalr", CLK_EXTALR),
 75
 76	/* Internal Core Clocks */
 77	DEF_BASE(".main", CLK_MAIN,	CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
 78	DEF_BASE(".pll1", CLK_PLL1,	CLK_TYPE_GEN4_PLL1, CLK_MAIN),
 79	DEF_BASE(".pll5", CLK_PLL5,	CLK_TYPE_GEN4_PLL5, CLK_MAIN),
 80	DEF_PLL(".pll20", CLK_PLL20,	CPG_PLL20CR),
 81	DEF_PLL(".pll21", CLK_PLL21,	CPG_PLL21CR),
 82	DEF_PLL(".pll30", CLK_PLL30,	CPG_PLL30CR),
 83	DEF_PLL(".pll31", CLK_PLL31,	CPG_PLL31CR),
 84	DEF_PLL(".pll4",  CLK_PLL4,	CPG_PLL4CR),
 85
 86	DEF_FIXED(".pll1_div2",		CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),
 87	DEF_FIXED(".pll20_div2",	CLK_PLL20_DIV2,	CLK_PLL20,	2, 1),
 88	DEF_FIXED(".pll21_div2",	CLK_PLL21_DIV2,	CLK_PLL21,	2, 1),
 89	DEF_FIXED(".pll30_div2",	CLK_PLL30_DIV2,	CLK_PLL30,	2, 1),
 90	DEF_FIXED(".pll31_div2",	CLK_PLL31_DIV2,	CLK_PLL31,	2, 1),
 91	DEF_FIXED(".pll5_div2",		CLK_PLL5_DIV2,	CLK_PLL5,	2, 1),
 92	DEF_FIXED(".pll5_div4",		CLK_PLL5_DIV4,	CLK_PLL5_DIV2,	2, 1),
 93	DEF_FIXED(".s1",		CLK_S1,		CLK_PLL1_DIV2,	2, 1),
 94	DEF_FIXED(".s3",		CLK_S3,		CLK_PLL1_DIV2,	4, 1),
 95	DEF_FIXED(".sdsrc",		CLK_SDSRC,	CLK_PLL5_DIV4,	1, 1),
 96
 97	DEF_RATE(".oco",		CLK_OCO,	32768),
 98
 99	DEF_BASE(".rpcsrc",		CLK_RPCSRC,	CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
100
101	/* Core Clock Outputs */
102	DEF_GEN4_Z("z0",	R8A779A0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL20,	2, 0),
103	DEF_GEN4_Z("z1",	R8A779A0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL21,	2, 8),
104	DEF_GEN4_Z("zg",	R8A779A0_CLK_ZG,	CLK_TYPE_GEN4_Z,	CLK_PLL4,	2, 88),
105	DEF_FIXED("zx",		R8A779A0_CLK_ZX,	CLK_PLL20_DIV2,	2, 1),
106	DEF_FIXED("s1d1",	R8A779A0_CLK_S1D1,	CLK_S1,		1, 1),
107	DEF_FIXED("s1d2",	R8A779A0_CLK_S1D2,	CLK_S1,		2, 1),
108	DEF_FIXED("s1d4",	R8A779A0_CLK_S1D4,	CLK_S1,		4, 1),
109	DEF_FIXED("s1d8",	R8A779A0_CLK_S1D8,	CLK_S1,		8, 1),
110	DEF_FIXED("s1d12",	R8A779A0_CLK_S1D12,	CLK_S1,		12, 1),
111	DEF_FIXED("s3d1",	R8A779A0_CLK_S3D1,	CLK_S3,		1, 1),
112	DEF_FIXED("s3d2",	R8A779A0_CLK_S3D2,	CLK_S3,		2, 1),
113	DEF_FIXED("s3d4",	R8A779A0_CLK_S3D4,	CLK_S3,		4, 1),
114	DEF_FIXED("zs",		R8A779A0_CLK_ZS,	CLK_PLL1_DIV2,	4, 1),
115	DEF_FIXED("zt",		R8A779A0_CLK_ZT,	CLK_PLL1_DIV2,	2, 1),
116	DEF_FIXED("ztr",	R8A779A0_CLK_ZTR,	CLK_PLL1_DIV2,	2, 1),
117	DEF_FIXED("zr",		R8A779A0_CLK_ZR,	CLK_PLL1_DIV2,	1, 1),
118	DEF_FIXED("cnndsp",	R8A779A0_CLK_CNNDSP,	CLK_PLL5_DIV4,	1, 1),
119	DEF_FIXED("vip",	R8A779A0_CLK_VIP,	CLK_PLL5,	5, 1),
120	DEF_FIXED("adgh",	R8A779A0_CLK_ADGH,	CLK_PLL5_DIV4,	1, 1),
121	DEF_FIXED("icu",	R8A779A0_CLK_ICU,	CLK_PLL5_DIV4,	2, 1),
122	DEF_FIXED("icud2",	R8A779A0_CLK_ICUD2,	CLK_PLL5_DIV4,	4, 1),
123	DEF_FIXED("vcbus",	R8A779A0_CLK_VCBUS,	CLK_PLL5_DIV4,	1, 1),
124	DEF_FIXED("cbfusa",	R8A779A0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),
125	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),
126	DEF_FIXED("cl16mck",	R8A779A0_CLK_CL16MCK,	CLK_PLL1_DIV2,	64, 1),
127
128	DEF_GEN4_SDH("sd0h",	R8A779A0_CLK_SD0H,	CLK_SDSRC,	   CPG_SD0CKCR),
129	DEF_GEN4_SD("sd0",	R8A779A0_CLK_SD0,	R8A779A0_CLK_SD0H, CPG_SD0CKCR),
130
131	DEF_BASE("rpc",		R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
132	DEF_BASE("rpcd2",	R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
133		 R8A779A0_CLK_RPC),
134
135	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	CPG_MSOCKCR),
136	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	CPG_CANFDCKCR),
137	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,	CLK_PLL5_DIV4,	CPG_CSICKCR),
138	DEF_DIV6P1("dsi",	R8A779A0_CLK_DSI,	CLK_PLL5_DIV4,	CPG_DSIEXTCKCR),
139
140	DEF_GEN4_OSC("osc",	R8A779A0_CLK_OSC,	CLK_EXTAL,	8),
141	DEF_GEN4_MDSEL("r",	R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
142};
143
144static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
145	DEF_MOD("3dge",		  0,	R8A779A0_CLK_ZG),
146	DEF_MOD("isp0",		 16,	R8A779A0_CLK_S1D1),
147	DEF_MOD("isp1",		 17,	R8A779A0_CLK_S1D1),
148	DEF_MOD("isp2",		 18,	R8A779A0_CLK_S1D1),
149	DEF_MOD("isp3",		 19,	R8A779A0_CLK_S1D1),
150	DEF_MOD("avb0",		211,	R8A779A0_CLK_S3D2),
151	DEF_MOD("avb1",		212,	R8A779A0_CLK_S3D2),
152	DEF_MOD("avb2",		213,	R8A779A0_CLK_S3D2),
153	DEF_MOD("avb3",		214,	R8A779A0_CLK_S3D2),
154	DEF_MOD("avb4",		215,	R8A779A0_CLK_S3D2),
155	DEF_MOD("avb5",		216,	R8A779A0_CLK_S3D2),
156	DEF_MOD("canfd0",	328,	R8A779A0_CLK_S3D2),
157	DEF_MOD("csi40",	331,	R8A779A0_CLK_CSI0),
158	DEF_MOD("csi41",	400,	R8A779A0_CLK_CSI0),
159	DEF_MOD("csi42",	401,	R8A779A0_CLK_CSI0),
160	DEF_MOD("csi43",	402,	R8A779A0_CLK_CSI0),
161	DEF_MOD("du",		411,	R8A779A0_CLK_S3D1),
162	DEF_MOD("dsi0",		415,	R8A779A0_CLK_DSI),
163	DEF_MOD("dsi1",		416,	R8A779A0_CLK_DSI),
164	DEF_MOD("fcpvd0",	508,	R8A779A0_CLK_S3D1),
165	DEF_MOD("fcpvd1",	509,	R8A779A0_CLK_S3D1),
166	DEF_MOD("hscif0",	514,	R8A779A0_CLK_S1D2),
167	DEF_MOD("hscif1",	515,	R8A779A0_CLK_S1D2),
168	DEF_MOD("hscif2",	516,	R8A779A0_CLK_S1D2),
169	DEF_MOD("hscif3",	517,	R8A779A0_CLK_S1D2),
170	DEF_MOD("i2c0",		518,	R8A779A0_CLK_S1D4),
171	DEF_MOD("i2c1",		519,	R8A779A0_CLK_S1D4),
172	DEF_MOD("i2c2",		520,	R8A779A0_CLK_S1D4),
173	DEF_MOD("i2c3",		521,	R8A779A0_CLK_S1D4),
174	DEF_MOD("i2c4",		522,	R8A779A0_CLK_S1D4),
175	DEF_MOD("i2c5",		523,	R8A779A0_CLK_S1D4),
176	DEF_MOD("i2c6",		524,	R8A779A0_CLK_S1D4),
177	DEF_MOD("ispcs0",	612,	R8A779A0_CLK_S1D1),
178	DEF_MOD("ispcs1",	613,	R8A779A0_CLK_S1D1),
179	DEF_MOD("ispcs2",	614,	R8A779A0_CLK_S1D1),
180	DEF_MOD("ispcs3",	615,	R8A779A0_CLK_S1D1),
181	DEF_MOD("msi0",		618,	R8A779A0_CLK_MSO),
182	DEF_MOD("msi1",		619,	R8A779A0_CLK_MSO),
183	DEF_MOD("msi2",		620,	R8A779A0_CLK_MSO),
184	DEF_MOD("msi3",		621,	R8A779A0_CLK_MSO),
185	DEF_MOD("msi4",		622,	R8A779A0_CLK_MSO),
186	DEF_MOD("msi5",		623,	R8A779A0_CLK_MSO),
187	DEF_MOD("pwm0",		628,	R8A779A0_CLK_S1D8),
188	DEF_MOD("rpc-if",	629,	R8A779A0_CLK_RPCD2),
189	DEF_MOD("scif0",	702,	R8A779A0_CLK_S1D8),
190	DEF_MOD("scif1",	703,	R8A779A0_CLK_S1D8),
191	DEF_MOD("scif3",	704,	R8A779A0_CLK_S1D8),
192	DEF_MOD("scif4",	705,	R8A779A0_CLK_S1D8),
193	DEF_MOD("sdhi0",	706,	R8A779A0_CLK_SD0),
194	DEF_MOD("sys-dmac1",	709,	R8A779A0_CLK_S1D2),
195	DEF_MOD("sys-dmac2",	710,	R8A779A0_CLK_S1D2),
196	DEF_MOD("tmu0",		713,	R8A779A0_CLK_CL16MCK),
197	DEF_MOD("tmu1",		714,	R8A779A0_CLK_S1D4),
198	DEF_MOD("tmu2",		715,	R8A779A0_CLK_S1D4),
199	DEF_MOD("tmu3",		716,	R8A779A0_CLK_S1D4),
200	DEF_MOD("tmu4",		717,	R8A779A0_CLK_S1D4),
201	DEF_MOD("tpu0",		718,	R8A779A0_CLK_S1D8),
202	DEF_MOD("vin00",	730,	R8A779A0_CLK_S1D1),
203	DEF_MOD("vin01",	731,	R8A779A0_CLK_S1D1),
204	DEF_MOD("vin02",	800,	R8A779A0_CLK_S1D1),
205	DEF_MOD("vin03",	801,	R8A779A0_CLK_S1D1),
206	DEF_MOD("vin04",	802,	R8A779A0_CLK_S1D1),
207	DEF_MOD("vin05",	803,	R8A779A0_CLK_S1D1),
208	DEF_MOD("vin06",	804,	R8A779A0_CLK_S1D1),
209	DEF_MOD("vin07",	805,	R8A779A0_CLK_S1D1),
210	DEF_MOD("vin10",	806,	R8A779A0_CLK_S1D1),
211	DEF_MOD("vin11",	807,	R8A779A0_CLK_S1D1),
212	DEF_MOD("vin12",	808,	R8A779A0_CLK_S1D1),
213	DEF_MOD("vin13",	809,	R8A779A0_CLK_S1D1),
214	DEF_MOD("vin14",	810,	R8A779A0_CLK_S1D1),
215	DEF_MOD("vin15",	811,	R8A779A0_CLK_S1D1),
216	DEF_MOD("vin16",	812,	R8A779A0_CLK_S1D1),
217	DEF_MOD("vin17",	813,	R8A779A0_CLK_S1D1),
218	DEF_MOD("vin20",	814,	R8A779A0_CLK_S1D1),
219	DEF_MOD("vin21",	815,	R8A779A0_CLK_S1D1),
220	DEF_MOD("vin22",	816,	R8A779A0_CLK_S1D1),
221	DEF_MOD("vin23",	817,	R8A779A0_CLK_S1D1),
222	DEF_MOD("vin24",	818,	R8A779A0_CLK_S1D1),
223	DEF_MOD("vin25",	819,	R8A779A0_CLK_S1D1),
224	DEF_MOD("vin26",	820,	R8A779A0_CLK_S1D1),
225	DEF_MOD("vin27",	821,	R8A779A0_CLK_S1D1),
226	DEF_MOD("vin30",	822,	R8A779A0_CLK_S1D1),
227	DEF_MOD("vin31",	823,	R8A779A0_CLK_S1D1),
228	DEF_MOD("vin32",	824,	R8A779A0_CLK_S1D1),
229	DEF_MOD("vin33",	825,	R8A779A0_CLK_S1D1),
230	DEF_MOD("vin34",	826,	R8A779A0_CLK_S1D1),
231	DEF_MOD("vin35",	827,	R8A779A0_CLK_S1D1),
232	DEF_MOD("vin36",	828,	R8A779A0_CLK_S1D1),
233	DEF_MOD("vin37",	829,	R8A779A0_CLK_S1D1),
234	DEF_MOD("vspd0",	830,	R8A779A0_CLK_S3D1),
235	DEF_MOD("vspd1",	831,	R8A779A0_CLK_S3D1),
236	DEF_MOD("rwdt",		907,	R8A779A0_CLK_R),
237	DEF_MOD("cmt0",		910,	R8A779A0_CLK_R),
238	DEF_MOD("cmt1",		911,	R8A779A0_CLK_R),
239	DEF_MOD("cmt2",		912,	R8A779A0_CLK_R),
240	DEF_MOD("cmt3",		913,	R8A779A0_CLK_R),
241	DEF_MOD("pfc0",		915,	R8A779A0_CLK_CP),
242	DEF_MOD("pfc1",		916,	R8A779A0_CLK_CP),
243	DEF_MOD("pfc2",		917,	R8A779A0_CLK_CP),
244	DEF_MOD("pfc3",		918,	R8A779A0_CLK_CP),
245	DEF_MOD("tsc",		919,	R8A779A0_CLK_CL16MCK),
246	DEF_MOD("vspx0",	1028,	R8A779A0_CLK_S1D1),
247	DEF_MOD("vspx1",	1029,	R8A779A0_CLK_S1D1),
248	DEF_MOD("vspx2",	1030,	R8A779A0_CLK_S1D1),
249	DEF_MOD("vspx3",	1031,	R8A779A0_CLK_S1D1),
250	DEF_MOD("fcpvx0",	1100,	R8A779A0_CLK_S1D1),
251	DEF_MOD("fcpvx1",	1101,	R8A779A0_CLK_S1D1),
252	DEF_MOD("fcpvx2",	1102,	R8A779A0_CLK_S1D1),
253	DEF_MOD("fcpvx3",	1103,	R8A779A0_CLK_S1D1),
254};
255
256static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
257	MOD_CLK_ID(907),	/* RWDT */
258};
259
260/*
261 * CPG Clock Data
262 */
263/*
264 *   MD	 EXTAL		PLL1	PLL20	PLL30	PLL4	PLL5	OSC
265 * 14 13 (MHz)			   21	   31
266 * ----------------------------------------------------------------
267 * 0  0	 16.66 x 1	x128	x216	x128	x144	x192	/16
268 * 0  1	 20    x 1	x106	x180	x106	x120	x160	/19
269 * 1  0	 Prohibited setting
270 * 1  1	 33.33 / 2	x128	x216	x128	x144	x192	/32
271 */
272#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
273					 (((md) & BIT(13)) >> 13))
274static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {
275	/* EXTAL div	PLL1 mult/div	PLL5 mult/div	OSC prediv */
276	{ 1,		128,	1,	192,	1,	16,	},
277	{ 1,		106,	1,	160,	1,	19,	},
278	{ 0,		0,	0,	0,	0,	0,	},
279	{ 2,		128,	1,	192,	1,	32,	},
280};
281
282static int __init r8a779a0_cpg_mssr_init(struct device *dev)
283{
284	const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
285	u32 cpg_mode;
286	int error;
287
288	error = rcar_rst_read_mode_pins(&cpg_mode);
289	if (error)
290		return error;
291
292	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
293
294	return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
295}
296
297const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
298	/* Core Clocks */
299	.core_clks = r8a779a0_core_clks,
300	.num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
301	.last_dt_core_clk = LAST_DT_CORE_CLK,
302	.num_total_core_clks = MOD_CLK_BASE,
303
304	/* Module Clocks */
305	.mod_clks = r8a779a0_mod_clks,
306	.num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
307	.num_hw_mod_clks = 15 * 32,
308
309	/* Critical Module Clocks */
310	.crit_mod_clks		= r8a779a0_crit_mod_clks,
311	.num_crit_mod_clks	= ARRAY_SIZE(r8a779a0_crit_mod_clks),
312
313	/* Callbacks */
314	.init = r8a779a0_cpg_mssr_init,
315	.cpg_clk_register = rcar_gen4_cpg_clk_register,
316
317	.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
318};