clk-vbattb.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * VBATTB clock driver
  4 *
  5 * Copyright (C) 2024 Renesas Electronics Corp.
  6 */
  7
  8#include <linux/cleanup.h>
  9#include <linux/clk-provider.h>
 10#include <linux/device.h>
 11#include <linux/io.h>
 12#include <linux/mod_devicetable.h>
 13#include <linux/of.h>
 14#include <linux/platform_device.h>
 15#include <linux/pm_runtime.h>
 16#include <linux/reset.h>
 17
 18#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
 19
 20#define VBATTB_BKSCCR			0x1c
 21#define VBATTB_BKSCCR_SOSEL		6
 22#define VBATTB_SOSCCR2			0x24
 23#define VBATTB_SOSCCR2_SOSTP2		0
 24#define VBATTB_XOSCCR			0x30
 25#define VBATTB_XOSCCR_OUTEN		16
 26#define VBATTB_XOSCCR_XSEL		GENMASK(1, 0)
 27#define VBATTB_XOSCCR_XSEL_4_PF		0x0
 28#define VBATTB_XOSCCR_XSEL_7_PF		0x1
 29#define VBATTB_XOSCCR_XSEL_9_PF		0x2
 30#define VBATTB_XOSCCR_XSEL_12_5_PF	0x3
 31
 32/**
 33 * struct vbattb_clk - VBATTB clock data structure
 34 * @base: base address
 35 * @lock: lock
 36 */
 37struct vbattb_clk {
 38	void __iomem *base;
 39	spinlock_t lock;
 40};
 41
 42static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc)
 43{
 44	switch (of_lc) {
 45	case 4000:
 46		*reg_lc = VBATTB_XOSCCR_XSEL_4_PF;
 47		break;
 48	case 7000:
 49		*reg_lc = VBATTB_XOSCCR_XSEL_7_PF;
 50		break;
 51	case 9000:
 52		*reg_lc = VBATTB_XOSCCR_XSEL_9_PF;
 53		break;
 54	case 12500:
 55		*reg_lc = VBATTB_XOSCCR_XSEL_12_5_PF;
 56		break;
 57	default:
 58		return -EINVAL;
 59	}
 60
 61	return 0;
 62}
 63
 64static void vbattb_clk_action(void *data)
 65{
 66	struct device *dev = data;
 67	struct reset_control *rstc = dev_get_drvdata(dev);
 68	int ret;
 69
 70	ret = reset_control_assert(rstc);
 71	if (ret)
 72		dev_err(dev, "Failed to de-assert reset!");
 73
 74	ret = pm_runtime_put_sync(dev);
 75	if (ret < 0)
 76		dev_err(dev, "Failed to runtime suspend!");
 77
 78	of_clk_del_provider(dev->of_node);
 79}
 80
 81static int vbattb_clk_probe(struct platform_device *pdev)
 82{
 83	struct device_node *np = pdev->dev.of_node;
 84	struct clk_parent_data parent_data = {};
 85	struct clk_hw_onecell_data *clk_data;
 86	const struct clk_hw *parent_hws[2];
 87	struct device *dev = &pdev->dev;
 88	struct reset_control *rstc;
 89	struct vbattb_clk *vbclk;
 90	u32 of_lc, reg_lc;
 91	struct clk_hw *hw;
 92	/* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBATTCLK. */
 93	u8 num_clks = 4;
 94	int ret;
 95
 96	/* Default to 4pF as this is not needed if external clock device is connected. */
 97	of_lc = 4000;
 98	of_property_read_u32(np, "quartz-load-femtofarads", &of_lc);
 99
100	ret = vbattb_clk_validate_load_capacitance(&reg_lc, of_lc);
101	if (ret)
102		return ret;
103
104	vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL);
105	if (!vbclk)
106		return -ENOMEM;
107
108	clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_KERNEL);
109	if (!clk_data)
110		return -ENOMEM;
111	clk_data->num = num_clks;
112
113	vbclk->base = devm_platform_ioremap_resource(pdev, 0);
114	if (IS_ERR(vbclk->base))
115		return PTR_ERR(vbclk->base);
116
117	ret = devm_pm_runtime_enable(dev);
118	if (ret)
119		return ret;
120
121	rstc = devm_reset_control_get_shared(dev, NULL);
122	if (IS_ERR(rstc))
123		return PTR_ERR(rstc);
124
125	ret = pm_runtime_resume_and_get(dev);
126	if (ret)
127		return ret;
128
129	ret = reset_control_deassert(rstc);
130	if (ret) {
131		pm_runtime_put_sync(dev);
132		return ret;
133	}
134
135	dev_set_drvdata(dev, rstc);
136	ret = devm_add_action_or_reset(dev, vbattb_clk_action, dev);
137	if (ret)
138		return ret;
139
140	spin_lock_init(&vbclk->lock);
141
142	parent_data.fw_name = "rtx";
143	hw = devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0,
144						   vbclk->base + VBATTB_SOSCCR2,
145						   VBATTB_SOSCCR2_SOSTP2,
146						   CLK_GATE_SET_TO_DISABLE, &vbclk->lock);
147	if (IS_ERR(hw))
148		return PTR_ERR(hw);
149	clk_data->hws[VBATTB_XC] = hw;
150
151	hw = devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0, 1, 1);
152	if (IS_ERR(hw))
153		return PTR_ERR(hw);
154	clk_data->hws[VBATTB_XBYP] = hw;
155
156	parent_hws[0] = clk_data->hws[VBATTB_XC];
157	parent_hws[1] = clk_data->hws[VBATTB_XBYP];
158	hw = devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0,
159						 vbclk->base + VBATTB_BKSCCR,
160						 VBATTB_BKSCCR_SOSEL,
161						 1, 0, &vbclk->lock);
162	if (IS_ERR(hw))
163		return PTR_ERR(hw);
164	clk_data->hws[VBATTB_MUX] = hw;
165
166	/* Set load capacitance before registering the VBATTCLK clock. */
167	scoped_guard(spinlock, &vbclk->lock) {
168		u32 val = readl_relaxed(vbclk->base + VBATTB_XOSCCR);
169
170		val &= ~VBATTB_XOSCCR_XSEL;
171		val |= reg_lc;
172		writel_relaxed(val, vbclk->base + VBATTB_XOSCCR);
173	}
174
175	/* This feeds the RTC counter clock and it needs to stay on. */
176	hw = devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CRITICAL,
177						 vbclk->base + VBATTB_XOSCCR,
178						 VBATTB_XOSCCR_OUTEN, 0,
179						 &vbclk->lock);
180
181	if (IS_ERR(hw))
182		return PTR_ERR(hw);
183	clk_data->hws[VBATTB_VBATTCLK] = hw;
184
185	return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
186}
187
188static const struct of_device_id vbattb_clk_match[] = {
189	{ .compatible = "renesas,r9a08g045-vbattb" },
190	{ /* sentinel */ }
191};
192MODULE_DEVICE_TABLE(of, vbattb_clk_match);
193
194static struct platform_driver vbattb_clk_driver = {
195	.driver		= {
196		.name	= "renesas-vbattb-clk",
197		.of_match_table = vbattb_clk_match,
198	},
199	.probe = vbattb_clk_probe,
200};
201module_platform_driver(vbattb_clk_driver);
202
203MODULE_DESCRIPTION("Renesas VBATTB Clock Driver");
204MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
205MODULE_LICENSE("GPL");